DETAILED ACTION
Specification
1. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. (Notably, the specification amendment should be filed separately from the remarks).
Claim Rejections - 35 USC § 102
2. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
3. Claim(s) 1 – 4, 18, 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (9165993).
With regard to claim 1, Kim discloses a display device (for example, see fig. 11) comprising:
a first capacitor electrode (114-1) disposed on a substrate (101);
a second capacitor electrode (116-1) disposed on the first capacitor electrode (114-1) and constituting a first capacitor (Cst1) together with the first capacitor electrode (114-1);
a third capacitor electrode (118-1) disposed on the second capacitor electrode (116-1) and constituting a second capacitor (Cst2) together with the second capacitor electrode (116-1);
a first voltage line (the driving voltage line PL including the connection wiring 120. Therefore. the connection wiring 120 functioning as first voltage line; for example, see column 12, lines 64, 65) including a first portion (referred to as “120A” by examiner’s annotation shown in fig. 11 below) and a second portion (referred to as “120B” by examiner’s annotation shown in fig. 11 below) spaced apart from the first and second capacitors (Cst1, Cst2) in a plan view (a cross-sectional view including a plan view); and
a first bridge pattern (117) wherein the first portion (120A) of the first voltage line (120) is electrically connected (electrically connected via the contact via Cnt3) to an end portion (referred to as “117A” by examiner’s annotation shown in fig. 11 below) of the first bridge pattern (117), the second portion (120B) of the first voltage line (120) is electrically connected (electrically connected via the contact via Cnt3) to another end portion (referred to as “117B” by examiner’s annotation shown in fig. 11 below) of the first bridge pattern (117),
wherein the first voltage line (120) and the third capacitor electrode (118-1) are disposed in different layers (layers 120, 118-1 are in different levels functioning as different layers), and the first bridge pattern (117) and the first voltage line (120) are disposed in different layers (layers 117, 120 are in different levels functioning as different layers).
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With regard to claim 2, Kim discloses the first capacitor (Cst1) is a storage capacitor, and the second capacitor (Cst2) functioning as a hold capacitor (Although the applicant uses terms different to those of Kim to label/describe the claimed invention, this does not result in any structural difference between the claimed invention and the prior art. The use different terminology to describe the plurality of elements that constitute an integrated circuit as this is just a writing style and the way in which a structural limitation is expressed does not affect the configuration of the described elements.).
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With regard to claim 3, Kim discloses the first, second, and third capacitor electrodes (114-1, 116-1, 118-1) overlap with each other in a plan view (a cross-sectional view including a plan view).
With regard to claim 4, Kim discloses the first voltage line (120) functioning as a common voltage line to which a common voltage (a driving voltage) is applied. (the driving voltage line PL including the connection wiring 120. Therefore. the connection wiring 120 functioning as first voltage line for left and right capacitors Cst1, Cst2; for example, see column 12, lines 64, 65).
With regard to claim 18, Kim discloses a display device (for example, see fig. 11) comprising:
a first capacitor electrode (114-1) disposed on a substrate (101);
a second capacitor electrode (116-1) disposed on the first capacitor electrode (114-1) and constituting a first capacitor (Cst1) together with the first capacitor electrode (114-1);
a third capacitor electrode (118-1) disposed on the second capacitor electrode (116-1) and constituting a second capacitor (Cst2) together with the second capacitor electrode (116-1);
a first voltage line (the driving voltage line PL including the connection wiring 120 connected to the conductive via hole line Cnt3. Therefore. the conductive via hole line Cnt3 functioning as first voltage line; for example, see column 12, lines 64, 65) including a first portion (referred to as “Cnt3A” by examiner’s annotation shown in fig. 11 below) and a second portion (referred to as “Cnt3B” by examiner’s annotation shown in fig. 11 below) spaced apart from the first and second capacitors (Cst1, Cst2) in a plan view (a cross-sectional view including a plan view); each of the first portion (Cnt3A) and the second portion (Cnt3B) extending in a first direction (a vertical direction functioning as a first direction); and
a first bridge pattern (referred to as “120C” by examiner’s annotation shown in fig. 11 below; wherein the first bridge pattern 120C is a portion of the conductive line 120) spaced apart from the first and second capacitors (Cst1, Cst2) in a plan view (a cross-sectional view including a plan view) in a second direction (a horizontal direction functioning as a second direction) intersecting the first direction (the vertical direction), wherein the first portion (Cnt3A) of the first voltage line (Cnt3A) is electrically connected to an end portion (referred to as “120C1” by examiner’s annotation shown in fig. 11 below) of the first bridge pattern (120C), the second portion (Cnt3B) of the first voltage line (Cnt3) is electrically connected to another end portion (referred to as “120C2” by examiner’s annotation shown in fig. 11 below) of the first bridge pattern (120C),
wherein the first voltage line (Cnt3) and the third capacitor electrode (118-1) are disposed in different layers (different layers Cnt3, 118-1), and the first bridge pattern (120C) and the first voltage line (Cnt3) are disposed in different layers (the first bridge pattern 120C forming in the layer PVL; while the first voltage line Cnt3 forming in the layer GI3, ILD. Therefore, the layer PVL and GI3, ILD functioning as different layers).
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With regard to claim 19, Kim discloses the first voltage line (Cnt3) functioning as a common voltage line (shared voltage for left and right capacitors Cst1, Cst2) to which a common voltage (a common voltage from the driving voltage line PL for left and right capacitors Cst1, Cst2; for example, see column 12, lines 64, 65) is applied.
Claim Rejections - 35 USC § 103
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (9165993) in view of Cheng et al. (8384837).
With regard to claim 5, Kim does not clearly disclose the first pattern has a C shape in a plan view.
However, Cheng et al. disclose the first pattern (40) has a C shape in a plan view. (the common line, functioning as the first voltage pattern, has a "C" shape). (for example, see column 7, lines 15, 16).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Kim’s device to have the first pattern has a C shape in a plan view as taught by Cheng et al. in order to enhance a high capacitance efficiency of the capacitor for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
6. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (9165993) in view of Shin et al. (9966004).
With regard to claim 6, Kim discloses the first bridge pattern (117) including a metal having low resistance (the bridge pattern 117 is a portion of the gate line GL2; for example, see column 10, lines 17, 18), but Kim does not clearly disclose the first voltage line includes a metal having low resistance.
However, Shin et al. disclose the first voltage line (173R2, or 173G2, or 173B2) includes a metal having low resistance. (for example, see column 10, lines 40 - 44).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Kim’s device to have the first voltage line includes a metal having low resistance in a plan view as taught by Shin et al. in order to enhance a low resistance of the conductive wiring for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
7. Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (9165993) in view of Kwon et al. (9627462) and further in view of Wang et al. (2021/0265441).
With regard to claim 12, Kim does not clearly disclose a lower layer disposed on the substrate; an active layer disposed on the lower layer; a lower gate electrode disposed on the active layer; an upper gate electrode disposed on the lower gate electrode; a lower connection electrode disposed on the upper gate electrode; and an upper connection electrode disposed on the lower connection electrode.
However, Kwon et al. disclose a lower layer (1660) disposed on the substrate (1110); an active layer (1132) disposed on the lower layer (1660); a lower gate electrode (1131) disposed on the active layer (1132); an upper gate electrode (referred to as “1122A” by examiner’s annotation shown in fig. 10 below; a portion electrode 1122A is directly connected to the gate electrode 1131, functioning as an upper gate electrode) disposed on the lower gate electrode (1131); a lower connection electrode (referred to as “1122B” by examiner’s annotation shown in fig. 10 below) disposed on the upper gate electrode (1122A); and an upper connection electrode (an electrode 1134 functioning as an upper connection electrode) disposed on the lower connection electrode (1131).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Kim’s device to have a lower metal layer disposed on the substrate; an active layer disposed on the lower metal layer and including a metal oxide semiconductor; a lower gate electrode disposed on the active layer; an upper gate electrode disposed on the lower gate electrode; a lower connection electrode disposed on the upper gate electrode; and an upper connection electrode disposed on the lower connection electrode as taught by Kwon et al. in order to enhance a high capacitance efficiency of the capacitor for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
Kim and Kwon et al. do not clearly disclose the lower layer made of a metal material and an active layer including a metal oxide semiconductor.
However, Wang et al. disclose the lower layer (1) made of a metal material and an active layer (2) including a metal oxide semiconductor. (for example, see paragraphs [0044], [0046], fig. 7).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Kim and Kwon et al.’s device to have the lower layer made of a metal material and an active layer including a metal oxide semiconductor as taught by Wang et al. in order to enhance a high electron mobility efficiency of the channel and enhance a high light efficiency for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
8. Claims 15, 16 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (9165993) in view of Kwon et al. (9627462) and Wang et al. (2021/0265441) and further in view of Lee et al. (11283042).
With regard to claims 15, 16, Wang et al. disclose a light emitting element including a pixel electrode (11), a light emitting layer (13), and a common electrode (14) sequentially disposed on the upper connection electrode (referred to as “7A” by examiner’s annotation shown in fig. 7 below), wherein the light emitting layer (13) includes a light emitting material,
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Kim, Kwon et al. and Wang et al. do not clearly disclose a plurality of quantum dots dispersed in the light emitting material (137) wherein a light blocking layer disposed on the light emitting element and including an opening overlapping the light emitting layer in a plan view; and a color filter disposed in the opening.
However, Lee et al. disclose a plurality of quantum dots (for example, see column 4, lines 15 – 17) dispersed in the light emitting material wherein a light blocking layer (164) disposed on the light emitting element (E) and including an opening (referred to as “OP” by examiner’s annotation shown in fig. 2 below) overlapping the light emitting layer (137) in a plan view (a cross-sectional view including a plan view); and a color filter (162) disposed in the opening.
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Kim, Kwon et al. and Wang et al.’s device to have a plurality of quantum dots dispersed in the light emitting material wherein a light blocking layer disposed on the light emitting element and including an opening overlapping the light emitting layer in a plan view; and a color filter disposed in the opening as taught by Lee et al. in order to enhance a high light efficiency of the semiconductor device for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
9. Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (9165993) in view of Kwon et al. (9627462) and Wang et al. (2021/0265441) and further in view of Funaya et al. (10157974).
With regard to claim 17, Kwon et al. disclose a first via insulating layer (1113) covering (covering the bottom surface) the lower connection electrode (1122B); and a second via insulating layer (1114) disposed on the first via insulating layer (1113) and covering (covering the bottom surface) the upper connection electrode (1134).
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Kim, Kwon et al. and Wang et al. do not clearly disclose each of the first insulating layer and the second insulating layer includes photosensitive polyimide.
However, Funaya et al. disclose each of the first insulating layer (PI1) and the second insulating layer (PI1) includes photosensitive polyimide. (for example, see column 11, lines 58, 59; and column 12, lines 8, 9, fig. 11, 25).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the Kim, Kwon et al. and Wang et al.’s device to have each of the first insulating layer and the second insulating layer includes photosensitive polyimide as taught by Funaya et al. in order to enhance in order to minimize the signal interference for enhancing a stability operation of the semiconductor device, as is known to one of ordinary skill in the art.
Allowable Subject Matter
10. Claims 7 – 11, 13, 14, 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 7 – 11, 13, 14, 20 are allowable over the prior art of record, because none of these references disclose or can be combined to yield the claimed invention such as a second voltage line including a first portion and a second portion spaced apart from the first and second capacitors in a plan view; and a second bridge pattern the first portion of the second voltage line is electrically connected to an end portion of the second bridge pattern, the second portion of the second voltage line is electrically connected to another end portion of the second bridge pattern, wherein the second voltage line and the third capacitor electrode are disposed in different layers, and the second bridge pattern and the second voltage line are disposed in different layers as recited in claim 7, the first capacitor electrode and the lower metal layer are disposed in a same layer, the second capacitor electrode and the lower gate electrode are disposed in a same layer, and the third capacitor electrode and the upper gate electrode are disposed in a same layer as recited in claim 13, the first voltage line and the lower connection electrode are disposed in a same layer, and the first bridge pattern and the upper connection electrode are disposed in a same layer as recited in claim 14, a second voltage line including a first portion and a second portion spaced apart from the first and second capacitors in a plan view, each of the first portion and the second portion of the second voltage line extending in the first direction; and a second bridge pattern spaced apart from the first and second capacitors in a plan view in the second direction, the first portion of the second voltage line is electrically connected to an end portion of
the second bridge pattern, the second portion of the second voltage line is electrically connected to another end portion of the second bridge pattern, wherein the second voltage line includes a reference voltage line to which a reference voltage is applied, the second voltage line and the third capacitor electrode are disposed in different layers, and the second bridge pattern and the second voltage line are disposed in different layers as recited in claim 20.
Response to Arguments
11. Applicant’s arguments filed 04/03/26 have been fully considered but they are not persuasive.
It is argued, at pages of the remarks, that “Kim does not suggest or teach ‘the first portion of the first voltage line is electrically connected to an end portion of the first bridge pattern,
the second portion of the first voltage line is electrically connected to another end portion
of the first bridge pattern’”. However, fig. 11 of Kim does show a first bridge pattern (117) wherein the first portion (120A) of the first voltage line (120) is electrically connected (electrically connected via the contact via Cnt3) to an end portion (referred to as “117A” by examiner’s annotation shown in fig. 11 below) of the first bridge pattern (117), the second portion (120B) of the first voltage line (120) is electrically connected (electrically connected via the contact via Cnt3) to another end portion (referred to as “117B” by examiner’s annotation shown in fig. 11 below) of the first bridge pattern (117). Since claim 1 does not recite the first portion of the first voltage line is directly and electrically connected to an end portion of the first bridge pattern, the second portion of the first voltage line is directly and electrically connected to another end portion
of the first bridge pattern applicant’s claims 1 do not distinguish over Kim reference.
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It is argued, at pages of the remarks, that “Kim does not suggest or teach ‘the first portion of the first voltage line is electrically connected to an end portion of the first bridge pattern, the second portion of the first voltage line is electrically connected to another end portion of the first bridge pattern’”. However, fig. 11 of Kim does show a first bridge pattern (referred to as “120C” by examiner’s annotation shown in fig. 11 below; wherein the first bridge pattern 120C is a portion of the conductive line 120) spaced apart from the first and second capacitors (Cst1, Cst2) in a plan view (a cross-sectional view including a plan view) in a second direction (a horizontal direction functioning as a second direction) intersecting the first direction (the vertical direction), wherein the first portion (Cnt3A) of the first voltage line (Cnt3A) is electrically connected to an end portion (referred to as “120C1” by examiner’s annotation shown in fig. 11 below) of the first bridge pattern (120C), the second portion (Cnt3B) of the first voltage line (Cnt3) is electrically connected to another end portion (referred to as “120C2” by examiner’s annotation shown in fig. 11 below) of the first bridge pattern (120C). Since claim 18 does not recite the first portion of the first voltage line is directly and electrically connected to an end portion of the first bridge pattern, the second portion of the first voltage line is directly and electrically connected to another end portion
of the first bridge pattern applicant’s claims 18 do not distinguish over Kim reference.
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It is argued, at pages of the remarks, that “Applicant does not agree ‘a cross-sectional view as including or encompassing a plan view”. However, a cross-sectional view can be defined as a plane cross-sectional view as including or encompassing a plan view would be considered a reasonable.
Conclusion
12. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
13. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAN N TRAN whose telephone number is (571) 272 - 1923. The examiner can normally be reached on 8:30-5:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached on (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TAN N TRAN/
Primary Examiner, Art Unit 2812
Prosecution Insights