Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-2 are rejected under 35 U.S.C. 103 as being unpatentable over Suzuki et al. US 20040238882 A1 (hereinafter referred to as Suzuki), in view of Mitani et al WO 2019044921 A1 (hereinafter referred to as Mitani).
Regarding claim 1, Suzuki teaches
A field effect transistor (“vertical type MOSFET 101r” para. 0078 FIG. 2B) comprising:
a semiconductor substrate (“semiconductor substrate 1” para. 0056) having a trench (“striped trenches” para. 0071 FIG. 4B and 2B) on an upper surface;
a gate insulating film (“gate oxide film 41” para. 0071) covering an inner surface of the trench;
a gate electrode (“gate electrode 42” para. 0071) disposed inside the trench and being insulated from the semiconductor substrate by the gate insulating film (“gate oxide 41” insulates “gate electrode 42”), wherein
the semiconductor substrate includes:
a source layer (“n-conduction type regions 33 serving as sources” para. 0070 FIG. 2B and 4A) of n-type being in contact with the gate insulating film on a side surface of the trench (“n-conduction type regions 33” are shown in contact with “gate oxide 41” in FIG. 2A);
a body layer (“p-conduction type layer 31 serving as body layer” para. 0069) of p-type located below the source layer and being in contact with the gate insulating film on the side surface of the trench (sides of “gate oxide 41” below “n-conduction type regions 33” are shown in contact with “p-conduction type regions 32” in FIG. 2B);
a plurality of p-type deep layers (“p-conduction type regions 21” para. 0074);
a plurality of n-type deep layers (“n-conduction type regions 22” para. 0074); and
a drift layer (“n.sup.-conduction type layer 11r” para. 0078),
each of the plurality of p-type deep layers protrudes downward from the body layer (“p-conduction type regions 21” protrude downward from “p-conduction type layer 31”), extends from the body layer to a position below a bottom surface of the trench (“p-conduction type layer 31” extend to a position lower than the bottom of the trench with “gate oxide 41”), extends along a first direction that intersects the trench when the semiconductor substrate is viewed from above (the “p-conduction type region 21” extends perpendicularly to the extension of the trench, para. 0071), is disposed to have a spacing portion therebetween in a second direction that is orthogonal to the first direction when the semiconductor substrate is viewed from above (each “p-conduction type region 21” is spaced apart from the other in a direction perpendicular to the extension of the “p-conduction type regions 21”), and is in contact with the gate insulating film on the side surface of the trench and the bottom surface of the trench located below the body layer (trenches project into the “pn column”, para. 0071, so that “p-conduction type regions 21” make contact with the bottom and side surface of “gate oxide 41”),
each of the plurality of n-type deep layers is disposed in the spacing portion and is in contact with the gate insulating film on the side surface of the trench located below the body layer (“n-conduction type regions 22” are between adjacent “p-conduction type regions 21” and contact the bottom and side surface of “gate oxide 41”),
the drift layer is n-type having an n-type impurity concentration lower than an n-type impurity concentration of each of the plurality of n-type deep layers (from “n.sup.--conduction type layer 11r”, “n-conduction type regions 22”, and “n.sup.+-conduction type layer 11”, n.sup--conduction is understood to correspond to a lower concentration of dopants than n-conduction or n.sup.+-conduction, para. 0078), and is in contact with a lower surface of each of the plurality of n-type deep layers (“n-conduction type regions 22” are formed on and in contact with “n.sup.--conduction type layer 11r”, para. 0078),
each of the plurality of p-type deep layers has a shape in which a dimension in a thickness direction of the semiconductor substrate is larger than a dimension in the second direction (FIG. 2B-5A and “p-conduction type regions 21” and “n-conduction type regions 22” being described as having a striped pattern, the examiner understands that the “p-conduction type regions 21” have a greater thickness or height than a width),
each of the plurality of n-type deep layers has a shape in which a dimension in the thickness direction of the semiconductor substrate is larger than a dimension in the second direction (FIG. 2B-5A and “p-conduction type regions 21” and “n-conduction type regions 22” being described as having a striped pattern, the examiner understands that the “n-conduction type regions 22” have a greater thickness or height than a width), and
the plurality of n-type deep layers extend from a lower surface of the body layer (“n-conduction type regions 22” protrude downward from “p-conduction type layer 31”)
However, Suzuki fails to teach the plurality of n-type deep layers extend to a position below a lower surface of each of the plurality of p-type deep layers.
Nevertheless, Mitani teaches
the plurality of n-type deep layers (“first current dispersion layer 13” between “p-type first deep layers 14”, [0022-0023] FIG. 1-3) extend to a position below a lower surface of each of the plurality of p-type deep layers (“The first deep layer 14 is formed shallower than the first current dispersion layer 13. That is, the first deep layer 14 is formed such that the bottom portion is located in the first current dispersion layer 13.” [0025]).
Suzuki and Mitani teach vertical MOSFETs with superjunction structures. The “first current dispersion layer 13” is formed to extend beyond and under the “first deep layers 14” so that narrowing of the current path by the “first deep layer 14” can be suppressed, a depletion layer extending from the first deep layer 14 greatly extends to the n-type layer 12 side, and an increase in on-resistance can be suppressed [0067, 0069]. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that a “first current dispersion layer 13” extending beyond the lower surface of “first deep layers 14” can lower the on-resistance of the transistor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the field-effect transistor in Suzuki with the n-type deep layers and p-type deep layers as taught in Mitani. When the n-type deep layers extend to a position below a lower surface of each of the plurality of p-type deep layers, the depletion layer can extend towards the drift layer and the on-resistance can remain low.
Regarding claim 2, Suzuki modified by Mitani, teaches the field effect transistor according to claim 1, wherein the plurality of n-type deep layers are connected to each other via a region located below the lower surface of each of the plurality of p-type deep layers (“the first current dispersion layer 13 is located between the bottom portion of the first deep layer 14 and the n-type layer 12” such that portions of “the first current dispersion layer 13” between “first deep layers 14” are connected under each “first deep layers 14”, [0069]).
Allowable Subject Matter
Claim 3 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the most relevant prior art Takeuchi WO 2019044922 A1 teaches a “JFET portion 3” having a thickness of 1.5µm and “field block layers 4” having thicknesses of 1.4 µm ([0015-0016}). The “JFET portion 3” is 1.0714 times greater than the “field block layers 4”. Though it may be rounded down to 1.07, Takeuchi does not indicate it may be lesser than 1.07, nor does Takeuchi teach how the difference in depth affects the device performance. Therefore, claim 3 is considered to contain allowable subject matter.
Conclusion
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/ERIC MANUEL MULERO FLORES/ Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898