DETAILED ACTION
This correspondence is in response to the communications received 01/05/2026. Claims 20-25 have been withdrawn. Claims 1-25 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of species A in the reply filed on 01/05/2026 is acknowledged.
Claims 20-25 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 01/05/2026.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 07/19/2023 and 03/15/2024 have been considered by the examiner and made of record in the application file.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, a display apparatus, comprising:
a first electrode ("second conductive pattern 2002") and a second electrode ("third conductive pattern 2003") that are disposed apart from each other on a substrate (100, see Fig. 21);
a first insulating layer (" barrier layer 110") disposed on the substrate and overlapping the first electrode and the second electrode (see Fig. 21);
a third electrode ("sixth conductive pattern 2102") disposed on the first insulating layer and overlapping the first electrode and the second electrode (see Fig. 21);
a second insulating layer ("buffer layer 111") disposed on the first insulating layer and overlapping the third electrode (see Fig. 21);
a fourth electrode ("fourth semiconductor pattern 2204") disposed on the second insulating layer, overlapping the third electrode, and electrically connected to the first electrode (see Fig. 21);
a third insulating layer ("first insulating layer 113") disposed on the second insulating layer and overlapping the fourth electrode (see Fig. 21); and
a fifth electrode ("11-th conductive pattern 2304") disposed on the third insulating layer, overlapping the fourth electrode, and electrically connected to the third electrode (see Fig. 21).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 8, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Cha et al. (US 10,991,783 B2) in view of Isa et al. (US 8,324,018 B2).
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Regarding claim 1, Figs. 1-5 of Cha disclose a display apparatus (“display device 100”, col. 7, line 48), comprising:
a first electrode (“second storage electrode 341”, col. 9, line 43) and a second electrode (“second program electrode 383”, col. 10, line 56) that are disposed apart from each other on a substrate (as seen in Fig. 1, 341 and 383 are disposed apart from each other on “substrate 310”, col. 9, lines 19);
a first insulating layer (“first insulation layer IL1”, col. 9, line 20) disposed on the substrate and overlapping the first electrode and the second electrode (as seen in Fig. 3, IL1 is disposed on 310 and overlapping 341 and 383);
a third electrode (“first connecting pattern 363”, col. 10, lines 12-13, while Cha does not disclose 363 as an electrode, a secondary reference will be used below to define 363 as an electrode) disposed on the first insulating layer and overlapping the first electrode and the second electrode (as seen in Fig. 3, 363 is disposed on IL1 and overlapping 341 and 383);
a second insulating layer (“second insulation layer IL2”, col. 9, line 34) disposed on the first insulating layer and overlapping the third electrode (as seen in Fig. 3, IL2 is disposed on IL1 and overlapping 363);
a fourth electrode (“second connecting pattern 365”, col. 10, line 13, while Cha does not disclose 365 as an electrode, a secondary reference will be used below to define 365 as an electrode) disposed on the second insulating layer, overlapping the third electrode, and electrically connected to the first electrode (as seen in Fig. 3, 365 is disposed on IL2, overlapping 363 and electrically connect to 341 via “third contact hole CH3”, col. 10, line 30, “driving gate electrode 331a”, col. 9, line 36, and “storage capacitor Cst”, col. 9, line 16);
a third insulating layer (“third insulation layer IL3”, col. 9, line 41) disposed on the second insulating layer and overlapping the fourth electrode (as seen in Fig. 3, IL3 is disposed on IL3 and overlapping 383); and
a fifth electrode (“first program electrode 371”, col. 10, lines 62-63) disposed on the third insulating layer, overlapping the fourth electrode, and electrically connected to the third electrode (as seen in Fig. 3, 371 is disposed on IL3, overlapping 365, and electrically connected to 363 via “program capacitor Cpr”, col. 9, line 17, 383, and “eighth contact hole CH8”, col. 11, line 7).
Cha fails to specify “a third electrode; and a fourth electrode”.
However, in a similar field of endeavor, Figs. 1A-1C of Isa teach a third electrode (“a component (also referred to as a pattern) refers to a conductive layer such as a wiring layer, a gate electrode layer, a source electrode layer, or a drain electrode layer”, col. 6, lines 31-33, thus 363 of Cha is an electrode);
a fourth electrode (as discussed above, a pattern may refer to an electrode, thus 365 of Cha is an electrode).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a third electrode; and a fourth electrode” as taught by Isa in the system of Cha for the purpose of defining a shaped conductive layer.
Regarding claim 8, Figs. 1-5 of Cha in combination with Figs. 1A-1C of Isa disclose the display apparatus of claim 1, Figs. 1-5 of Cha further disclose further comprising:
a semiconductor layer (“second active layer 350b”, col. 9, line 56) disposed between the third electrode and the fourth electrode (as seen in Fig. 3, 350b is disposed horizontally between 363 and 365) and including an oxide semiconductor material (“the second active layer 350b and 350c may be formed of polysilicon or an oxide semiconductor”, col. 10, lines 1-3).
Regarding claim 12, Figs. 1-5 of Cha disclose a display apparatus (“display device 100”, col. 7, line 48), comprising:
a first electrode (“second storage electrode 341”, col. 9, line 43) and a second electrode (“pixel electrode 391”, col. 11, line 31) that are disposed apart from each other on a substrate (as seen in Fig. 1, 341 and 391 are disposed apart from each other on “substrate 310”, col. 9, lines 19);
a first insulating layer (“first insulation layer IL1”, col. 9, line 20) disposed on the substrate and overlapping the first electrode and the second electrode (as seen in Fig. 3, IL1 is disposed on 310 and overlapping 341 and 391);
a third electrode (“first connecting pattern 363”, col. 10, lines 12-13, while Cha does not disclose 363 as an electrode, a secondary reference will be used below to define 363 as an electrode) disposed on the first insulating layer and overlapping the first electrode and the second electrode (as seen in Fig. 3, 363 is disposed on IL1 and overlapping 341 and 391);
a second insulating layer (“second insulation layer IL2”, col. 9, line 34) disposed on the first insulating layer and overlapping the third electrode (as seen in Fig. 3, IL2 is disposed on IL1 and overlapping 363);
a fourth electrode (“second program electrode 383”, col. 10, line 56) disposed on the second insulating layer, overlapping the third electrode, and electrically connected to the second electrode (as seen in Fig. 3, 383 is disposed on IL2, overlapping 363 and electrically connected to 391);
a third insulating layer (“third insulation layer IL3”, col. 9, line 41) disposed on the second insulating layer and overlapping the fourth electrode (as seen in Fig. 3, IL3 is disposed on IL3 and overlapping 383);
a fifth electrode (“second connecting pattern 365”, col. 10, line 13, while Cha does not disclose 365 as an electrode, a secondary reference will be used below to define 365 as an electrode) disposed on the third insulating layer, overlapping the third electrode, and electrically connected to the first electrode (as seen in Fig. 3, 365 is electrically connected to 341 via “third contact hole CH3”, col. 10, line 30, “driving gate electrode 331a”, col. 9, line 36, and “storage capacitor Cst”, col. 9, line 16);
a fourth insulating layer (“fourth insulation layer IL4”, col. 9, line 48) disposed on the third insulating layer and overlapping the fifth electrode (as seen in Fig. 3, IL4 is disposed on IL3 and overlapping 365); and
a sixth electrode (“first program electrode 371”, col. 10, lines 62-63) disposed on the fourth insulating layer, overlapping the fifth electrode, and electrically connected to the third electrode (as seen in Fig. 3, 371 is disposed on IL4, overlapping 365 and electrically connected to 363 via “program capacitor Cpr”, col. 9, line 17, 383, and “eighth contact hole CH8”, col. 11, line 7).
Cha fails to specify “a third electrode; and a fourth electrode”.
However, in a similar field of endeavor, Figs. 1A-1C of Isa teach a third electrode (“a component (also referred to as a pattern) refers to a conductive layer such as a wiring layer, a gate electrode layer, a source electrode layer, or a drain electrode layer”, col. 6, lines 31-33, thus 363 of Cha is an electrode);
a fourth electrode (as discussed above, a pattern may refer to an electrode, thus 365 of Cha is an electrode).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a third electrode; and a fourth electrode” as taught by Isa in the system of Cha for the purpose of defining a shaped conductive layer.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Cha et al. (US 10,991,783 B2) in view of Isa et al. (US 8,324,018 B2) in view of Cheng et al. (US 20150214249 A1).
Regarding claim 13, Figs. 1-5 of Cha in combination with Figs. 1A-1C of Isa disclose the display apparatus of claim 12.
Cha in combination with Isa fails to disclose “wherein the fourth electrode includes an oxide semiconductor material.”
However, in a similar field of endeavor, Figs. 2 and 3 of Cheng teach wherein the fourth electrode includes an oxide semiconductor material (“second region 402”, [0035] where “the second region 402 of the oxide active layer constitutes a first electrode plate of the storage capacitor”, [0035], and “For example, the material for oxide active layer may be IGZO (indium gallium zinc oxide), IZO (indium zinc oxide), InSnO (indium tin oxide) and InGaSnO (indium gallium tin oxide)”, [0042]. IGZO, IZO, InSnO, and InGaSnO are known in the art as semiconducting materials, thus as 371 of Cha is also a first plate of a capacitor, 371 can also be made of an oxide semiconductor layer).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein the fourth electrode includes an oxide semiconductor material” as taught by Isa for the purpose of improving adhesion between conductive elements and the active regions made of oxide semiconductor material.
Allowable Subject Matter
Claims 2-7, 9-11, and 14-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art of record does not teach or fairly suggest the X as recited in the claims of the instant application.
Regarding claim 2, the prior art of Cha et al. (US 10,991,783 B2) in combination with Isa et al. (US 8,324,018 B2) discloses a display apparatus but fails to disclose the specific claims of the instant application regarding the geometry of the second electrode relative to the first electrode e.g. “wherein
in a plan view, the second electrode substantially extends in a first direction and has a protrusion protruding in a second direction intersecting the first direction, and
the first electrode is disposed adjacent in the first direction to the protrusion of the second electrode”.
Regarding claim 3, the prior art of Cha et al. (US 10,991,783 B2) in combination with Isa et al. (US 8,324,018 B2) discloses a display apparatus but fails to disclose the specific claims of the instant application regarding the arrangement of the first storage and first hold capacitors relative to the electrodes, the gate of the first transistor, the source of the first transistor, and the power line, e.g. “wherein
the first pixel circuit includes:
a first storage capacitor electrically connected between a gate of the first transistor and a source of the first transistor; and
a first hold capacitor electrically connected between the power line and the source of the first transistor,
a first storage capacitance of the first storage capacitor is a sum of a first capacitance between the first electrode and the third electrode, a second capacitance between the third electrode and the fourth electrode, and a third capacitance between the fourth electrode and the fifth electrode, and
a first hold capacitance of the first hold capacitor is a fourth capacitance between the second electrode and the third electrode”.
Claims 4 and 5 are allowable by virtue of their dependence on claim 3.
Regarding claim 6, the prior art of Cha et al. (US 10,991,783 B2) in combination with Isa et al. (US 8,324,018 B2) discloses a display apparatus but fails to disclose the specific claims of the instant application regarding the arrangement of the first storage and first hold capacitors relative to the electrodes, the gate of the first transistor, the source of the first transistor, and the power line, e.g. “wherein
the pixel circuit includes:
a storage capacitor including a first storage electrode and a second storage electrode, the first storage electrode being electrically connected to a gate of the first transistor, and the second storage electrode being electrically connected to a source of the first transistor; and
a hold capacitor including a first hold electrode and a second hold electrode, the first hold electrode being electrically connected to the power line, and the second hold electrode being electrically connected to the source of the first transistor,
the first storage electrode of the storage capacitor includes the first electrode and the fourth electrode,
the second storage electrode of the storage capacitor includes a portion of the third electrode overlapping the first electrode, and the fifth electrode,
the first hold electrode of the hold capacitor includes the second electrode, and
the second hold electrode of the hold capacitor includes another portion of the third electrode overlapping the second electrode.”
Claim 7 is allowable by virtue of its dependence on claim 6.
Regarding claim 9, the prior art of Cha et al. (US 10,991,783 B2) in combination with Isa et al. (US 8,324,018 B2) discloses a display apparatus but fails to disclose the specific claims of the instant application regarding the geometry of the third electrode, and the connections between the first electrode and the fourth electrode, e.g. “wherein
the third electrode includes an opening exposing at least a portion of the first insulating layer, and
the first electrode is electrically connected to the fourth electrode through a contact hole passing through the opening of the third electrode.”
Claim 10 is allowable by virtue of its dependence on claim 9.
Regarding claim 11, the prior art of Cha et al. (US 10,991,783 B2) in combination with Isa et al. (US 8,324,018 B2) discloses a display apparatus but fails to disclose the specific claims of the instant application regarding the geometry of the fourth electrode, the third electrode, and the fifth electrode, e.g. “wherein
the fourth electrode includes an opening exposing at least a portion of the second insulating layer, and
the third electrode is electrically connected to the fifth electrode through a contact hole passing through the opening of the fourth electrode.
Regarding claim 14, the prior art of Cha et al. (US 10,991,783 B2) in combination with Isa et al. (US 8,324,018 B2) discloses a display apparatus but fails to disclose the specific claims of the instant application regarding the geometry of the second electrode relative to the first electrode e.g. “wherein
in a plan view, the second electrode substantially extends in a first direction and has a protrusion protruding in a second direction intersecting the first direction, and
the first electrode is disposed adjacent in the first direction to the protrusion of the second electrode”.
Regarding claim 15, the prior art of Cha et al. (US 10,991,783 B2) in combination with Isa et al. (US 8,324,018 B2) discloses a display apparatus but fails to disclose the specific claims of the instant application regarding the arrangement of the storage and hold capacitors relative to the electrodes, the gate of the transistor, the source of the transistor, and the power line, e.g. “wherein
the pixel circuit includes:
a storage capacitor including a first storage electrode and a second storage electrode, the first storage electrode being electrically connected to a gate of the transistor, and
the second storage electrode being electrically connected to a source of the transistor; and
a hold capacitor including a first hold electrode and a second hold electrode, the first hold electrode being electrically connected to the power line, and the second hold electrode being electrically connected to the source of the transistor,
the first storage electrode of the storage capacitor includes the first electrode and the fifth electrode,
the second storage electrode of the storage capacitor includes a portion of the third electrode overlapping the first electrode, and the sixth electrode,
the first hold electrode of the hold capacitor includes the second electrode and the fourth electrode, and
the second hold electrode of the hold capacitor includes another portion of the third electrode overlapping the second electrode.”
Regarding claim 16, the prior art of Cha et al. (US 10,991,783 B2) in combination with Isa et al. (US 8,324,018 B2) discloses a display apparatus but fails to disclose the specific claims of the instant application regarding the arrangement of the first storage and first hold capacitors relative to the electrodes, the gate of the first transistor, the source of the first transistor, and the power line, e.g. “wherein
the pixel circuit includes:
a first storage capacitor electrically connected between a gate of the first transistor and a source of the first transistor; and
a first hold capacitor electrically connected between the power line and the source of the first transistor,
a first storage capacitance of the first storage capacitor is a sum of a first capacitance between the first electrode and the third electrode, a second capacitance between the third electrode and the fifth electrode, and a third capacitance between the fifth electrode and the sixth electrode, and
a first hold capacitance of the first hold capacitor is a sum of a fourth capacitance between the second electrode and the third electrode, and a fifth capacitance between the third electrode and the fourth electrode.”
Claims 17 and 18 are allowable by virtue of their dependence on claim 16.
Regarding claim 19, the prior art of Cha et al. (US 10,991,783 B2) in combination with Isa et al. (US 8,324,018 B2) discloses a display apparatus but fails to disclose the specific claims of the instant application regarding the geometry of the third electrode, and the fifth electrode, and arrangement of the connection between the first and fifth electrodes and the arrangement of the connection between the third and the sixth electrodes, e.g. “wherein
the third electrode includes a first opening exposing at least a portion of the first insulating layer,
the fifth electrode includes a second opening exposing at least a portion of the third insulating layer,
the first electrode is electrically connected to the fifth electrode through a first contact hole passing through the first opening of the third electrode, and
the third electrode is electrically connected to the sixth electrode through a second contact hole passing through the second opening of the fifth electrode.”
Conclusion
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/BENJAMIN MICHAEL KUPP/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893