DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species II, claims 1-20, in the reply filed on 12/30/25 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Shin et al. (US 2023/0209928).
Regarding claim 1, Shin discloses a display device comprising:
a display area (110, fig. 1 and paragraph 0040);
a metal line which is connected to the display area, transmits a first signal to the
display area and extends along a first direction (DL, figs. 1, 3-5 and paragraphs 0041, 0061);
a gate line which is connected to the display area, transmits a second signal to the display area and extends along a second direction crossing the first direction (GL, figs. 1, 3-5 and paragraphs 0041, 0061);
the gate line crossing the metal line and defining an opening of the gate line which overlaps the metal line (figs. 4-5); and
a first bridge pattern extending across the opening in the gate line and crossing the metal line, the first bridge pattern contacting the gate line at two contact locations along the gate line (GBL2, figs. 4-5 and paragraphs 11-13, 0119-0123).
Regarding claim 2, Shin further discloses wherein the two contact locations are spaced apart from each other along the second direction, and the opening is defined between the two contact locations, along the second direction (figs. 4-5).
Regarding claim 3, Shin further discloses wherein the gate line includes a first portion and a second portion spaced apart from each other (GBL2, GBL1, fig. 4), and
each of the first portion and the second portion overlaps the metal line (DL1, fig. 4).
Regarding claim 4, Shin further discloses wherein the first portion of the gate line and the second portion of the gate line are spaced apart from each other along the first direction, and the opening is positioned between the first portion and the second portion, along the first direction (fig. 4).
Regarding claim 4, Shin further discloses wherein the first portion and the second
portion of the gate line are spaced apart from the first bridge pattern, along the first direction (fig. 4 and paragraphs 0119-0123).
Regarding claim 6, Shin further discloses a buffer layer on the metal line (111, fig. 5 and paragraph 0070);
an active pattern of a transistor, on the buffer layer (124, fig. 3 and paragraphs 0071-0073);
a gate electrode of the transistor, on the active pattern and overlapping the active
pattern (121, fig. 3 and paragraphs 0071-0073);
a first insulation layer on the gate electrode (paragraphs 0071-0073);
a source electrode and a drain electrode of the transistor which are on the first
insulation layer and connected to the active pattern (122, 123, fig. 3 and paragraphs 0071-0073);
a second insulation layer on the source electrode and the drain electrode; and
a pixel electrode of a light-emitting element, on the second insulation layer and
connected to the transistor (fig. 3 and paragraphs 0071-0080).
Regarding claim 7, Shin further discloses wherein the gate line is in a same layer as the gate electrode (paragraph 0084).
Regarding claim 8, Shin further discloses wherein the first bridge pattern is in a same layer as the source electrode and the drain electrode (paragraph 0121).
Regarding claim 9, Shin further discloses a second bridge pattern in a same layer as the pixel electrode (figs. 3, 4 and paragraphs 0071-0075).
Regarding claim 10, Shin further discloses wherein the second bridge pattern is in a different layer from the first bridge pattern, and connected to the first bridge pattern (paragraph 0121).
Regarding claim 11, Shin further discloses wherein the second bridge pattern is spaced apart from the first portion and the second portion of the gate line, along the first direction (fig. 4 and paragraphs 0119-0123).
Regarding claim 12, Shin further discloses wherein a first hole is defined in the first insulation layer, a second hole overlapping the first hole, is defined in the second insulation layer, and the first hole and the second hole together form a hole portion which exposes the gate line to outside both the first insulation layer and the second insulation layer (figs. 4-5 and paragraphs 0119-0123).
Regarding claim 13, Shin further discloses wherein the hole portion overlaps the gate line at the first portion or the second portion, and is spaced apart from the metal line (figs. 4-5).
Regarding claim 14, Shin further discloses wherein the first bridge pattern is in a same layer as the pixel electrode (figs. 3, 4 and paragraphs 0071-0075).
Regarding claim 15, Shin further discloses a metal pattern (DL2, fig. 4) in a same layer as the metal line (DL1, fig. 4), the metal pattern overlapping the gate line at the first portion or the second portion and spaced apart from the metal line (fig. 4).
Regarding claim 16, Shin further discloses wherein the metal line transmits a data signal to the display area, and the gate line transmits a gate signal to the display area (DL, GL, paragraph 0050).
Regarding claim 17, Shin discloses a display device comprising:
a display area (110, fig. 1 and paragraph 0040);
a metal line which is connected to the display area, transmits a first signal to the
display area and extends along a first direction (DL, figs. 1, 3-5 and paragraphs 0041, 0061);
a gate line which is connected to the display area, transmits a second signal to the display area and extends along a second direction crossing the first direction (GL, figs. 1, 3-5 and paragraphs 0041, 0061);
the gate line crossing the metal line to define two overlapping portions of the gate
line which are spaced apart from each other along the first direction and define a gap of the gate line therebetween (fig. 4); and a bridge pattern extending along the two overlapping portions of the gate line and crossing the metal line, the bridge pattern contacting the gate line at two contact locations along the gate line (GBL1, GBL2, figs. 4-5 and paragraphs 11-13, 0119-0123).
Regarding claim 18, Shin further discloses wherein the two overlapping portions of the gate line meet each other at a front end of the gap and at a rear end of the gap which is opposite to the front end along the second direction (fig. 4).
Regarding claim 19, Shin further discloses wherein the two contact locations are
respectively further from the gap than the front end and the rear end (CH1, fig. 4).
Regarding claim 20, Shin further discloses wherein the two overlapping portions of the gate line are spaced apart from the bridge pattern, along the first direction (figs. 4-5).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Patent Application Publication 2016/0370666 discloses a method of repairing data lines of a display substrate utilizing electrode line bridges.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS M MENZ whose telephone number is (571)272-1877. The examiner can normally be reached Monday-Friday 8:00am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DOUGLAS M MENZ/Primary Examiner, Art Unit 2897 3/30/26
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