Prosecution Insights
Last updated: July 17, 2026
Application No. 18/355,171

COPPER FEATURES AND RELATED METHODS OF FORMING

Non-Final OA §103
Filed
Jul 19, 2023
Examiner
VALENZUELA, PATRICIA D
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Semiconductor Components Industries LLC
OA Round
2 (Non-Final)
90%
Grant Probability
Favorable
2-3
OA Rounds
0m
Est. Remaining
92%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allowance Rate
647 granted / 717 resolved
+22.2% vs TC avg
Minimal +2% lift
Without
With
+2.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
63 currently pending
Career history
794
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
86.7%
+46.7% vs TC avg
§102
4.8%
-35.2% vs TC avg
§112
1.8%
-38.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 717 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after[0062] March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over YALAMANCHILI (USPGPUB DOCUMENT: 2012/0322234, hereinafter[0062] YALAMANCHILI) in view of Pace (USPATENT: 5904499, hereinafter[0062] Pace). Re claim 1 YALAMANCHILI discloses in Fig 1C/4/5 a method of forming a copper feature comprising: providing a copper layer(508/402A/402B); cutting a trench(412) partially through the thickness leaving a remaining thickness using a laser[0033]; and after[0062] cutting, removing the remaining thickness using a water jet[0055]. YALAMANCHILI does not disclose providing a copper layer(508/402A/402B) with a thickness thicker than 1 mm[0023]; Pace disclose providing a copper layer(780) with a thickness thicker than 1 mm[col 15,lines35-50]; It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Pace to the teachings of YALAMANCHILI in order to have high packaging efficiency [col 3, lines 10-20, Pace]. Re claim 2 YALAMANCHILI and Pace disclose the method of claim 1, further comprising coupling the copper layer(508/402A/402B) with a dielectric substrate(505)[0036]. Re claim 3 YALAMANCHILI and Pace disclose the method of claim 2, wherein the dielectric substrate(505)[0036] is comprises one of aluminum oxide or boron nitride. Re claim 4 YALAMANCHILI and Pace disclose the method of claim 1, further comprising: forming a layer over the copper layer(508/402A/402B) prior to laser[0033]ing; and removing[0060 of Pace] the layer after[0062] cutting. Re claim 5 YALAMANCHILI and Pace disclose the method of claim 1, further comprising reducing copper oxide in the copper layer(508/402A/402B) by exposing the copper layer(508/402A/402B) to a forming gas[0055 of Pace]. Re claim 6 YALAMANCHILI and Pace disclose the method of claim 2, wherein the copper layer(508/402A/402B) is a first copper layer(508/402A/402B) and the method further comprises: coupling a second metal layer(13 of YALAMANCHILI) with a thickness thicker than 1 mm[col 15,lines35-50 of Pace]; to the dielectric substrate(505)[0036]; cutting a trench(412)[0046 of Pace] partially through the thickness of the second metal layer(13 of YALAMANCHILI) leaving a remaining thickness of the second metal layer(13 of YALAMANCHILI) using the laser[0033]; and after[0062] laser[0033]ing, cutting through the remaining thickness of the second metal layer(13 of YALAMANCHILI) using the water jet[0047 of Pace]. Re claim 7 YALAMANCHILI and Pace disclose the method of claim 2, wherein the copper layer(508/402A/402B) is a first copper layer(508/402A/402B) and the method further comprises: coupling a heat sink comprising a second metal layer(13 of YALAMANCHILI) with a thickness thicker than 1 mm[col 15,lines35-50 of Pace]; to the dielectric substrate(505)[0036]; cutting a trench(412)[0046 of Pace] partially through the thickness of the second metal layer(13 of YALAMANCHILI) leaving a remaining thickness of the second metal layer(13 of YALAMANCHILI) using the laser[0033]; and after[0062] laser[0033]ing, cutting into the remaining thickness of the second metal layer(13 of YALAMANCHILI) using the water jet[0047 of Pace] to form a fin of the heat sink. Re claim 8 YALAMANCHILI discloses in Fig 1C/4/5 a method of forming a copper feature comprising: providing a copper layer(508/402A/402B); cutting a trench(412) partially through the thickness leaving a remaining thickness using a water jet[0055]; and after[0062] cutting, etching[0038] through the remaining thickness. YALAMANCHILI does not disclose providing a copper layer(508/402A/402B) with a thickness thicker than 1 mm; Pace disclose providing a copper layer(780) with a thickness thicker than 1 mm[col 15,lines35-50 of Pace]; It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Pace to the teachings of YALAMANCHILI in order to have high packaging efficiency [col 3, lines 10-20, Pace]. Re claim 9 YALAMANCHILI and Pace disclose the method of claim 8, further comprising coupling the copper layer(508/402A/402B) with a dielectric substrate(505)[0036]. Re claim 10 YALAMANCHILI and Pace disclose the method of claim 9, wherein the dielectric substrate(505)[0036] is comprises one of aluminum oxide or boron nitride. Re claim 11 YALAMANCHILI and Pace disclose the method of claim 8, further comprising: forming a layer over the copper layer(508/402A/402B) prior to laser[0033]ing; and removing[0060 of Pace] the layer after[0062] etching[0038][0016 of Pace]. Re claim 12 YALAMANCHILI and Pace disclose the method of claim 8, further comprising reducing copper oxide in the copper layer(508/402A/402B) by exposing the copper layer(508/402A/402B) to a forming gas[0055 of Pace]. Re claim 13 YALAMANCHILI and Pace disclose the method of claim 9, wherein the copper layer(508/402A/402B) is a first copper layer(508/402A/402B) and the method further comprises: coupling a second metal layer(13 of YALAMANCHILI) with a thickness thicker than 1 mm[col 15,lines35-50 of Pace]; to the dielectric substrate(505)[0036]; cutting a trench(412)[0046 of Pace] partially through the thickness of the second metal layer(13 of YALAMANCHILI) leaving a remaining thickness of the second metal layer(13 of YALAMANCHILI) using the water jet[0047 of Pace]; and after[0062] cutting, etching[0038][0016 of Pace] through the remaining thickness of the second metal layer(13 of YALAMANCHILI). Re claim 14 YALAMANCHILI and Pace disclose the method of claim 9, wherein the copper layer(508/402A/402B) is a first copper layer(508/402A/402B) and the method further comprises: coupling a heat sink comprising a second metal layer(13 of YALAMANCHILI) with a thickness thicker than 1 mm[col 15,lines35-50 of Pace]; to the dielectric substrate(505)[0036]; and cutting a trench(412)[0046 of Pace] partially through the thickness of the second metal layer(13 of YALAMANCHILI) leaving a remaining thickness of the second metal layer(13 of YALAMANCHILI) using the water jet[0047 of Pace] to form a fin of the heat sink. Re claim 15 YALAMANCHILI discloses in Fig 1C/4/5 a method of forming an insulated copper feature comprising: providing a copper layer(508/402A/402B) comprising a thickness[0023]; forming a plurality of trench(412)es through the thickness; YALAMANCHILI does not disclose permanently filling the plurality of trench(412)es with at least one polymer material immediately after[0062] forming the plurality of trench(412)es. Pace disclose permanently filling the plurality of trenches(trenches within 514) with at least one polymer material immediately after[0062] forming the plurality of trenches[col9, lines 10-25]. It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Pace to the teachings of YALAMANCHILI in order to have high packaging efficiency [col 3, lines 10-20, Pace]. Re claim 16 YALAMANCHILI and Pace disclose the method of claim 15, further comprising coupling the copper layer(508/402A/402B) with a dielectric substrate(505)[0036]. Re claim 17 YALAMANCHILI and Pace disclose the method of claim 15, wherein permanently filling the trench(412)[0046 of Pace]es further comprises printing the at least one polymer material into the plurality of trench(412)[0046 of Pace]es. Re claim 18 YALAMANCHILI and Pace disclose the method of claim 15, wherein the at least one polymer material[0020 of Pace] extends above the thickness of the copper layer(508/402A/402B). Re claim 19 YALAMANCHILI and Pace disclose the method of claim 18, further comprising coupling a thinned semiconductor die to the copper layer(508/402A/402B) where the at least one polymer material extends around one or more edges of the thinned semiconductor die. Re claim 20 YALAMANCHILI and Pace disclose the method of claim 18, further comprising a submodule to the copper layer(508/402A/402B) where the at least one polymer material[0020 of Pace] extends around one or more edges of the submodule. Response to Arguments Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to PATRICIA D VALENZUELA whose telephone number is (571)272-9242. The examiner can normally be reached Monday-Friday 10am-6pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
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Prosecution Timeline

Jul 19, 2023
Application Filed
Nov 10, 2025
Non-Final Rejection mailed — §103
Feb 09, 2026
Response Filed
Jun 03, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
90%
Grant Probability
92%
With Interview (+2.1%)
2y 2m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 717 resolved cases by this examiner. Grant probability derived from career allowance rate.

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