DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chou et al (US Publication No. 2022/0123115)
Regarding claim 1, Chou discloses a method, comprising: forming an epitaxial source/drain region Fig 10D, 82 ¶0042 in a substrate Fig 10D, 50;forming a first inter-layer dielectric Fig 12B, 88 over the epitaxial source/drain region Fig 12B, 82; forming a gate stack Fig 14B, 96 over the substrate and adjacent to the first inter-layer dielectric Fig 14B;forming a gate mask Fig 18B, 100 over the gate stack; forming a source/drain plug Fig 26B, 120 through the first inter-layer dielectric and electrically connected to the epitaxial source/drain region Fig 26B;depositing a dielectric layer Fig 27B, 104 over the gate mask Fig 27B, 100 and the first inter-layer dielectric Fig 27B, the dielectric layer having a different etch selectivity than the gate mask ¶0056-0059;forming a second inter-layer dielectric Fig 27B, 124 over the dielectric layer Fig 27B, 104;forming a gate plug Fig 36B, 132 through the second interlayer dielectric and electrically connected to the gate stack Fig 36B;etching an opening through the second inter-layer dielectric Fig 36B, 124 and the dielectric layer Fig 27B, 104, the opening exposing the source/drain plug and the gate mask Fig 27B; and forming a conductive feature Fig 36B, 134/136 in the opening, the conductive feature being electrically connected to the source/drain plug and gate plug Fig 36B.
Regarding claim 3, Chou discloses forming an additional epitaxial source/drain region Fig 10D, 82 ¶0042 in the substrate; and forming an additional source/drain plug through the first inter-layer dielectric and electrically connected to the additional epitaxial source/drain region Fig 26B, wherein the conductive feature is in physical contact with the source/drain plug and the additional source/drain plug Fig 28B.
Regarding claim 4, Chou discloses forming a gate plug Fig 28B, 132 through the second inter-layer dielectric and electrically connected to the gate stack Fig 28B, wherein forming the conductive feature comprises forming the conductive feature as a butted contact with the gate plug and the source/drain plug Fig 30B.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 9 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Chou et al (US Publication No. 2022/0123115) in view of Chiang et al (US Publication No. 2020/0043732).
Regarding claim 2, Chou discloses wherein forming the gate mask comprises: recessing the gate stack Fig 15B;depositing a dielectric liner over the gate stack Fig 15B; and depositing a nitride layer over the dielectric liner Fig 15B.Chou discloses all the limitations but silent on the material used as a liner over the gate stack. Whereas Chiang discloses depositing a metal dielectric liner Fig 1G, 134 ¶0030 over the gate stack; and depositing a nitride layer Fig 1K, 146 over the metal dielectric liner Fig 1K, 134. Chou and Chiang are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chou because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the mask used by Chou and incorporate the teachings of Chiang since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of design choice. In re Leshin, 125 USPQ 416 (1960).
Regarding claim 9, Chou discloses a method, comprising: forming a first epitaxial region Fig 10D, 82 ¶0042 and a second epitaxial region Fig 10D, 82 ¶0042 in a substrate Fig 10D, 50; forming a first oxide layer over the first epitaxial region and the second epitaxial region ¶0047; forming a first gate stack Fig 14B, 96 and a second gate stack Fig 14B, 96 over the substrate Fig 14B, 50, the first gate stack being interposed between the first epitaxial region and the second epitaxial region Fig 14B; forming a nitride mask Fig 18B, 100 over the first gate stack; etching the first oxide layer ¶0047 to expose the first epitaxial region and the second epitaxial region Fig 25B; forming a first conductive feature Fig 26B, 122 over the first epitaxial region and a second conductive feature over the second epitaxial region Fig 26B; forming an etch stop layer Fig 26B, 104 over the nitride mask Fig 26B, 100 and the first oxide layer Fig 26B; forming a second oxide layer Fig 27B, 124 over the etch stop layer Fig 27B, 104; forming a gate plug Fig 28B, 132 over and physically contacting the first gate stack Fig 28B; and forming a third conductive feature Fig 28B, 130/130a through the second oxide layer and the etch stop layer Fig 28B, the third conductive feature physically contacting the first conductive feature Fig 28B. Chou also discloses wherein forming the gate mask comprises: recessing the gate stack Fig 15B;depositing a dielectric liner over the gate stack Fig 15B; and depositing a nitride layer over the dielectric liner Fig 15B.Chou discloses all the limitations but silent on the material used as a liner over the gate stack. Whereas Chiang discloses depositing a metal dielectric liner Fig 1G, 134 ¶0030 over the gate stack; and depositing a nitride layer Fig 1K, 146 over the metal dielectric liner Fig 1K, 134. Chou and Chiang are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chou because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the mask used by Chou and incorporate the teachings of Chiang since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of design choice. In re Leshin, 125 USPQ 416 (1960).
Regarding claim 14, Chou discloses wherein the third conductive feature is in physical contact with the gate plug Fig 28B.
Claims 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Chou et al (US Publication No. 2022/0123115) in view of Ho et al (US Patent No. 9,548,366).
Regarding claim 5, Chou discloses all the limitations but silent on the dielectric layer as an etch stop. Whereas Ho discloses before forming the conductive feature, performing an etch process to etch through the second inter-layer dielectric Fig 12, 54 and the dielectric layer Fig 12, 52, wherein the dielectric layer Fig 12, 52 acts as an etch stop layer during the etch process Fig 12. Chou and Ho are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chou because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the mask used by Chou and incorporate the teachings of Ho to protect the underlying layers.
Regarding claim 6, Ho discloses wherein after performing the etch process the gate mask remains substantially unetched Fig 12.
Regarding claim 7, Ho discloses wherein the dielectric layer and the gate mask have an etch selectivity greater than or equal to 10 (Column 7 lines 25-40 and Column 8, lines 7-30).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Chou et al (US Publication No. 2022/0123115) and Ho et al (US Patent No. 9,548,366) and in further view of Tsai et al (US Publication No. 2022/0157656).
Regarding claim 8, Chou discloses all the limitations but silent on the material used for the mask. Whereas Tsai discloses , wherein the gate mask comprises silicon nitride, and wherein the dielectric layer comprises silicon carbonate or silicon carbonitride ¶0039 and 0043 Fig 13. Chou and Tsai are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chou because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the mask used by Chou and incorporate the teachings of Tsai since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of design choice. In re Leshin, 125 USPQ 416 (1960).
Claims 10 21-22, 24 are rejected under 35 U.S.C. 103 as being unpatentable over Chou et al (US Publication No. 2022/0123115) and Chiang et al (US Publication No. 2020/0043732) in view of Ho et al (US Patent No. 9,548,366).
Regarding claim 10, Chou discloses all the limitations but silent on the material of the etch stop. Whereas Ho discloses. wherein the etch stop layer has an etch selectivity of 10 or greater in comparison with the nitride mask(Column 7 lines 25-40 and Column 8, lines 7-30). Chou and Ho are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chou because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the mask used by Chou and incorporate the teachings of Ho since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of design choice. In re Leshin, 125 USPQ 416 (1960).
Regarding claim 21, Chou discloses a method, comprising: forming a fin Fig 3, 52 over a substrate Fig 3, 50; forming a gate stack Fig 14B, 96 over the fin Fig 14B, 52; forming an epitaxial source/drain region Fig 14B, 82 in the fin Fig 14B, 52 adjacent to the gate stack Fig 14B, 96; forming a first inter-layer dielectric (ILD) Fig 14B, 88 over the gate stack Fig 14B, 96 and the epitaxial source/drain region Fig 14B, 82;recessing the gate stack to form a recess Fig 15B; forming a first dielectric layer Fig 18B, 100 in the recess and over the gate stack Fig 18B, 96, the first dielectric layer Fig 18B, 100 comprising a first material ¶0056;forming a second dielectric layer Fig 19B, 102 over the first dielectric layer Fig 19B, 100, the second dielectric layer Fig 19B, 102 comprising a second material different from the first material¶0058; forming a second ILD Fig 25B, 104 over the second dielectric layer Fig 25B, 102;forming a first opening through the first ILD Fig 25B, 88, the first opening exposing the epitaxial source/drain region Fig 25B;forming a first conductive feature Fig 26B, 122 in the first opening; forming a second opening through the second ILD Fig 27B, 104 and the second dielectric layer Fig 27B, 102 using an etch process ¶0076, and forming a second conductive feature in the second opening Fig 28B, the second conductive feature electrically coupled to the first conductive feature Fig 28B. Chou discloses all the limitations but silent on the material properties of the first dielectric layer.
Whereas Ho discloses wherein the first dielectric layer Fig 12, 52 acts as an etch stop layer during the etch process, and wherein a ratio of an etch rate of the second material Fig 12, 54 to an etch rate of the first material is greater than or equal to 10(Column 7 lines 25-40 and Column 8, lines 7-30). Chou and Ho are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chou because they are from the same field of endeavor. Therefore, it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the mask used by Chou and incorporate the teachings of Ho to protect the underlying layers.
Chou also discloses wherein forming the gate mask comprises: recessing the gate stack Fig 15B;depositing a dielectric liner over the gate stack Fig 15B; and depositing a nitride layer over the dielectric liner Fig 15B.Chou discloses all the limitations but silent on the material used as a liner over the gate stack. Whereas Chiang discloses depositing a metal dielectric liner Fig 1G, 134 ¶0030 over the gate stack; and depositing a nitride layer Fig 1K, 146 over the metal dielectric liner Fig 1K, 134. Chou and Chiang are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chou because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the mask used by Chou and incorporate the teachings of Chiang since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of design choice. In re Leshin, 125 USPQ 416 (1960).
Regarding claim 22, Chou discloses wherein the first material comprises silicon nitride ¶0056, and the second material comprises silicon carbonitride or silicon oxycarbide ¶0058.
Regarding claim 24, Chou discloses wherein the second opening extends laterally beyond lateral edges of the first conductive feature Fig 27B and 28B.
Claims 11-13 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Chou et al (US Publication No. 2022/0123115) and Chiang et al (US Publication No. 2020/0043732) in view of Kim et al (US Publication No. 2022/0181323).
Regarding claim 11, Chou discloses all the limitations but silent on the shape. Whereas Kim discloses wherein in a plan view the third conductive feature has a rectangular shape, and wherein a length of the rectangular shape is two to three times greater than a width of the rectangular shape Fig 1. Chou and Kim are analogous art because they are directed to semiconductor devices having metal gates and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chou because they are from the same field of endeavor. Therefore it would have been obvious to one having ordinary skill of the art before the effective filing date of the claimed invention to modify the arrangement of Chou and incorporate the teachings of Kim since such a modification would have involved a mere change in the shape of a component. A change in shape is generally recognized as being within the level of ordinary skill in the art. In reDailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Regarding claim 12, Chou discloses wherein the third conductive feature is directly over the first epitaxial region, the first gate stack, and the second gate stack Fig 27B and 28B.
Regarding claim 13, Chou discloses wherein the third conductive feature is directly over the first epitaxial region and the second epitaxial region Fig 27B and 28B.
Regarding claim 23, Kim discloses wherein forming the second opening comprises forming the second opening with a slot shape having a length greater than or equal to two times a width Fig 1.
Allowable Subject Matter
Claims 25-26 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
After further search and consideration, it is determined that the prior art of record neither anticipates nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination, in particular, prior art of record does not teach or suggest the specific arrangement and method of forming the metal dielectric liner relative to the gate contact layer and the first dielectric layer.
Response to Arguments
Applicant's arguments filed 6/8/2026 have been fully considered but they are not persuasive.
In response applicants’ argument that the prior art of record does not teach the gate plug step, the examiner disagrees and finds the argument unpersuasive. Chou discloses the above claimed limitations as described in the rejection above specifically Fig 36B.
In response applicants’ argument that the prior art of record does not teach the metal dielectric liner, the examiner disagrees and finds the argument unpersuasive. Chiang discloses the above claimed limitations as described in the rejection above specifically Fig 1G, 134 ¶0030.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTINE A ENAD whose telephone number is (571)270-7891. The examiner can normally be reached Monday-Friday, 7:30 am -4:30 pm.
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/CHRISTINE A ENAD/ Primary Examiner, Art Unit 2811
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