DETAILED ACTION
This Office action is in response to the RCE filed 23 March 2026. Claims 1-16, 20, and 22-30 are currently pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 23 March 2026 has been entered.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 8, and 23 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
The indicated allowability of claims 16, 20, 22, and 26-30 is withdrawn in view of the newly discovered reference(s) to De-Michielis. Rejections based on the newly cited reference(s) follow.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5-6, 8-9, 11-13, 15-16, 20, 22, 23-28, and 30 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2019/0123172 A1 to De-Michielis et al. (hereinafter “De-Michielis”).
Regarding independent claim 1, De-Michielis (Fig. 3) discloses a power semiconductor device, comprising: a semiconductor layer structure comprising a drift region 5 (¶ 0047) of a first conductivity type (n) and a well region 4 (¶ 0047) of a second conductivity type (p); and
a plurality of gate trenches (70/72 disposed therein; ¶ 0052) extending into the drift region 5, wherein the gate trenches are spaced apart from one another in a first direction (Fig. 3 - direction left to right) and comprise gate insulating layers 72 (¶ 0052) therein, and
wherein respective portions 9 (¶ 0057) of the drift region adjacent the gate trenches comprise a concentration of dopants of the first conductivity type (n) that varies along the first direction (dopant concentration in 5 varies as a result of presence of doped regions 9), and wherein a peak concentration of the concentration of dopants (in 9) is between nearest corners of adjacent ones of the gate trenches in the first direction (Fig. 3; ¶ 0056) and is spaced apart from the gate insulating layers 72 therein in the first direction by a portion 8 (¶ 0056) of the semiconductor structure (Fig. 3).
Regarding claim 2, De-Michielis (Fig. 3) discloses the power semiconductor device of claim 1, wherein the drift region comprises respective conduction enhancing regions 9 (¶ 0057) of the first conductivity type (n) that are spaced apart from the nearest corners of the adjacent ones of the gate trenches (70/72 disposed therein) along the first direction (left to right), wherein the concentration of the dopants of the first conductivity type (n) comprises a first concentration proximate the nearest corners of the adjacent ones of the gate trenches and a second concentration in the respective conduction enhancing regions 9, wherein the second concentration is higher than the first concentration (¶ 0057).
Regarding claim 3, De-Michielis (Fig. 3) discloses the power semiconductor device of claim 2, wherein the concentration of the dopants of the first conductivity type (n) further comprises a concentration gradient of the dopants of the first conductivity type between the first concentration and the second concentration along the first direction (dopant concentration varies as a result of presence of doped regions 9 in 5).
Regarding claim 5, De-Michielis (Fig. 3) discloses the power semiconductor device of claim 2, further comprising: respective shielding patterns 8 (¶ 0056)) of the second conductivity type (p) in the respective portions of the drift region 5 between the gate trenches and/or under the gate trenches (70/72 disposed therein), wherein the respective conduction enhancing regions 9 are between the gate trenches and extend into the drift region 5 beyond a lower boundary of the respective shielding patterns 8, and wherein the respective conduction enhancing regions are offset from the respective shielding patterns towards the gate trenches, and/or wherein the respective conduction enhancing regions 8 extend along at least one of a side or a lower boundary of the respective shielding patterns 8 (Fig. 3).
Regarding claim 6, De-Michielis (Fig. 3) discloses the power semiconductor device of claim 2, wherein the concentration of the dopants of the first conductivity type varies (dopant concentration in 5 varies as a result of presence of doped regions 9) such that, responsive to a voltage applied to the power semiconductor device, the respective portions of the drift region between the gate trenches comprise an electric field distribution having a peak that is distal from the nearest corners of the adjacent ones of the gate trenches in the first direction. (This limitation is considered functional language. De-Michielis discloses the structure as recited in the claim as currently drafted, thus the structure of De-Michielis is presumed to be capable of the functionally defined limitations of the claimed device. MPEP § 2114 (I)).
Regarding independent claim 8, De-Michielis (Fig. 3) discloses a power semiconductor device, comprising: a semiconductor layer structure comprising a drift region 5 (¶ 0047) of a first conductivity type (n) and a well region 4 (¶ 0047) of a second conductivity type (p); and
a plurality of gate trenches (70/72 disposed therein; ¶ 0052) extending into the drift region 5, wherein the drift region comprises a concentration of dopants of the first conductivity type (n-), wherein the concentration of the dopants comprises a first concentration proximate respective corners of the gate trenches and a second concentration (in 9; ¶ 0057) distal from the respective corners, wherein the second concentration is higher than the first concentration (¶ 0057).
Regarding claim 9, De-Michielis (Fig. 3) discloses the power semiconductor device of claim 8, wherein the gate trenches (70/72 disposed therein) are spaced apart from one another in a first direction (Fig. 3 - direction from left to right). The limitation “wherein an electric field distribution in respective portions of the drift region between the gate trenches is asymmetric along the first direction” is considered functional language. De-Michielis discloses the structure as recited in the claim as currently drafted, thus the structure of De-Michielis is presumed capable of the functionally defined limitations of the claimed device. MPEP § 2114 (I).
Regarding claim 11, De-Michielis (Fig. 3) discloses the power semiconductor device of claim 9, wherein the respective portions of the drift region 5 between the gate trenches (70/72 disposed therein) comprise the concentration of dopants of the first conductivity type (n) that varies along the first direction between adjacent ones of the gate trenches (dopant concentration in 5 varies between adjacent ones of the gate trenches as a result of doped regions 9).
Regarding claim 12, De-Michielis (Fig. 3) discloses the power semiconductor device of claim 11, further comprising: respective conduction enhancing regions 9 of the first conductivity type (n) that are spaced apart from the respective corners of the gate trenches (70/72 disposed therein) along the first direction (Fig. 3 - left to right), wherein the concentration of the dopants of the first conductivity type (n) comprises a first concentration (¶ 0057) proximate the respective corners of the gate trenches and a second concentration in the respective conduction enhancing regions 9 (¶ 0057), wherein the second concentration is higher than the first concentration (¶ 0057).
Regarding claim 13, De-Michielis (Fig. 3) discloses the power semiconductor device of claim 12, wherein the concentration of the dopants of the first conductivity type (n) further comprises a concentration gradient of the dopants of the first conductivity type between the first concentration and the second concentration along the first direction (dopant concentration varies as a result of presence of doped regions 9 in 5).
Regarding claim 15, De-Michielis (Fig. 3) discloses the power semiconductor device of claim 12, wherein the respective conduction enhancing regions 9 comprise the peak of the electric field distribution (this limitation is considered functional language). De-Michielis discloses the structure as recited in the claim as currently drafted, thus the structure of De-Michielis is presumed capable of the functionally defined limitations of the claimed device. MPEP § 2114 (I)).
Regarding independent claim 16, De-Michielis (Fig. 3) discloses a power semiconductor device, comprising: a semiconductor structure comprising a drift region 5 (¶ 0047) of a first conductivity type (n) and a well region 4 (¶ 0047) of a second conductivity type (p); a plurality of gate trenches (70/72 disposed therein; ¶ 0052) extending into the drift region 5 and spaced apart from one another in a first direction (Fig. 3 - left to right); and respective shielding patterns 8 (¶ 0056) of the second conductivity type (p) in respective first portions of the drift region 5 adjacent the gate trenches (Fig. 3); and respective conduction enhancing regions 9 (¶ 0057) of the first conductivity type (n) that are spaced apart from respective corners of the gate trenches along the first direction (Fig. 3 - spaced apart from corners of the gate trenches by 8) and extend around a periphery of the respective shielding patterns 8 (Fig. 3).
Regarding claim 20, De-Michielis (Fig. 3) discloses the power semiconductor device of claim 16, wherein the respective portions second portions of the drift region 5 adjacent the gate trenches (70/72 disposed therein) comprise a concentration of dopants of the first conductivity type (n) that varies along the first direction (Fig. 3 - left to right) (dopant concentration in portions of 5 adjacent the gate trenches varies as a result of doped regions 9/8).
Regarding claim 22, De-Michielis (Fig. 3) discloses the power semiconductor device of claim 20, wherein the respective shielding patterns 8 extend along bottom portions of the gate trenches (Fig. 3), and wherein the concentration of dopants of the first conductivity type (n) varies along the first direction between adjacent ones of the gate trenches (dopant concentration in portions of 5 bewteen adjacent the gate trenches varies as a result of doped regions 9/8).
Regarding independent claim 23, De-Michielis (Fig. 3) discloses a power semiconductor device, comprising: a semiconductor structure comprising a drift region 5 (¶ 0047) of a first conductivity type (n) and a well region 4 (¶ 0047) of a second conductivity type (p); and a plurality of gate trenches (70/72 disposed therein; ¶ 0052) extending into the drift region 5; and respective shielding patterns 8 (¶ 0056) of the second conductivity type (p) in respective portions of the drift region 5 adjacent the gate trenches, wherein, the drift region 5 comprises a concentration of dopants (n-; ¶ 0047) of the first conductivity type (n-type), the concentration of the dopants comprising a first concentration proximate respective corners of the gate trenches (70/72 disposed therein) and a second concentration (in 9) distal from the respective corners, wherein the second concentration is higher than the first concentration (¶ 0057).
The limitation “such that, respective portions of the drift region between the gate trenches provide an electric field distribution having a peak that is between and distal from the respective corners of the gate trenches” is considered functional language that does not structurally distinguish the claimed invention over the prior art. Examiner notes that the above recitation refers to a result occurring during operation of the device, as an electric field is not present when the device is not being operated; and no other structural limitations (e.g., presence of other doped regions, doping concentration, dopant distribution, etc.) are recited that structurally distinguish the claimed invention over the prior art. De-Michelis discloses the structure as recited in the claim as currently drafted, thus the structure of De-Michelis is presumed capable of the functionally defined limitations of the claimed device. MPEP § 2114(I).
Regarding claim 24, De-Michielis (Fig. 3) discloses the power semiconductor device of claim 23, wherein the gate trenches (70/72 disposed therein) are spaced apart from one another in a first direction (Fig. 3, left to right), and wherein the electric field distribution in the respective portions of the drift region between the gate trenches is asymmetric along the first direction (this limitation is considered functional language; De-Michielis discloses the structure as recited in the claim as currently drafted, thus the structure of De-Michielis is presumed capable of the functionally defined limitations of the claimed device. MPEP § 2114 (I)).
Regarding claim 25, De-Michielis (Fig. 3) discloses the power semiconductor device of claim 23, wherein the gate trenches (70/72 disposed therein) are spaced apart from one another along a first direction (Fig. 3, left to right), wherein the respective shielding patterns 8 extend along bottom portions of the gate trenches (Fig. 3), and wherein the concentration of dopants of the first conductivity type varies along the first direction between adjacent ones of the gate trenches (dopant concentration in 5 varies between adjacent ones of the gate trenches as a result of presence of doped regions 8/9).
Regarding claim 26, De-Michielis (Fig. 3) discloses the power semiconductor device of claim 1, further comprising: respective shielding patterns 8 (¶ 0056)) of the second conductivity type (p) in the drift region 5 between the gate trenches and/or under the gate trenches (70/72 disposed therein; Fig. 3); and respective conduction enhancing regions 9 (¶ 0057) of the first conductivity type (n) that are spaced apart from the gate trenches along the first direction (Fig. 3 - spaced apart from gate trenches by 8) and extend around a periphery of the respective shielding patterns 8 (Fig. 3).
Regarding claim 27, De-Michielis (Fig. 3) discloses the power semiconductor device of claim 20, wherein the concentration of the dopants of the first conductivity type (n) comprises a first concentration proximate the respective corners of the gate trenches (70/72 disposed therein) and a second concentration in the respective conduction enhancing regions 9, wherein the second concentration is higher than the first concentration (¶ 0057).
Regarding claim 28, De-Michielis (Fig. 3) discloses the power semiconductor device of Claim 27, wherein the concentration of the dopants of the first conductivity type (n) further comprises a concentration gradient of the dopants of the first conductivity type that varies between the first concentration and the second concentration along the first direction (dopant concentration in 5 varies along the left-to-right direction as a result of presence of doped regions 8/9).
Regarding claim 30, De-Michielis (Fig. 3) discloses the power semiconductor device of Claim 27, wherein the respective conduction enhancing regions 9 are in direct contact with the respective shielding patterns 8 (Fig. 3).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 4, 7, 10, 14, and 29 are rejected under 35 U.S.C. 103 as being unpatentable over De-Michielis.
Regarding claim 7, De-Michielis (Fig. 3) discloses the power semiconductor device of claim 6, however fails to expressly disclose wherein the peak of the electric field distribution is greater than a strength of the electric field distribution proximate the nearest corners of the adjacent ones of the gate trenches by a factor of about 10 or more.
Regarding claim 10, De-Michielis (Fig. 3) discloses the power semiconductor device of claim 9, however fails to expressly disclose wherein the peak of the electric field distribution is greater than a strength of the electric field distribution proximate the respective corners of the gate trenches by a factor of about 10 or more.
Regarding claims 7 and 10, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the claimed electric field distribution relationship since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F .2d 272, 205 USPQ 215 (CCPA 1980). Here, the electric field distribution relationship is considered a result effective variable because it affects on-state voltage, breakdown voltage, and performance of the power semiconductor device (De-Michielis, ¶ 0022-23). Thus, the ordinary artisan would have been motivated to modify the electric field distribution relationship as recited for the purpose of improving on-state and breakdown voltage characteristics, thus improving performance of the power semiconductor device.
Regarding claims 4, 14, and 29, De-Michielis (Fig. 3) discloses the power semiconductor device of claims 2, 12, and 27, however fail to expressly disclose: wherein the second concentration is higher than the first concentration by a factor of about 2 or more.
it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide the claimed dopant concentration relationship since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F .2d 272, 205 USPQ 215 (CCPA 1980). Here, the dopant concentration relationship is considered a result effective variable because it affects the electric field generated during device operation, on-state voltage, breakdown voltage, and performance of the power semiconductor device (De-Michielis, ¶ 0021-23). Thus, the ordinary artisan would have been motivated to modify the dopant concentration relationship as recited for the purpose of improving the device characteristics discussed above, thus improving performance of the power semiconductor device.
Conclusion
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CANDICE Y. CHAN
Examiner
Art Unit 2813
4 April 2026
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
Prosecution Insights