DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/20/2023, 9/13/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chai (US 2017/0256544).
Regarding claim 18, Chai discloses, in at least figures 1-10, 16A-17B, and related text, a semiconductor structure, comprising:
a substrate (SUB, [221]) comprising a first region (region of P_Tb (P_T2), [221], [222]), a second region (region of P_Tc (P_T3), [221], [222]), and a third region (region of N_Tb (N_T2), [221], [222]);
first channel members (P_S2, [49]) over the first region (region of P_Tb (P_T2), [221], [222]);
second channel members (P_S3, [61]) over the second region (region of P_Tc (P_T3), [221], [222]);
third channel members (N_S2, [119]) over the third region (region of N_Tb (N_T2), [221], [222]);
a first gate structure (P_G2, [222]) wrapping around each of the first channel members (P_S2, [49]) and comprising:
a first gate dielectric layer (P_Oa, [43]) in contact with each of the first channel members (P_S2, [49]),
a second gate dielectric layer (P_Ob, [43]) over the first gate dielectric layer (P_Oa, [43]),
a third gate dielectric layer (P_O2b, [57]) over the second gate dielectric layer (P_Ob, [43]), and
a first gate electrode (P_GE2, [50]);
a second gate structure (P_G3, [222]) wrapping around each of the second channel members (P_S3, [61]) and comprising:
the first gate dielectric layer (P_Oa, [43]) in contact with each of the second channel members (P_S3, [61]),
a fourth gate dielectric layer (P_O3a, [70]) over the first gate dielectric layer (P_Oa, [43]),
the third gate dielectric layer (P_O3b, [70]) over the fourth gate dielectric layer (P_O3a, [70]), and
a second gate electrode (P_GE3, [62]); and
a third gate structure (N_G2, [222]) wrapping around each of the third channel members (N_S2, [119]) and comprising:
a fifth gate dielectric layer (N_Oa, [110]) in contact with each of the third channel members (N_S2, [119]),
the fourth gate dielectric layer (N_O3a, [133]) over the fifth gate dielectric layer (N_Oa, [110]),
the third gate dielectric layer (N_O3b, [133]) over the fourth gate dielectric layer (N_O3a, [133]), and
a third gate electrode (N_GE2, [119]),
wherein a composition of the first gate dielectric layer (P_Oa, [43]) is different from a composition of the fourth gate dielectric layer (P_O3a, [70]),
wherein a composition of the third gate dielectric layer (P_O3b, [70]) is different from the composition of the fourth gate dielectric layer (P_O3a, [70]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chai (US 2017/0256544) in view of Chen (US 2020/0083114).
Regarding claim 19, Chai discloses the semiconductor structure of claim 18 as described above.
Chai does not explicitly disclose the first gate electrode, the second gate electrode, and the third gate electrode comprise a same composition.
Chen teaches, in at least figure 15 and related text, the device comprising the first gate electrode (108 of 310, [53]), the second gate electrode (108 of 320, [53]), and the third gate electrode (108 of 330, [53]) comprise a same composition, for the purpose of providing multiple different threshold voltages in different transistor devices on a substrate without affecting respective spacings for the gates of the transistor devices ([13]).
Chai and Chen are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chai with the specified features of Chen because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Chai to have the first gate electrode, the second gate electrode, and the third gate electrode comprising a same composition, as taught by Chen, for the purpose of providing multiple different threshold voltages in different transistor devices on a substrate without affecting respective spacings for the gates of the transistor devices ([13], Chen).
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chai (US 2017/0256544) in view of Liao (US 2022/0320293).
Regarding claim 20, Chai discloses the semiconductor structure of claim 18 as described above.
Chai does not explicitly disclose a total thickness of the first gate dielectric layer, the second gate dielectric layer and the third gate dielectric layer is between about 5Å and about 50Å.
Liao teaches, in at least figure 18 and related text, the device comprising a total thickness of the first gate dielectric layer (280, [28]), the second gate dielectric layer (282, [29]) and the third gate dielectric layer (285, [41]) is between about 5Å and about 50Å ([28], [29], [41]), for the purpose of providing PFET with extremely low threshold voltages and NFET with super low leakage values with broad tunable range of threshold voltage ([54]).
Chai and Liao are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Chai with the specified features of Liao because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Chai to have the total thickness of the first gate dielectric layer, the second gate dielectric layer and the third gate dielectric layer being between about 5Å and about 50Å, as taught by Liao, for the purpose of providing PFET with extremely low threshold voltages and NFET with super low leakage values with broad tunable range of threshold voltage ([54], Liao).
Allowable Subject Matter
Claims 1-10 are allowed because the prior art of record, US 2021/0366783, neither anticipates nor render obvious the limitations of the base claims 1 that recite "after the removing, depositing a second gate dielectric layer to wrap around each of the first channel members, each of the second channel members, and each of the third channel members" in combination with other elements of the base claims 1.
Claims 11-17 are allowed because the prior art of record, US 2023/0073078 in view of US 2021/0366783, neither anticipates nor render obvious the limitations of the base claims 11 that recite "after the removing, depositing a second gate dielectric layer to wrap around each of the first top channel members, each of the second top channel members, and each of the third top channel members" in combination with other elements of the base claims 11.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONG-HO KIM whose telephone number is (571)270-0276. The examiner can normally be reached Monday thru Friday; 8:30 AM to 5PM.
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/TONG-HO KIM/Primary Examiner, Art Unit 2811