DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election filed on 12/15/2025 without traverse to prosecute the claims of Invention I, claims 1-15 (and new claims 21-25) is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/20/2023 is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Jiang et al. (CN 110828378 A) in view of Wu et al. (US 20200168715 A1) and Lin et al. (TW 202119557 A).
Jiang teaches a method for forming a semiconductor device structure (200, page 5, FIG. 4), comprising:
forming a stack (204, page 5) over a substrate (202), wherein the stack has a plurality of semiconductor layers (206, page 9 par 3) and a plurality of sacrificial layers (208, page 9 par 3, material is SiGe) laid out in an alternating manner (FIG. 4);
patterning the stack to form a first fin structure (210, page 5) and a second fin structure (212, page 5),
forming a first gate stack (224, page 5) wrapped around the first fin structure (210);
forming a second gate stack (226) wrapped around the second fin structure (212, FIG. 7).
Jiang does not teach simultaneously removing the sacrificial layers of the first fin structure and the second fin structure, wherein remaining portions of the semiconductor layers of the first fin structure form a plurality of first semiconductor nanostructures, remaining portions of the semiconductor layers of the second fin structure form a plurality of second semiconductor nanostructures, and each of the second semiconductor nanostructures is thicker than each of the first semiconductor nanostructures.
Wu teaches simultaneously removing the sacrificial layers (205a and 205b, [0041], FIG. 18B) of the first fin structure (303a) [0024] and the second fin structure (303b), wherein remaining portions (FIG. 19B) of the semiconductor layers (407a) [0043] of the first fin structure (303a) form a plurality of first semiconductor nanostructures (407a), remaining portions of the semiconductor layers (207b) [0043] of the second fin structure (303b) form a plurality of second semiconductor nanostructures (207b), and each of the second semiconductor nanostructures (207b) is thicker than each of the first semiconductor nanostructures (407a, FIG. 19B).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Wu into the structure of Jiang since Wu teaches a gate all around semiconductor device.
The ordinary artisan would have been motivated to modify Wu in combination with Jiang in the above manner for the motivation of forming the fins to have different semiconductor nanostructure heights to optimize the chip structure to allow for smaller transistors. [0003] states, “One of the goals of the semiconductor industry is to continue shrinking the size and increasing the speed of individual FETs.”
Jiang in view of Wu does not teach the second fin structure is wider than the first fin structure.
Lin teaches the second fin structure (210A, page 8 par 1) is wider than the first fin structure (210B, FIG. 9A).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Lin into the structure of Jiang in view of Wu since Lin teaches a gate all around semiconductor device.
The ordinary artisan would have been motivated to modify Lin in combination with Jiang in view of Wu in the above manner for the motivation of forming the fins to have different semiconductor nanostructure widths to optimize the chip structure to allow for smaller transistors. Page 3 par 1 states, “With the development of integrated circuit (IC) technology toward smaller technology nodes, gate-all-around (GAA) transistors have been incorporated into SRAM to reduce chip footprint while maintaining Reasonable processing margin.” A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Jiang et al. (CN 110828378 A) in view of Wu et al. (US 20200168715 A1) and Lin et al. (TW 202119557 A) and You et al. (CN 113140545 A).
Re Claim 2 Jiang in view of Wu and Lin teaches the method for forming a semiconductor device structure as claimed in claim 1, but does not teach:
partially removing the first fin structure and the second fin structure to form a plurality of recesses exposing side surfaces of the semiconductor layers and the sacrificial layers of the first fin structure and the second fin structure;
forming a plurality of inner spacers covering the side surfaces of the sacrificial layers of the first fin structure and the second fin structure;
forming first epitaxial structures on the side surfaces of the semiconductor layers of the first fin structure before the first semiconductor nanostructures are formed; and
forming second epitaxial structures on the side surfaces of the semiconductor layers of the second fin structure before the second semiconductor nanostructures are formed, wherein the first epitaxial structures and the second epitaxial structures have a same conductivity type.
You teaches partially removing (page 16 par 2 states, “…the first groove 86, the second groove 90 and the third groove 94 of the first semiconductor material formed by the first semiconductor material 64 (e.g., the first nano structure 52) of the side wall of each layer is etched to form the side wall groove 96.”) the first fin structure (52/54 stack to left of 86, FIG. 12B) and the second fin structure (52/54 stack to left of 94, FIG. 12B) to form a plurality of recesses (86 and 94) exposing side surfaces of the semiconductor layers (54, page 16 par 2) and the sacrificial layers (52) of the first fin structure and the second fin structure (FIG. 12B);
forming a plurality of inner spacers (98, page 16 par 3) covering the side surfaces of the sacrificial layers (52) of the first fin structure and the second fin structure (FIG. 13B);
forming first epitaxial structures (FIG. 15B, 106 in groove that was 86) on the side surfaces of the semiconductor layers (54) of the first fin structure (52/54 stack to left of 86, FIG. 12B) before the first semiconductor nanostructures are formed (FIG. 19B shows sacrificial layers 52 removed); and
forming second epitaxial structures (FIG. 15B, 106 in groove that was 94) on the side surfaces of the semiconductor layers (54) of the second fin structure (52/54 stack to left of 94, FIG. 12B) before the second semiconductor nanostructures are formed (54 in FIG. 19B), wherein the first epitaxial structures (106) and the second epitaxial structures (106) have a same conductivity type (Page 8 par 2 states, “Each of the short channel region 50S and the long channel region 50L may include one or more of an n-type region50N and/or a p-type region 50P.”, both 106 regions references are in 50S and 50L. Assume both are same conductivity type).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by You into the structure of Jiang in view of Wu and Lin since You teaches a gate all around semiconductor device.
The ordinary artisan would have been motivated to modify You in combination with Jiang in view of Wu and Lin in the above manner for the motivation of optimally integrating epitaxial regions around the fin structures to allow for smaller semiconductor devices than previously produced. Page 3 par 4 states, “The semiconductor industry continues to improve the integrated density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum component size, thereby allowing more components to be integrated into a given area.”
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Jiang et al. (CN 110828378 A) in view of Wu et al. (US 20200168715 A1) and Lin et al. (TW 202119557 A) and Trivedi et al. (US 20210280683 A1).
Re Claim 3 Jiang in view of Wu and Lin teaches the method for forming a semiconductor device structure as claimed in claim 1, wherein a third fin structure (Lin, 210C) is formed during the patterning of the stack, the third fin structure (210C) is substantially as wide as the first fin structure (210B), and the first gate stack (232, page 16 par 2) is wrapped around the third fin structure (210C), and the method further comprises:
removing the sacrificial layers (206, page 10 par 1) of the third fin structure (210C), wherein remaining portions of the semiconductor layers of the third fin structure form a plurality of third semiconductor nanostructures (208, page 10 par 1, see image FIG. 9A and 10A, 206 is removed after 9A and before 10A).
Jiang in view of Wu and Lin does not teach each of the first semiconductor nanostructures is thicker than each of the third semiconductor nanostructures.
Trivedi teaches each of the first semiconductor nanostructures (306B) [0049] is thicker than each of the third semiconductor nanostructures (308B, see figure below).
Annotated FIG. 3H below identifies the 1st and 3rd fin structures
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It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Trivedi into the structure of Jiang in view of Wu and Lin since Trivedi teaches a gate all around semiconductor device.
The ordinary artisan would have been motivated to modify Trivedi in combination with Jiang in view of Wu and Lin in the above manner for the motivation of forming the channel regions with optimal thickness to optimize the available space in the chip as semiconductor devices continue to scale down. [0002] states, “For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips.”
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Jiang et al. (CN 110828378 A) in view of Wu et al. (US 20200168715 A1) and Lin et al. (TW 202119557 A) and Trivedi et al. (US 20210280683 A1) and You et al. (CN 113140545 A).
Re Claim 4 Jiang in view of Wu and Lin and Trivedi teaches the method for forming a semiconductor device structure as claimed in claim 3, further but does not teach:
partially removing the first fin structure and the third fin structure to form a plurality of recesses exposing side surfaces of the semiconductor layers and the sacrificial layers of the first fin structure and the third fin structure;
forming a plurality of inner spacers covering the side surfaces of the sacrificial layers of the first fin structure and the third fin structure;
forming p-type doped epitaxial structures on the side surfaces of the semiconductor layers of the first fin structure before the first semiconductor nanostructures are formed; and
forming n-type doped epitaxial structures on the side surfaces of the semiconductor layers of the third fin structure before the third semiconductor nanostructures are formed.
You teaches partially removing the first fin structure (52/54 stack to left of 86 groove, FIG. 11B) and the third fin (52/54 stack to right of 94 groove) structure to form a plurality of recesses exposing side surfaces of the semiconductor layers (54) and the sacrificial layers (52) of the first fin structure and the third fin structure (FIG. 12B);
forming a plurality of inner spacers (98, page 16 par 3) covering the side surfaces of the sacrificial layers (52) of the first fin structure and the third fin structure (FIG. 13B);
forming p-type doped epitaxial structures (106, Page 8 par 2, “Each of the short channel region 50S and the long channel region 50L may include one or more of an n-type region50N and/or a p-type region 50P.”) on the side surfaces of the semiconductor layers (52/54 stack) of the first fin structure (FIG. 15B) before the first semiconductor nanostructures are formed (formed later in FIG. 19B); and
forming n-type doped epitaxial structures (106, Page 8 par 2, “Each of the short channel region 50S and the long channel region 50L may include one or more of an n-type region50N and/or a p-type region 50P.”) on the side surfaces of the semiconductor layers of the third fin structure (FIG. 15B) before the third semiconductor nanostructures are formed (formed later in FIG. 19B).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by You into the structure of Jiang in view of Wu and Lin and Trivedi since You teaches a gate all around semiconductor device.
The ordinary artisan would have been motivated to modify You in combination with Jiang in view of Wu and Lin and Trivedi in the above manner for the motivation of optimally shaping the fin structures to allow for smaller semiconductor devices than previously produced. Page 3 par 4 states, “The semiconductor industry continues to improve the integrated density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum component size, thereby allowing more components to be integrated into a given area.”
Claims 5-9 are rejected under 35 U.S.C. 103 as being unpatentable over Jiang et al. (CN 110828378 A) in view of Wu et al. (US 20200168715 A1) and Lin et al. (TW 202119557 A) and Trivedi et al. (US 20210280683 A1) and Lee et al. (US 20200258740 A1).
Re Claim 5 Jiang in view of Wu and Lin and Trivedi teaches the method for forming a semiconductor device structure as claimed in claim 3, wherein a fourth fin structure (Lin, 201D, FIG. 9A) is formed during the patterning of the stack (206/208 stack, FIG. 8, page 17 par 2), the fourth fin structure (210D) is substantially as wide as the second fin structure (210A), and the second gate stack (232 portion around 210D, FIG. 9A, page 16 par 2) is wrapped around the fourth fin structure (210D), and the method further comprises:
removing the sacrificial layers (206) of the fourth fin structure (20D), wherein remaining portions of the semiconductor layers of the fourth fin structure form a plurality of fourth semiconductor nanostructures (208, FIG. 10A).
Jiang in view of Wu and Lin and Trivedi does not explicitly teach each of the second semiconductor nanostructures is thicker than each of the fourth semiconductor nanostructures,
Trivedi teaches each of the second semiconductor nanostructures (306B stack in between 1st and 3rd fins, refer to image under claim 3) is thicker than each of the fourth semiconductor nanostructures (308B stack to right of 3rd fin in image under claim 3).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Trivedi into the structure of Jiang in view of Wu and Lin and Trivedi since Trivedi teaches a gate all around semiconductor device.
The ordinary artisan would have been motivated to modify Trivedi in combination with Jiang in view of Wu and Lin and Trivedi in the above manner for the motivation of forming the semiconductor nanostructures to be an optimal thickness. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Jiang in view of Wu and Lin and Trivedi does not teach each of the fourth semiconductor nanostructures is thicker than each of the third semiconductor nanostructures
Lee teaches each of the fourth semiconductor nanostructures (229) [0053] is thicker than each of the third (227) semiconductor nanostructures (see figure below).
Annotated FIG. 2F below identifies the structures
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It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Lee into the structure of Jiang in view of Wu and Lin and Trivedi since Lee teaches a gate all around semiconductor device.
The ordinary artisan would have been motivated to modify Lee in combination with Jiang in view of Wu and Lin and Trivedi in the above manner for the motivation of forming the channel regions with optimal thickness to optimize the available space in the chip as semiconductor devices continue to scale down. [0002] states, “This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs.” A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Re Claim 6 Jiang in view of Wu and Lin and Trivedi and Lee teaches the method for forming a semiconductor device structure as claimed in claim 5, wherein the first semiconductor nanostructures (Lin, 210B), the second semiconductor nanostructures (210A), the third semiconductor nanostructures (210C), and the fourth semiconductor nanostructures (210D) are formed simultaneously (FIG. 9A and 10A).
Re Claim 7 Jiang in view of Wu and Lin and Trivedi and Lee teaches the method for forming a semiconductor device structure as claimed in claim 6, wherein each of the second semiconductor nanostructures (Lin, 208 in 202A region) has a substantially planar upper surface and a substantially planar lower surface (FIG. 10A, FIG. 9E better shows 208 shape as flat upper and lower surfaces).
Re Claim 8 Jiang in view of Wu and Lin and Trivedi and Lee teaches the method for forming a semiconductor device structure as claimed in claim 6, wherein each of the first semiconductor nanostructures (Wu, 407a) and the third semiconductor nanostructures (407c) has a curved upper surface and a curved lower surface (FIG. 26).
Re Claim 9 Jiang in view of Wu and Lin and Trivedi and Lee teaches the method for forming a semiconductor device structure as claimed in claim 6, further comprising:
removing (page 20 par 3 states, “The redundant gate structure 230 is then selectively removed, and a gate trench is formed in the ILD 242 (and between the gate spacers 236), thereby exposing (along the x-direction) the stack of semiconductor layers 206 and 208 Top surface and side surface. In other words, each of the semiconductor layer 208 and the remaining part of the semiconductor layer 206 is exposed on at least two side surfaces in the gate trench. Then, a suitable wet etching process is used to selectively remove the remaining part of the semiconductor layer 206 through the gate trench, without affecting the semiconductor layer 208 substantially.”) the first gate stack (Lin, 232 to right of 224 label, 232 is part of 230, FIG. 9A) and the second gate stack (232 to left of 224 label) before the first semiconductor nanostructures (210B), the second semiconductor nanostructures (210A), the third semiconductor nanostructures (210C), and the fourth semiconductor nanostructures (210D) are formed;
forming a first metal gate stack (221D to right of 224 in FIG. 10A, page 21 par 2) wrapped around the first semiconductor nanostructures (210B) and the third semiconductor nanostructures (210C); and
forming a second metal gate stack (221D to left of 224 label in FIG. 10A) wrapped around the second semiconductor nanostructures (210A).
Jiang in view of Wu and Lin and Trivedi and Lee does not explicitly teach second metal gate stack wrapped around the fourth semiconductor nanostructures.
Lee teaches a second metal gate stack (226) [0053] wrapped around the second semiconductor nanostructures and the fourth semiconductor nanostructures (see annotated FIG. 2F below claim 5 for nanostructures).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Lee into the structure of Jiang in view of Wu and Lin and Trivedi and Lee since Lee teaches a gate all around semiconductor device.
The ordinary artisan would have been motivated to modify Lee in combination with Jiang in view of Wu and Lin and Trivedi and Lee in the above manner for the motivation of forming a gate structure around the second and fourth nanostructures to optimize the available space in the semiconductor device as chips continue to scale down in size. [0002] states, “This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs.”
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Jiang et al. (CN 110828378 A) in view of Wu et al. (US 20200168715 A1) and Lin et al. (TW 202119557 A) and Trivedi et al. (US 20210280683 A1) and Lee et al. (US 20200258740 A1) and Lin (US 20220223587 A1), Lin2 hereafter.
Re Claim 10 Jiang in view of Wu and Lin and Trivedi and Lee teaches the method for forming a semiconductor device structure as claimed in claim 9, but does not teach the first metal gate stack has a first p-type work function layer wrapped around each of the first semiconductor nanostructures, the second metal gate stack has a second p-type work function layer wrapped around each of the second semiconductor nanostructures, the first metal gate stack has a first n-type work function layer wrapped around each of the third semiconductor nanostructures, and the second metal gate stack has a second n-type work function layer wrapped around each of the fourth semiconductor nanostructures.
Lin2 teaches the first metal gate stack (1010) [0056] has a first p-type work function layer ([0059] states, “…the gate metal may be a p-type work function layer, an n-type work function layer…”) wrapped around each of the first semiconductor nanostructures (402) [0058], the second metal gate stack (1050) [0056] has a second p-type work function layer wrapped around each of the second semiconductor nanostructures (402), the first metal gate stack (repeat process with 1010 as n-type) has a first n-type work function layer ([0059] states, “…the gate metal may be a p-type work function layer, an n-type work function layer…”) wrapped around each of the third semiconductor nanostructures (402), and the second metal gate stack (repeat process with 1050 as n-type) has a second n-type work function layer wrapped around each of the fourth semiconductor nanostructures (402, FIG. 10A).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Lin2 into the structure of Jiang in view of Wu and Lin and Trivedi and Lee since Lin2 teaches a gate all around semiconductor device.
The ordinary artisan would have been motivated to modify Lin2 in combination with Jiang in view of Wu and Lin and Trivedi and Lee in the above manner for the motivation of forming the gate structures to contain n-type and p-type work function layers to optimally integrate the gate metals into the device as space is critical since the feature size in the industry continues to down size. [0002] sates, “The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area.”
Claims 11, 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Ching et al. (US 9608116 B2, IDS) in view of Wu et al. (US 20200168715 A1) and Lin et al. (TW 202119557 A).
Re Claim 11 Ching teaches a method for forming a semiconductor device structure (FIG. 3), comprising:
forming a first fin structure (24, upper/left, col 4 line 48) and a second fin structure (24, lower/right) over a substrate (20, col 3 line 50), wherein each of the first fin structure (24) and the second fin structure (24) has a plurality of sacrificial layers (28, col 3 line 34) and a plurality of semiconductor layers (26, col 3 line 24) laid out in an alternating manner, and the first fin structure is substantially as wide as the second fin structure (FIG. 3);
forming a gate stack (46, col 4 line 64) wrapped around the first fin structure (24) and the second fin structure (24); and simultaneously removing the sacrificial layers (28) of the first fin structure and the second fin structure (Col 6 line 9 states, “Referring to FIG. 12A, an etching step is performed to remove silicon germanium oxide regions 40 (also refer to FIG. 9), concentrated semiconductor strips 28…”, Ching teaches removing 28 layers once, therefore all are removed simultaneously), wherein remaining portions of the semiconductor layers (26) of the first fin structure (see modified FIG. 12A below) form a plurality of first semiconductor nanostructures (remaining 26 in 1st fin), remaining portions of the semiconductor layers of the second fin structure form a plurality of second semiconductor nanostructures (remaining 26 in 2nd fin, see modified FIG. 12A below)
Modified FIG. 12A below shows the fin structures with remaining semiconductor layers (26)
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Ching does not each of the first semiconductor nano structures is thicker than each of the second semiconductor nanostructures.
Wu teaches each of the first semiconductor nanostructures (207b) [0018] is thicker than each of the second semiconductor nanostructures (407a, [0043], FIG. 19B).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Wu into the structure of Ching since Wu teaches a gate all around semiconductor device.
The ordinary artisan would have been motivated to modify Wu in combination with Ching in the above manner for the motivation of forming the fins to have different semiconductor nanostructure thickness to optimize the chip structure to allow for smaller transistors. [0003] states, “One of the goals of the semiconductor industry is to continue shrinking the size and increasing the speed of individual FETs.”
Ching in view of Wu does not teach the second stack structure is wider than the first stack structure.
Lin teaches the second stack structure (210D, page 8 par 1) is wider than the first stack structure (210C, FIG. 9A).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Lin into the structure of Ching in view of Wu since Lin teaches a gate all around semiconductor device.
The ordinary artisan would have been motivated to modify Lin in combination with Ching in view of Wu in the above manner for the motivation of forming the fins to have different semiconductor nanostructure widths to optimize the chip structure to allow for smaller transistors. Page 3 par 1 states, “With the development of integrated circuit (IC) technology toward smaller technology nodes, gate-all-around (GAA) transistors have been incorporated into SRAM to reduce chip footprint while maintaining Reasonable processing margin.”
Re Claim 21 Ching teaches a method for forming a semiconductor device structure (FIG. 2), comprising:
forming a plurality of semiconductor layers (26, col 3 line 25) and a plurality of sacrificial layers (28, col 3 line 34) laid out in an alternating manner over a substrate (20, col 2 line 63, FIG. 2);
patterning the semiconductor layers and the sacrificial layers to form a first stack structure (24 upper left, FIG. 3) and a second stack structure (24, lower right) laterally spaced apart from each other, and
removing the sacrificial layers (28) of the first stack structure (1st fin in figure under claim 11) and the second stack structure (2nd fin in figure under claim 11), wherein remaining portions of the semiconductor layers of the first stack structure form a plurality of first semiconductor nanostructures (26), remaining portions of the semiconductor layers of the second stack structure form a plurality of second semiconductor nanostructures (26, see modified FIG. 12 under claim 11).
each of the second semiconductor nanostructures is thicker than each of the first semiconductor nanostructures.
Wu teaches each of the second semiconductor nanostructures (207b) [0018] is thicker than each of the first semiconductor nanostructures (407a, [0043], FIG. 19B).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Wu into the structure of Ching since Wu teaches a gate all around semiconductor device.
The ordinary artisan would have been motivated to modify Wu in combination with Ching in the above manner for the motivation of forming the fins to have different semiconductor nanostructure dimensions to optimize the chip structure to allow for smaller transistors. [0003] states, “One of the goals of the semiconductor industry is to continue shrinking the size and increasing the speed of individual FETs.”
Ching in view of Wu does not teach Ching does not teach the second stack structure is wider than the first stack structure.
Lin teaches the second stack structure is wider than the first stack structure.
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Lin into the structure of Ching in view of Wu since Lin teaches a gate all around semiconductor device.
The ordinary artisan would have been motivated to modify Lin in combination with Ching in view of Wu in the above manner for the motivation of forming the fins to have different semiconductor nanostructure widths to optimize the chip structure to allow for smaller transistors. Page 3 par 1 states, “With the development of integrated circuit (IC) technology toward smaller technology nodes, gate-all-around (GAA) transistors have been incorporated into SRAM to reduce chip footprint while maintaining Reasonable processing margin.”
Re Claim 22 Ching in view of Wu and Lin teaches the method for forming a semiconductor device structure as claimed in claim 21, wherein the sacrificial layers (Ching, 28) of the first stack structure (use stack from 1st fin in modified FIG. 12A under claim 11) and the second stack (use stack from 1st fin in modified FIG. 12A under claim 11) structure are simultaneously removed (Col 6 line 9 states, “Referring to FIG. 12A, an etching step is performed to remove silicon germanium oxide regions 40 (also refer to FIG. 9), concentrated semiconductor strips 28…”, Ching teaches removing 28 layers once, therefore all are removed simultaneously).
Claims 12 is rejected under 35 U.S.C. 103 as being unpatentable over Ching et al. (US 9608116 B2, IDS) in view of Wu et al. (US 20200168715 A1) and Lin et al. (TW 202119557 A) and You et al. (CN 113140545 A).
Re Claim 12 Ching in view of Wu and Lin teaches the method for forming a semiconductor device structure as claimed in claim 11, but does not teach:
partially removing the first fin structure and the second fin structure to form a plurality of recesses exposing side surfaces of the semiconductor layers and the sacrificial layers of the first fin structure and the second fin structure;
forming a plurality of inner spacers covering the side surfaces of the sacrificial layers of the first fin structure and the second fin structure;
forming p-type doped epitaxial structures on the side surfaces of the semiconductor layers of the first fin structure before the first semiconductor nanostructures are formed; and
forming n-type doped epitaxial structures on the side surfaces of the semiconductor layers of the second fin structure before the second semiconductor nanostructures are formed.
You teaches partially removing the first fin structure (FIG. 12B, 52/54 stack to left of 86 groove, page 9 par 3) and the second fin structure (52/54 stack to left of 94 groove) to form a plurality of recesses (96, page 16 par 2) exposing side surfaces of the semiconductor layers (54) and the sacrificial layers (52) of the first fin structure and the second fin structure (FIG. 12B);
forming a plurality of inner spacers (98, page 16 par 3) covering the side surfaces of the sacrificial layers (52) of the first fin structure and the second fin structure (FIG. 13B);
forming p-type doped epitaxial structures (106, Page 8 par 2, “Each of the short channel region 50S and the long channel region 50L may include one or more of an n-type region50N and/or a p-type region 50P.”) on the side surfaces of the semiconductor layers (54) of the first fin structure (52/54 stack to left of 86 groove) before the first semiconductor nanostructures are formed (formed later in FIG. 19B); and
forming n-type doped epitaxial structures (106, Page 8 par 2, “Each of the short channel region 50S and the long channel region 50L may include one or more of an n-type region50N and/or a p-type region 50P.”) on the side surfaces of the semiconductor layers (54) of the second fin (52/54 stack to left of 94 groove) structure before the second semiconductor nanostructures are formed (formed later in FIG. 19B).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by You into the structure of Ching in view of Wu and Lin since You teaches a gate all around semiconductor device.
The ordinary artisan would have been motivated to modify You in combination with Ching in view of Wu and Lin in the above manner for the motivation of optimally integrating epitaxial regions around the fin structures to allow for smaller semiconductor devices than previously produced. Page 3 par 4 states, “The semiconductor industry continues to improve the integrated density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum component size, thereby allowing more components to be integrated into a given area.”
Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Ching et al. (US 9608116 B2, IDS) in view of Wu et al. (US 20200168715 A1) and Lin et al. (TW 202119557 A) and Chiang et al. (US 20210375858 A1) and Trivedi et al. (US 20210280683 A1) and Lee et al. (US 20200258740 A1).
Re Claim 13 Ching in view of Wu and Lin teaches the method for forming a semiconductor device structure as claimed in claim 11, but does not teach:
forming a third fin structure and a fourth fin structure over a substrate, wherein each of the third fin structure and the fourth fin structure has a plurality of second sacrificial layers and a plurality of second semiconductor layers laid out in an alternating manner, the third fin structure is substantially as wide as the fourth fin structure, and the third fin structure is wider than the first fin structure;
forming a second gate stack wrapped around the third fin structure and the fourth fin structure; and
simultaneously removing the second sacrificial layers of the third fin structure and the fourth fin structure, wherein remaining portions of the second semiconductor layers of the third fin structure form a plurality of third semiconductor nanostructures, remaining portions of the second semiconductor layers of the fourth fin structure form a plurality of fourth semiconductor nanostructures, each of the third semiconductor nanostructures is thicker than each of the fourth semiconductor nanostructures, and each of the fourth semiconductor nanostructures is thicker than each of the second semiconductor nanostructures.
Chiang teaches forming a third fin structure (222D) [0018] and a fourth fin (222E) structure over a substrate (202) [0015], wherein each of the third fin structure (222D) and the fourth fin structure (222E) has a plurality of second sacrificial layers (215) [0016] and a plurality of second semiconductor layers (220) laid out in an alternating manner, the third fin structure (222D) is substantially as wide as the fourth fin structure (222E), and the third fin structure (222D) is wider than the first fin structure (222B, FIG. 4);
forming a second gate stack (284, [0030], use 282 as first gate stack) wrapped around the third fin structure (222D) and the fourth fin structure (222D, FIG. 10A); and
simultaneously removing (FIG. 15A and 16A) the second sacrificial layers (215) of the third fin structure (222D) and the fourth fin structure (222E), wherein remaining portions of the second semiconductor layers (220’) [0040] of the third fin structure (222D) form a plurality of third semiconductor nanostructures (220’ layers between 270C and 270D), remaining portions of the second semiconductor layers (220’) of the fourth fin structure (222E) form a plurality of fourth semiconductor nanostructures (220’ to right of 270D).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Chiang into the structure of Ching in view of Wu and Lin since Chiang teaches a gate all around semiconductor device.
The ordinary artisan would have been motivated to modify Chiang in combination with Ching in view of Wu and Lin in the above manner for the motivation of optimally integrating a third and fourth fin structure to help the device function at a peak level and still allow for a device to not be oversized. [0002] states, “GAA devices enable aggressive scaling down of IC technologies, maintaining gate control and mitigating SCEs, while seamlessly integrating with conventional IC manufacturing processes.”
Ching in view of Wu and Lin and Chiang does not teach each of the third semiconductor nanostructures is thicker than each of the fourth semiconductor nanostructures.
Trivedi teaches each of the third semiconductor nanostructures (306B) [0049] is thicker than each of the fourth semiconductor nanostructures (308B, see image below).
Annotated FIG. 3H below identifies the third and fourth structures
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It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Trivedi into the structure of Ching in view of Wu and Lin and Chiang since Trivedi teaches a gate all around semiconductor device.
The ordinary artisan would have been motivated to modify Trivedi in combination with Ching in view of Wu and Lin and Chiang in the above manner for the motivation of forming the channel regions with optimal thickness to optimize the available space in the chip as semiconductor devices continue to scale down. [0002] states, “For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips.” A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Ching in view of Wu and Lin and Chiang and Trivedi does not teach each of the fourth semiconductor nanostructures is thicker than each of the second semiconductor nanostructures.
Lee teaches each of the fourth semiconductor nanostructures (307) [0055] is thicker than each of the second semiconductor nanostructures (309, see image below).
Annotated FIG. 3H below identifies the second and fourth structures
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It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Lee into the structure of Ching in view of Wu and Lin and Chiang and Trivedi since Lee teaches a gate all around semiconductor device.
The ordinary artisan would have been motivated to modify Lee in combination with Ching in view of Wu and Lin and Chiang and Trivedi in the above manner for the motivation of forming the channel regions with optimal thickness to optimize the available space in the chip as semiconductor devices continue to scale down. [0002] states, “This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs.” A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
Re Claim 14 Ching in view of Wu and Lin and Chiang and Trivedi and Lee teaches the method for forming a semiconductor device structure as claimed in claim 13, wherein the first semiconductor nanostructures (Chiang, 220’ in 222B portion), the second semiconductor nanostructures (220’ in 222C portion), the third semiconductor nanostructures (220’ in 222D portion), and the fourth semiconductor nanostructures (220’ in 222E portion) are formed simultaneously (FIG. 15A and 16A).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Ching et al. (US 9608116 B2, IDS) in view of Wu et al. (US 20200168715 A1) and Lin et al. (TW 202119557 A) and Chiang et al. (US 20210375858 A1) and Trivedi et al. (US 20210280683 A1) and Lee et al. (US 20200258740 A1) and Park (US 20220406919 A1).
Re Claim 15 Ching in view of Wu and Lin and Chiang and Trivedi and Lee teaches the method for forming a semiconductor device structure as claimed in claim 14, wherein each of the third semiconductor nanostructures (Chiang, FIG. 16A, 220’ between 270C and 270D) and the fourth semiconductor nanostructures (220’ to right of 270D) has a substantially planar upper surface and a substantially planar lower surface (FIG. 16A).
Ching in view of Wu and Lin and Chiang and Trivedi and Lee does not teach each of the first semiconductor nanostructures and the second semiconductor nanostructures has a dumbbell-shaped profile.
Park teaches each of the first semiconductor nanostructures (141c, 142c, and 1423c {bottom half of 143c has a dumbbell shaped profile} on left, FIG. 7) [0060] and the second semiconductor nanostructures (141c, 142c, and 1423c {bottom half of 143c has a dumbbell shaped profile} on right) has a dumbbell-shaped profile (FIG. 7).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Park into the structure of Ching in view of Wu and Lin and Chiang and Trivedi and Lee since Park teaches a gate all around semiconductor device.
The ordinary artisan would have been motivated to modify Park in combination with Ching in view of Wu and Lin and Chiang and Trivedi and Lee in the above manner for the motivation of forming the channel regions in an optimal shape to optimize the available space in the chip as semiconductor devices continue to scale down. [0002] In the semiconductor integrated circuit (IC) industry, technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation.
Claims 23 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over Ching et al. (US 9608116 B2, IDS) in view of Wu et al. (US 20200168715 A1) and Lin et al. (TW 202119557 A) and Jiang et al. (CN 110828378 A).
Re Claim 23 Ching in view of Wu and Lin teaches the method for forming a semiconductor device structure as claimed in claim 21, but does not teach one of the first semiconductor nanostructures has a curved upper surface and a curved lower surface, one of the second semiconductor nanostructures has a less-curved upper surface and a less-curved lower surface.
Jiang teaches one of the first semiconductor nanostructures (206 in 210, Page 5) has a curved upper surface and a curved lower surface, one of the second semiconductor nanostructures (206 in 212) has a less-curved upper surface and a less-curved lower surface (FIG. 13).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Jiang into the structure of Ching in view of Wu and Lin since Jiang teaches a gate all around semiconductor device.
The ordinary artisan would have been motivated to modify Jiang in combination with Ching in view of Wu and Lin in the above manner for the motivation of forming the fins to have different semiconductor nanostructure surface profiles to optimize the chip structure to allow for smaller transistors. Page 2 par 3 states, “Semiconductor integrated circuit (IC) industry has experienced fast growth. Integrated circuit material have produced several generations of integrated circuit and technique development design, wherein each generation has circuit smaller than the previous generation and more complex.”
Re Claim 25 Ching in view of Wu and Lin and Jiang teaches the method for forming a semiconductor device structure as claimed in claim 21, wherein a topmost semiconductor nanostructure (Jiang, top 206) of the second semiconductor nanostructure (212) has a curved upper surface, and a lower semiconductor nanostructure (bottom 206) of the second semiconductor nanostructure (212) has a less-curved upper surface (left side of FIG. 16D, top and bottom 206 have the same height but the bottom 206 is a wider elliptical shape and therefore has a less curved upper surface).
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Ching et al. (US 9608116 B2, IDS) in view of Wu et al. (US 20200168715 A1) and Lin et al. (TW 202119557 A) and Kim et al. (US 20220005946 A1).
Re Claim 24 Ching in view of Wu and Lin teaches the method for forming a semiconductor device structure as claimed in claim 21, but does not teach a topmost semiconductor nanostructure of the second semiconductor nanostructure has a curved upper surface and a less-curved lower surface.
Kim teaches a topmost semiconductor nanostructure (CH1) [0033] of the second semiconductor nanostructure (105) [0032] has a curved upper surface and a less-curved lower surface (FIG. 2).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Kim into the structure of Ching in view of Wu and Lin since Kim teaches a gate all around semiconductor device.
The ordinary artisan would have been motivated to modify Kim in combination with Ching in view of Wu and Lin in the above manner for the motivation of optimizing nanostructure surface profiles to improve the improved electrical characteristics and reliability in the semiconductor device. [0005] states, “Example embodiments provide a semiconductor device having a channel including a three-dimensional structure, with improved electrical characteristics and reliability and a method of fabricating the same.”
Conclusion
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/KENNETH MARK SIPLING/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 2/24/26