Prosecution Insights
Last updated: April 19, 2026
Application No. 18/356,244

SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

Non-Final OA §103
Filed
Jul 21, 2023
Examiner
WARREN, MATTHEW E
Art Unit
2815
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company Ltd.
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
2y 8m
To Grant
93%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allow Rate
862 granted / 986 resolved
+19.4% vs TC avg
Moderate +6% lift
Without
With
+5.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
25 currently pending
Career history
1011
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
47.8%
+7.8% vs TC avg
§102
39.7%
-0.3% vs TC avg
§112
8.9%
-31.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 986 resolved cases

Office Action

§103
DETAILED ACTION This Office Action is in response to the Election filed on November 20, 2025. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election of Group II, species B in the reply filed on November 20, 2025 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)). The applicant asserts that the amendments to the claims amended claims 1-10 and new claims 21-24 corresponds to Group II invention and species B, including claims 11-16. The examiner believes that although the claims are amended, they still present separate species within the Group II invention. For instance, despite the amendment, species A discloses depositing a ferroelectric inducing layer, species B discloses providing a transistor having a gate stack and epitaxial layers, while species C discloses forming a second electrode on the first electrode. These elements describe methods of forming different semiconductor devices and therefore represent different embodiments. For these reasons, the examiner believes that the claims 11-16 best represent Group II, species B, which the applicant elects. Claims 1-10 and 21-24 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention and species, there being no allowable generic or linking claim. Election was made without traverse in the reply. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Manipatruni et al. (US Pub. 2024/0347397 A1) in view of Lee et al. (US Pub. 2024/0196623 A1). In re claim 11, Manipatruni et al. discloses (figs. 9, 10; [0118-0132,0139]) a method of forming a semiconductor device, comprising: providing a transistor (1002), wherein the transistor comprises a gate stack (1004) on a substrate and epitaxial layers (1010, 1012; [0125]) in the substrate at two sides of the gate stack; and forming a ferroelectric stack (801) over and electrically connected to the transistor, wherein a method of forming the ferroelectric stack comprises: forming a first electrode (802); forming a ferroelectric layer comprising HfZrO on the first electrode [0139], and forming a second electrode (806) on the ferroelectric layer. Manipatruni discloses all of the elements of the claims except wherein the ferroelectric layer is formed at a low temperature process of about 350°C or less and has a remanent polarization (Pr) of about 10 uC/cm² or more. It would have been obvious to one of ordinary skill in the art at the time the invention was made to the process temperature or the remanent polaraization of the ferroelectric to be any desired parameter, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). However, Lee et al. discloses [0074-0086] a method of forming a HfZrO ferroelectric layer wherein the ferroelectric layer is formed at a low temperature process of about 350°C or less [0076,0077] and has a remanent polarization (Pr) of about 10 uC/cm² or more [0075]. With this configuration, the ferroelectric film is formed having excellent reliability and electrical characteristics [0085,0089]. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to modify the semiconductor device of Manipatruni by forming the ferroelectric layer at a low temperature as taught by Lee to provide a ferroelectric layer having high reliability and good electrical characteristics. In re claim 12, Manipatruni and Lee disclose all of the elements of the claims including the ferroelectric layer having a thickness of about 1 to 10 nm (Lee; figs. 6, 24; [090]). In re claim 13, Manipatruni and Lee disclose all of the elements of the claims including a post-annealing process of greater than 350°C is absent after depositing the ferroelectric layer and before forming the second electrode. Lee does not disclose the post annealing process after the first annealing process. Claims 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Manipatruni et al. (US Pub. 2024/0347397 A1) in view of Lee et al. (US Pub. 2024/0196623 A1) as applied to claim 11 above, and further in view of Chia et al. (US Pub. 2021/0398990 A1). In re claims 14 and 15, Manipatruni and Lee show all of the elements of the claims except wherein the first electrode comprises Ru, the second electrode comprises Ru, and the HfZrO of the ferroelectric layer is in physical contact with the Ru of the first electrode and the Ru of the second electrode. Chia shows (fig. 8) a semiconductor device wherein an electrode (128,130) comprises Ru (128) and is in direct physical contact with the ferroelectric layer (126). In addition, the electrode has a multiple-layer structure comprising a Ru-based layer (128) and a Ru-free layer (130), and the Ru-based layer is in contact with the ferroelectric layer (126). With this configuration, the Ru layer as an interface layer helps induce the adjacent ferroelectric layer to have the orthorhombic phase [0105,0111,0112]. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to modify the device of Manipatruni and Lee by forming the electrode comprising Ru as taught by Chia to induce an orthorhombic phase in the adjacent ferroelectric. In re claim 16, the combined references do not specifically disclose a sidewall of the first electrode layer is protruded from a sidewall of the ferroelectric layer. However, it is well known in the art to form electrode components having any size or shape in a capacitor device to modulate the capacitance. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Islam Raisul (WO-2023004379-A1), Kim Sun Kook (KR-20240146494-A), and Byung Jin Cho (KR-20240142092-A) also disclose various elements of the claims. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW E WARREN whose telephone number is (571)272-1737. The examiner can normally be reached Mon-Fri 10am - 6pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MATTHEW E WARREN/Primary Examiner, Art Unit 2815
Read full office action

Prosecution Timeline

Jul 21, 2023
Application Filed
Jan 09, 2026
Non-Final Rejection — §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
93%
With Interview (+5.6%)
2y 8m
Median Time to Grant
Low
PTA Risk
Based on 986 resolved cases by this examiner. Grant probability derived from career allow rate.

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