Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 12-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 12 states: “a dummy pattern to be formed …. the dummy pattern is proximal to and at least partially between different portions of the mark pattern; removing the dummy pattern from the circuit layout”; it is not clear whether the dummy pattern has previously been formed; there is at least a lack antecedent basis, as shown below.
Claim 12 recites the limitation "a dummy pattern to be formed …. the dummy pattern is proximal to and at least partially between different portions of the mark pattern; removing the dummy pattern from the circuit layout" in lines 3-6. There is insufficient antecedent basis for this limitation in the claim.
For purpose of examination, claim 12 will be treated as “a dummy pattern to be formed …. the dummy pattern to be formed is proximal to and at least partially between different portions of the mark pattern; removing the dummy pattern to be formed from the circuit layout".
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 and 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Koketsu et al. (US 2009/0206411 A1) in view of Huang (US 2014/0264961 A1).
Regarding independent claim 1: Koketsu teaches (e.g., Figs. 9-24 and 30; [0021]-[0038]) a method of manufacturing a semiconductor structure ([0080]-[0135]), comprising:
providing a substrate ([0083]: 1S), including a device layer ([0105]),
forming an interconnect structure ([0125]: PLG1/L1/L2 in interconnect layers 8/9/10/11, [0082], [0086]-[0087]) over the device layer;
forming a first conductive feature ([0087]-[0088]: P1b) and at least one second conductive feature ([0087]-[0088]: P1b; [0144]: second conductive feature P1b adjacent first/center P1b) in the interconnect structure,
wherein the first conductive feature is recognizable as a first identification mark ([0087]-[0088]: P1b; [0144]: center P1b configured as part of alignment mark element AM, Fig. 30), and
the at least one second conductive feature ([0087]-[0088]: P1b; [0144]: second conductive feature P1b adjacent first/center P1b) is disposed between different portions of the first conductive feature; and
forming a third conductive feature ([0086]-[0088] and [0144]: P1a) at a first elevation over a second elevation of the first conductive feature (P1b),
wherein the third conductive feature (P1a) overlaps the first conductive feature (P1b) vertically and is recognizable as a second identification mark ([0086]-[0088] and [0144]: P1a as well as P1b are in the alignment mark and function as second and first identification marks respectively), and
a space other than the third conductive feature in the logo region at the first elevation is filled with a dielectric material ([0066]-[0087]: 10).
Koketsu does not expressly teach that a logo region is defined in a peripheral region of the substrate.
Huang teaches (e.g., Fig. 1) a method of manufacturing a semiconductor structure comprising a substrate ([0012]: 30);
Huang further teaches that a logo region ([0013]-[0014]: 40B) is defined in a peripheral region of the substrate ([0012]-[0014]: 30).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the method of Koketsu, the logo region being defined in a peripheral region of the substrate, as taught by Huang, for the benefits of labeling different wafers in a stack by different an alphanumeric characters and thus identify all wafers, allowing effective tracking of manufactured chips and wafers.
Regarding claim 2: Koketsu and Huang teach the claim limitation of the method of claim 1, on which this claim depends,
wherein the first identification mark includes a first character Koketsu: ([0087]-[0088]: P1b; [0144]: the first identification mark P1b in the center includes a character which is its shape),
the second identification mark includes a second character (Koketsu: [0087]-[0088]: P1b; [0144]: the second identification mark P1b adjacent first/center identification mark P1b, includes a character which is its shape), and
the first character and the second character have a same configuration and vertically overlap one another (Koketsu: [0087]-[0088]: P1b; [0144]: the first character and the second character have a same configuration, which their shape and they overlap on a vertical plane).
Regarding claim 3: Koketsu and Huang teach the claim limitation of the method of claim 1, on which this claim depends,
wherein the first or second identification mark is selected from a group consisting of a numeral, a punctuation mark, a word, an English letter, and a combination thereof (Koketsu: [0087]-[0088]: the shape of the first or second identification mark indicate a punctuation mark).
Regarding claim 4: Koketsu and Huang teach the claim limitation of the method of claim 1, on which this claim depends,
wherein the third conductive feature includes aluminum (Koketsu: [0096]: “stripe-shaped, grating-shaped, or dot-shaped fine pattern formed by an aluminum layer can be used. In this case, the diffusion reflection layer formed in the peripheral region of the cross-shaped mark main body part is formed in the same layer as that of the mark main body part” the aluminum material used is for forming the structure described as dot-shaped fine pattern, which is the alignment mark; (“[0100] and [0144]”) and is disposed above the interconnect structure (Koketsu: [0125]: PLG1/L1 in interconnect layers 8/9/10/11, [0082] and [0086]-[0087]).
Regarding claim 5: Koketsu and Huang teach the claim limitation of the method of claim 1, on which this claim depends,
wherein the third conductive features (Koketsu: [0086]-[0088] and [0144]: P1a) is disposed in one of top two metal line layers of the interconnect structure (Koketsu: Fig. 9; [0086]-[0088] and [0144]).
Regarding claim 6: Koketsu and Huang teach the claim limitation of the method of claim 5, on which this claim depends,
wherein the third conductive feature is disposed in a topmost metal layer of the interconnect structure, and the method further comprises:
forming a passivation layer (Koketsu: [0082]: 11) at a third elevation over the third conductive feature (Koketsu: [0086]-[0088] and [0144]: P1a),
wherein the second identification mark of the third conductive feature is recognizable through the passivation layer from a top view (Fig. 10: [0081]-[0083]: the light rays reaches the second identification mark of the third conductive feature; thus the second identification mark of the third conductive feature is recognizable through the passivation layer from a top view).
Regarding claim 7: Koketsu and Huang teach the claim limitation of the method of claim 6, on which this claim depends, further comprising:
forming a plurality of conductive pads (Koketsu: [0133]: L3 considered as pad; “ the third layer wiring L3 (pad)”, as disclosed in [0133]; Left side L3 and Right side L3) at the third elevation,
wherein the plurality of conductive pads (Koketsu: L3) are surrounded by the passivation layer (Koketsu: 11) and separated from the third conductive feature (Koketsu: P1a) from a top view (Koketsu: Figs. 1 and 5 show top view in connection with Fig. 9 the plurality of conductive pads are separated from the third conductive feature).
Regarding claim 9: Koketsu and Huang teach the claim limitation of the method of claim 1, on which this claim depends,
wherein the first conductive feature is disposed in a metal line layer (Koketsu: Fig. 10; [0086] and [0090]; the first conductive feature P1b is disposed in a metal line layer within inter-metal layer 9) below top two metal line layers of the interconnect structure (koketsu: [0125]: PLG1/L1/L2), and the first conductive feature includes a plurality of segments parallel to one another (koketsu: [0086]-[0088] and [0125]: P1b).
Regarding claim 10: Koketsu and Huang teach the claim limitation of the method of claim 1, on which this claim depends,
wherein the first conductive feature (koketsu: [0087]-[0088] and [0125]: P1b) is electrically isolated from the third conductive feature (koketsu: [0087]-[0088] and [0125]: P1a), and the first conductive feature and the third conductive feature are electrically isolated from all other conductive features of the substrate (Fig. 10; [0086]-[0088], [0125] and [0144]: first conductive feature and the third conductive feature P1b and P1a are electrically isolated by insulating layers 9 and 10).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Koketsu et al. (US 2009/0206411 A1) in view of Huang (US 2014/0264961 A1) as applied above and further in view of Chen et al. (US 10,504,852 B1).
Regarding claim 11: Koketsu and Huang teach the claim limitation of the method of claim 1, on which this claim depends,
wherein the first conductive feature includes a first portion having a first orientation (Koketsu: [0087]-[0088]: first conductive feature P1b includes a first portion having a first orientation, horizontal direction) and a second portion having a second orientation (Koketsu: [0087]-[0088]: first conductive feature P1b includes a first portion having a second orientation, vertical direction), and
Koketsu as modified by Huang does not expressly teach that a region between the first portion and the second portion includes no conductive materials.
Chen teaches (e.g., Fig. 1 and Fig. 9) a method comprising a first conductive feature includes a first portion having a first orientation and a second portion having a second orientation (Col. 9, Lines 17-23: AM1);
Chen further teaches that a region between the first portion and the second portion includes no conductive materials (Fig. 9; Col. 9, Lines 17-23: AM1).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the method of Koketsu as modified by Huang, the
region between the first portion and the second portion that includes no conductive materials, as taught by Chen, for the benefits of creating a contrast with region between the first portion and the second portion, and thus improve visibility of the alignment mark and therefore increase alignment process accuracy.
Claims 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over Koketsu et al. (US 2009/0206411 A1) in view of Sun et al. (US 2019/0067204 A1) and Fu et al. (US 2011/0016443 A1).
Regarding independent claim 12: Koketsu teaches (e.g., Figs. 9-24 and 30; [0021]-[0038]) a method for manufacturing a semiconductor structure, comprising:
receiving a circuit layout (Fig. 1 and Fig. 10; [0086]), that includes a circuit pattern ([0069] and [0086]: pattern including gate electrode G/ p-type well PWL and region 6), a mark pattern ([0086]: pattern including MK1), and
a dummy pattern to be formed (dummy pattern is intended to be formed, not yet formed) on a same material layer (material layer intended for dummy pattern formation within layers 8/9/10/11, [0082], [0086]-[0087]) over an integrated circuit (IC) substrate ([0069] and [0086]: 1S),
wherein the circuit pattern ([0069] and [0086]: pattern including gate electrode G/ p-type well PWL and region 6) is distant from the mark pattern (Fig. 10; ([0086]: pattern including MK1).
Koketsu does not expressly teach that the dummy pattern to be formed is proximal to and at least partially between different portions of the mark pattern;
removing the dummy pattern to be formed from the circuit layout; and
generating a modified circuit layout for circuit fabrication without the dummy pattern to be formed.
Sun teaches (e.g., Fig. 9) a method for manufacturing a semiconductor structure, comprising a dummy pattern ([0031]: 118) and a mark pattern ([0031]: 124);
Sun further teaches that the dummy pattern ([0031]: 118) is proximal to and at least partially between different portions of the mark pattern ([0031]: 124).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the method of Koketsu, the dummy pattern to be formed being proximal to and at least partially between different portions of the mark pattern, as taught by Sun for the benefits of increasing the alignment marks visibility during alignment process and thus improving bonding process and deposition process accuracy, and therefore, improving manufacturing yield.
Fu teaches (e.g., Fig. 8) a method for manufacturing a semiconductor structure, comprising:
removing a dummy pattern to be formed from a circuit layout (Fig. 8 at step 470, [0041]-[0042]); and
generating a modified circuit layout for circuit fabrication without the dummy pattern to be formed (Fig. 8 at step 480, [0041]-[0042]).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the method of Koketsu as modified by Sun, the method comprising removing the dummy pattern to be formed from the circuit layout; and generating a modified circuit layout for circuit fabrication without the dummy pattern to be formed for the benefits of meeting the desired manufacturing requirements.
Regarding claim 13: Koketsu, Sun and Fu teach the claim limitation of the method of claim 12, on which this claim depends, further comprising:
transferring the modified circuit layout to a conductive layer (Fu: [0008] and [0044]; claim 19).
Regarding claim 14: Koketsu, Sun and Fu teach the claim limitation of the method of claim 12, on which this claim depends,
Koketsu as modified by Sun and Fu teaches that the conductive layer is a topmost metal line layer of an interconnect structure (Koketsu: [0125]: PLG1/L1/L2 in interconnect layers 8/9/10/11, [0082], [0086]-[0087]).
Regarding claim 15: Koketsu, Sun and Fu teach the claim limitation of the method of claim 12, on which this claim depends, further comprising:
Koketsu as modified by Sun and Fu teaches fragmenting the mark pattern to generate a fragmented mark pattern (Fu: [0044]) having a plurality of segments configured in parallel (koketsu: [0086]-[0088] and [0125]: P1b); and
transferring the modified circuit layout to a layer of an interconnect structure (Fu: [0008], [0041] and [0044]; claim 19).
Claims 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 10,504,852 B1) in view of Sun et al. (US 2019/0067204 A1) and Hatano (US 2009/0023266 A1).
Regarding independent claim 16: Chen teaches (e.g., Figs. 1-2) a semiconductor structure, comprising:
a substrate (Col. 5, Lines 27-34: #102), including a cell region (Col. 5, Lines 27-34: #20),
a peripheral region (Col. 5, Lines 27-34: #22) surrounding the cell region, and
a logo region in the peripheral region;
a first metal layer (Col. 4, Lines 60-67: copper layer BV1), disposed over the substrate and comprising:
a first conductive feature (Col. 4, Lines 60-67: first conductive feature BV1) in the cell region (20);
wherein the third conductive feature is disposed between different portions of the second conductive feature and configured as a dummy pattern; and
a second metal layer (Col. 5, Lines 60-64: metal layer BV2), disposed over the first metal layer (BV1) and comprising:
a fourth conductive feature (Col. 5, Lines 60-64: BV2 represents a fourth conductive feature) in the cell region, electrically connected to the first conductive feature (BV1);
Chen does not expressly teach
a second conductive feature in the logo region,
wherein the second conductive feature is recognizable as a first identification mark; and
a third conductive feature in the logo region adjacent to the second conductive feature,
a fifth conductive feature in the logo region, overlapping the second conductive feature,
wherein the fifth conductive feature is recognizable as a second identification mark; and
a dielectric layer, surrounding the fifth conductive feature,
wherein the second metal layer in the logo region consists of the fifth conductive feature and the dielectric layer.
Sun teaches (e.g., Figs. 1-2 and 9) a method for manufacturing a semiconductor structure, comprising a logo region (Figs. 1-2, [0023]: region 20 corresponds to a logo region because the lines form a logo);
Sun further teaches
a second conductive feature ([0024]: 122) in the logo region,
wherein the second conductive feature is recognizable as a first identification mark ([0024]: 122 usable as first identification mark); and
a third conductive feature ([0024]: 112) in the logo region adjacent to the second conductive feature (122),
a fifth conductive feature ([0024]: 124) in the logo region, overlapping the second conductive feature (122),
wherein the fifth conductive feature is recognizable as a second identification mark ([0024]: fifth conductive feature 124 usable as first identification mark); and
a layer (120), surrounding the fifth conductive feature (124).
It would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the method of Chen, the second conductive feature in the logo region, wherein the second conductive feature is recognizable as a first identification mark; and a third conductive feature in the logo region adjacent to the second conductive feature, a fifth conductive feature in the logo region, overlapping the second conductive feature, wherein the fifth conductive feature is recognizable as a second identification mark, as taught by Sun, for the benefits of accurately forming the different masking levels and thus improve manufacturing reliability.
Hatano teaches (e.g., Fig. 11) a semiconductor structure, comprising a logo region ([0053]-[0055]: Dc/Mb1/Ma1 shows a logo);
Hatano further teaches a dielectric layer ([0053]: ISL), surrounding a fifth conductive feature ([0053]: layer Dc in layer Lc is a fifth conductive feature),
wherein a second metal layer ([0053]-[0055]: metal layer used for Dc; [0027] and [0052]-[0053]: metal wire formed by damascene) in the logo region consists of the fifth conductive feature and the dielectric layer (ISL).
Therefore, it would have been obvious to a person of ordinary skill in the art at the time of the effective filing date to include in the method of Chen as modified by Sun, the dielectric layer, surrounding the fifth conductive feature, wherein the second metal layer in the logo region consists of the fifth conductive feature and the dielectric layer, as taught by Hatano, for the benefits of increasing the contrast and improve the overlayer accuracy and as a results improve photomasking quality.
Regarding claim 17: Chen, Sun and Hatano teach the claim limitation of the semiconductor structure of claim 16, on which this claim depends,
wherein the fifth conductive feature (Sun: [0024]: 124/ (Sun: [0024]: 122)) is electrically isolated from the second conductive feature (Sun: [0024]: 122 or (Sun: [0024]: 124)).
Regarding claim 18: Chen, Sun and Hatano teach the claim limitation of the semiconductor structure of claim 16, on which this claim depends,
wherein the dielectric layer (Hatano: ISL) in the logo region encircled the fifth conductive feature (Hatano: [0053]: layer Dc in layer Lc is a fifth conductive feature).
Regarding claim 19: Chen, Sun and Hatano teach the claim limitation of the semiconductor structure of claim 16, on which this claim depends,
wherein the second conductive feature comprises a plurality of segments arranged parallel to one another (Chen: Col. 5, Lines 60-64: metal layer BV2 includes a left side segment and a right side segment arranged parallel to one another).
Regarding claim 20: Chen, Sun and Hatano teach the claim limitation of the semiconductor structure of claim 16, on which this claim depends,
wherein an entirety of a top surface of the fifth conductive feature is covered by the dielectric layer (Hatano: [0053]: the fifth conductive feature is covered by the dielectric layer ISL).
Allowable Subject Matter
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 8: the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a method of manufacturing a semiconductor structure comprising:
“the first conductive feature and the at least one second conductive features include a same conductive material, and the third conductive feature includes a conductive material different from that of the first conductive feature”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HERVE-LOUIS Y ASSOUMAN whose telephone number is (571)272-2606. The examiner can normally be reached M-F: 08:30 AM-5:30 PM.
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/HERVE-LOUIS Y ASSOUMAN/ Examiner, Art Unit 2812