DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1,2, 5-7, and 28 is/are rejected under 35 U.S.C. 102(a)(1) as being unpatentable over Deng et al. US 2012/0185812 A1 (“Deng”).
As to claim 1, Deng discloses a structure, comprising:
a first semiconductor structure having a first channel with a first channel width (Figure 2 or Paragraphs 25 or 41 – e.g., FETs, e.g., 211a); and
a second semiconductor structure having a second channel with a second channel width different from the first channel width (Figure 2 or Paragraphs 25 or 41 – e.g., FETs with a different channel width, e.g., 211b), wherein the first channel and the second channel are in contact with each other (Figure 2 or Paragraphs 25 or 41 – e.g., “connected to…the same electrical sub-circuit terminals”).
As to claim 2, Deng discloses the structure of claim 1. Deng further discloses wherein the first semiconductor structure comprises a high speed performance semiconductor device (Figure 2 or Paragraphs 25 or 41 – e.g., FETs, e.g., 211a).
As to claim 5, Deng discloses the structure of claim 1. Deng further discloses wherein a first gate of the first semiconductor structure is coupled to a second gate of the second semiconductor structure (Figure 2 or Paragraphs 25 or 41 – e.g., “connected to…the same electrical sub-circuit terminals”).
As to claim 6, Deng discloses the structure of claim 1. Deng further discloses wherein a first gate of the first semiconductor structure is decoupled to a second gate of the second semiconductor structure (Figure 2 or Paragraphs 25 or 41 – e.g., nearly identical elements may be coupled, elements which are not nearly identical would be decoupled).
As to claim 7, Deng discloses the structure of claim 1. Deng further discloses wherein a gate of the second semiconductor structure is coupled to a reference voltage, and wherein the reference voltage is a voltage drain or a voltage source (Paragraphs 22 or 29 – e.g., necessary in operating according to a power supply voltage).
Claim 28 recites elements similar to claim 1, and is rejected for the same reasons.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 3, 4, 10, 21, and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Deng as applied to claim 1 above, and further in view of Chen et al. US 2002/0163835 A1 (“Chen”).
As to claim 3, Deng discloses the structure of claim 1. Deng teaches multiple semiconductor structures including linked transistors, but does not explicitly disclose the additional elements of claim 3. However, the missing element is well known in the art because while disclosing circuit configurations, Chen teaches combinations of active and passive components and dummy cells used as part of a transistor and current source configuration (Chen Figure 4A-B or Paragraph 37). It would have been obvious to one having ordinary skill in the art at the time the invention was made for the second semiconductor structure to comprises a passive semiconductor device because similar configurations were well known in the art at the time the invention was made.
As to claim 4, Deng discloses the structure of claim 1. Deng teaches multiple semiconductor structures including linked transistors, but does not explicitly disclose the additional elements of claim 4. However, the missing element is well known in the art because while disclosing circuit configurations, Chen teaches combinations of active and passive components and dummy cells used as part of a transistor and current source configuration (Chen Figure 4A-B or Paragraph 37). It would have been obvious to one having ordinary skill in the art at the time the invention was made to have a dummy gate, the dummy gate having a dummy gate width (a width necessary in a gate) because similar configurations were well known in the art at the time the invention was made.
As to claim 10, Deng and Chen disclose the structure of claim 4. Deng and Chen further disclose wherein the dummy gate width is substantially similar to a first channel gate width of the first semiconductor structure or is substantially similar to a second channel gate width of the second semiconductor structure (Deng Figure 2 or Paragraphs 25 or 41 – e.g., FETs/structures associated with particular channel widths).
Claim 21 recites elements similar to claims 1-3, and is rejected for the same reasons.
Claims 25 recites elements similar to claim 6, and is rejected for the same reasons.
Allowable Subject Matter
Claims 8, 9, 22-24, 26, 27, 29, and 30 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art does not teach or suggest a structure or method having the combination of elements/steps of the claims including, among other elements, the doping and spacing or relative width relations of the claims, in combination with the structural and connectivity details of the claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRYCE M AISAKA whose telephone number is (571)270-5808. The examiner can normally be reached M-F: 6:30AM-5:00PM PT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at (571)272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRYCE M AISAKA/Primary Examiner, Art Unit 2851
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