DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-15, 21-25 in the reply filed on 09/30/25 is acknowledged.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
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Claim(s) 1-15, 21-25 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim(s) 10,13 of U.S. Patent No. 11710657, in view of Fan (US PG Pub. No. 2016/0379932, hereinafter Fan).
Regarding claim 1, claim(s) 10, 13 of US Patent 11710657 recited “A device comprising: a first oxide layer disposed over a substrate; a first material layer disposed over the first oxide layer; a second oxide layer disposed over the first material layer; a second material layer disposed over the second oxide layer, wherein a composition of the second material layer is different than the first material layer; a third oxide layer disposed over the second material layer; a first interconnect structure disposed in and extending through the first oxide layer and physically contacting an IC device feature formed on the substrate; a second interconnect structure disposed in the first material layer and the second oxide layer and physically contacting the first interconnect structure, wherein: the second interconnect structure is free of a barrier layer along sidewalls thereof and the second interconnect structure includes a ruthenium layer, and an air gap is disposed between sidewalls of the ruthenium layer and the second oxide layer, wherein a width of the air gap is substantially the same as a thickness of the first material layer; and a via disposed in the third oxide layer, the second material layer, and the second oxide layer, wherein the via physically contacts the second interconnect structure; wherein the via includes a first via portion disposed in the third oxide layer and a second via portion disposed in the second oxide layer, wherein a first width of the first via portion is greater than a second width of the second via portion and a third width of the second interconnect structure is less than the second width”
Claim(s) 10, 13 of US Patent 11710657 do not disclose an interconnect structure comprising: a source/drain contact disposed in an insulator layer; wherein the local contact is disposed on the source/drain contact;
Fan disclose a disclose an interconnect structure comprising: a source/drain contact (210) disposed in an insulator layer (212)_; wherein the local contact(218) is disposed on the source/drain contact.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Fan to the teachings of US Patent 11710657 in order to minimize parasitic resistance [0013, Fan].
Re claim 2 US Patent 11710657 and Fan disclose the interconnect structure of claim 1, wherein the metal is titanium US Patent 11710657[0015 of Fan].
Re claim 3 US Patent 11710657 and Fan disclose the interconnect structure of claim 1, wherein: the insulator layer includes a first oxide layer[0016 of Fan], a second oxide layer, and an amorphous silicon layer between the first oxide layer and the second oxide layer; the source/drain contact is disposed in the first oxide layer and the local contact is disposed in the second oxide layer and the amorphous silicon layer; the air gap is between the metal-comprising layer and the amorphous silicon layer; and the air gap is between the ruthenium-comprising layer and the second oxide layer[0016 of Fan].
Re claim 4 US Patent 11710657 and Fan disclose the interconnect structure of claim 3, wherein the air gap has a third width, the amorphous silicon layer has a thickness, and the third width is about equal to the thickness[US Patent 11710657].
Re claim 5 US Patent 11710657 and Fan disclose the interconnect structure of claim 1, wherein:the insulator layer includes a first oxide layer, a second oxide layer, and an amorphous carbon layer between the first oxide layer and the second oxide layer;the source/drain contact is disposed in the first oxide layer and the local contact is disposed in the second oxide layer and the amorphous carbon layer;the air gap is between the metal-comprising layer and the amorphous carbon layer; andthe air gap is between the ruthenium-comprising layer and the second oxide layer[0016 of Fan].
Re claim 6 US Patent 11710657 and Fan disclose the interconnect structure of claim 5, wherein the air gap has a third width, the amorphous carbon layer has a thickness, and the third width is about equal to the thickness[US Patent 11710657].
Re claim 7 US Patent 11710657 and Fan disclose the interconnect structure of claim 1, wherein: the insulator layer includes a first oxide layer, a second oxide layer, a third oxide layer, and a metal oxide layer between the second oxide layer and the third oxide layer; the source/drain contact is disposed in the first oxide layer and the local contact is disposed in the second oxide layer; and a thickness of the metal oxide layer is less than a distance between a top surface of the second oxide layer [0016 of Fan] and a top surface of the ruthenium layer.
Re claim 8 US Patent 11710657 and Fan disclose the interconnect structure of claim 1, wherein the metal-comprising layer has a first thickness, the ruthenium-comprising layer has a second thickness, and a ratio of the first thickness to the second thickness is about 1:2 to about 1:50[US Patent 11710657].
Re claim 9 US Patent 11710657 and Fan disclose the interconnect structure of claim 8, wherein the first thickness is about 1 nm to about 5 nm, and the second thickness is about 10 nm to about 50 nm[US Patent 11710657].
Regarding claim 10, claim(s) 10, 13 of US Patent 11710657 recited “A device comprising: a first oxide layer disposed over a substrate; a first material layer disposed over the first oxide layer; a second oxide layer disposed over the first material layer; a second material layer disposed over the second oxide layer, wherein a composition of the second material layer is different than the first material layer; a third oxide layer disposed over the second material layer; a first interconnect structure disposed in and extending through the first oxide layer and physically contacting an IC device feature formed on the substrate; a second interconnect structure disposed in the first material layer and the second oxide layer and physically contacting the first interconnect structure, wherein: the second interconnect structure is free of a barrier layer along sidewalls thereof and the second interconnect structure includes a ruthenium layer, and an air gap is disposed between sidewalls of the ruthenium layer and the second oxide layer, wherein a width of the air gap is substantially the same as a thickness of the first material layer; and a via disposed in the third oxide layer, the second material layer, and the second oxide layer, wherein the via physically contacts the second interconnect structure; wherein the via includes a first via portion disposed in the third oxide layer and a second via portion disposed in the second oxide layer, wherein a first width of the first via portion is greater than a second width of the second via portion and a third width of the second interconnect structure is less than the second width”
Claim(s) 10, 13 of US Patent 11710657 do not disclose an interconnect structure comprising: a device-level contact layer; a local contact layer disposed directly on the device-level contact layer, and a metal oxide layer, wherein the metal oxide layer is between the first dielectric layer and the second dielectric layer and the metal oxide layer is disposed on a top and sidewalls of the first dielectric layer.
Fan disclose an interconnect structure comprising: a device-level contact layer(210); a local contact layer(218) disposed directly on the device-level contact layer, and a metal oxide layer[0016], wherein the metal oxide layer is between the first dielectric layer(102a/b) and the second dielectric layer(102a/b) and the metal oxide layer is disposed on a top and sidewalls of the first dielectric layer.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Fan to the teachings of US Patent 11710657 in order to minimize parasitic resistance [0013, Fan].
Re claim 11 US Patent 11710657 and Fan disclose the interconnect structure of claim 10, wherein the device-level contact layer includes a source/drain contact disposed in a third dielectric layer, wherein the ruthenium- comprising contact[US Patent 11710657] is disposed directly on the source/drain contact and the first dielectric layer is disposed directly on the third dielectric layer.
Re claim 12 US Patent 11710657 and Fan disclose the interconnect structure of claim 10, wherein the device-level contact layer includes a source/drain contact disposed in a third dielectric layer and the local contact layer further includes an amorphous material layer, wherein the ruthenium-comprising contact[US Patent 11710657] is disposed directly on the source/drain contact, the amorphous material layer is between the first dielectric layer and the third dielectric layer, and the air gaps are disposed between the sidewalls of the ruthenium- comprising contact[US Patent 11710657] and the amorphous material layer.
Re claim 13 US Patent 11710657 and Fan disclose the interconnect structure of claim 10, wherein the metal oxide layer is a first metal oxide layer, the device-level contact layer includes a source/drain contact disposed in a third dielectric layer, and the local contact layer further includes a second metal oxide layer, wherein the ruthenium-comprising contact[US Patent 11710657] is disposed directly on the source/drain contact, the second metal oxide layer is between the first dielectric layer and the third dielectric layer, the air gaps are disposed between the sidewalls of the ruthenium-comprising contact[US Patent 11710657] and the second metal oxide layer, and the first metal oxide layer includes a first metal that is different than a second metal of the second metal oxide layer.
Re claim 14 US Patent 11710657 and Fan disclose the interconnect structure of claim 10, wherein the device-level contact layer includes a source/drain contact disposed in a third dielectric layer and the local contact layer further includes a silicon-and-nitrogen-comprising layer, wherein the ruthenium-comprising contact[US Patent 11710657] is disposed directly on the source/drain contact, the silicon-and-nitrogen-comprising layer is betweenthe first dielectric layer and the third dielectric layer, and the air gaps are disposed between the sidewalls of the ruthenium-comprising contact[US Patent 11710657] and the silicon-and-nitrogen-comprising layer.
Re claim 15 US Patent 11710657 and Fan disclose the interconnect structure of claim 10, wherein the ruthenium-comprising contact[US Patent 11710657] includes a ruthenium plug disposed over a titanium-comprising layer, wherein the titanium- comprising layer is between the ruthenium plug and the device-level contact layer.
Regarding claim 21, claim(s) 10, 13 of US Patent 11710657 recited “A device comprising: a first oxide layer disposed over a substrate; a first material layer disposed over the first oxide layer; a second oxide layer disposed over the first material layer; a second material layer disposed over the second oxide layer, wherein a composition of the second material layer is different than the first material layer; a third oxide layer disposed over the second material layer; a first interconnect structure disposed in and extending through the first oxide layer and physically contacting an IC device feature formed on the substrate; a second interconnect structure disposed in the first material layer and the second oxide layer and physically contacting the first interconnect structure, wherein: the second interconnect structure is free of a barrier layer along sidewalls thereof and the second interconnect structure includes a ruthenium layer, and an air gap is disposed between sidewalls of the ruthenium layer and the second oxide layer, wherein a width of the air gap is substantially the same as a thickness of the first material layer; and a via disposed in the third oxide layer, the second material layer, and the second oxide layer, wherein the via physically contacts the second interconnect structure; wherein the via includes a first via portion disposed in the third oxide layer and a second via portion disposed in the second oxide layer, wherein a first width of the first via portion is greater than a second width of the second via portion and a third width of the second interconnect structure is less than the second width”
Claim(s) 10, 13 of US Patent 11710657 do not disclose a multilayer interconnect (MLI) structure that includes routing layers and via layers, wherein a given routing layer of the routing layers and the top of the insulation layer is covered by the metal oxide layer.
Fan disclose a multilayer interconnect (MLI) structure (100) that includes routing layers and via layers[0002], wherein a given routing layer of the routing layers and the top of the insulation layer is covered by the metal oxide layer.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Fan to the teachings of US Patent 11710657 in order to minimize parasitic resistance [0013, Fan].
Re claim 22 US Patent 11710657 and Fan disclose the device structure of claim 21, wherein the given routing layer of the routing layers is a bottommost routing layer of the MLI structure(200 of Fan) and the given via layer of the via layers of the MLI structure(200 of Fan) is a bottommost via layer of the MLI structure.
Re claim 23 US Patent 11710657 and Fan disclose the device structure of claim 21, wherein the first one of the ruthenium- comprising interconnect structures [US Patent 11710657] is disposed between the via of the given via layer of the via layers of the MLI structure(200 of Fan) and a source/drain contact.
Re claim 24 US Patent 11710657 and Fan disclose the device structure of claim 21, wherein a third thickness of the metal oxide layer is less than the distance that the tops of the ruthenium-comprising interconnect structures [US Patent 11710657] are recessed below the top of the insulation layer.
Re claim 25 US Patent 11710657 and Fan disclose the device structure of claim 21, wherein the insulation layer includes a silicon oxide layer[0016 of Fan] disposed over an amorphous silicon layer.
Conclusion
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/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812