DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Terminal Disclaimer
The terminal disclaimer filed on 04/14/2026 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of 11710657 has been reviewed and is accepted. The terminal disclaimer has been recorded.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-15, 21-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bao(USPGPUB DOCUMENT: 2021/0305155, hereinafter Bao) in view of Bu (USPGPUB DOCUMENT: 2006/0030128, hereinafter Bu) and Fan (USPGPUB DOCUMENT: 2016/0379932, hereinafter Fan).
Re claim 1 Bao discloses in Fig 4 an interconnect structure comprising: and a local contact disposed in the insulator layer[0035], and the local contact includes:a metal-comprising layer(412)[0034] disposed directly on the source/drain contact[0027,0033],wherein the metal-comprising layer(412)[0034] has a first width,a ruthenium-comprising layer(422)[0034] disposed directly on the metal-comprising layer(412)[0034], wherein the ruthenium-comprising layer(422)[0034] has a second width, wherein the second width is about equal to the first width and a metal of the metal-comprising layer(412)[0034] is different than ruthenium(Co/W)[0034], andan air gap between the metal-comprising layer(412)[0034] and the insulator layer[0035] and between the ruthenium-comprising layer(422)[0034] and the insulator layer[0035].
Bao does not discloses a source/drain contact[0027,0033] disposed in an insulator layer[0035]; and a local contact disposed in the insulator layer[0035], wherein the local contact is disposed on the source/drain contact[0027,0033] andan air gap between the metal-comprising layer(412)[0034] and the insulator layer[0035] and between the ruthenium-comprising layer(422)[0034] and the insulator layer[0035].
Bu discloses an air gap(45) between the metal-comprising layer(44/22) and the insulator layer(40/30) and between the ruthenium-comprising layer(422)[0034] and the insulator layer[0035].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Bu to the teachings of Bao in order to minimize wiring capacitance [0002, Bu]. In doing so, an air gap(45 of Bu) between the metal-comprising layer(44/22 of Bu) and the insulator layer(40/30 of Bu) and between the ruthenium-comprising layer(422)[0034] and the insulator layer[0035].
Bao and Bu does not discloses a source/drain contact disposed in an insulator layer; and a local contact disposed in the insulator layer wherein the local contact is disposed on the source/drain contact
Fan discloses a source/drain contact(210) disposed in an insulator layer(212); and a local contact(218) disposed in the insulator layer wherein the local contact is disposed on the source/drain contact
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Fan to the teachings of Bao in order to minimize parasitic resistance [0013, Fan].
Re claim 2 Bao and Bu and Fan disclose the interconnect structure of claim 1, wherein the metal is titanium.
Re claim 3 Bao and Bu and Fan disclose the interconnect structure of claim 1, wherein: the insulator layer[0035] includes a first oxide layer, a second oxide layer, and an amorphous silicon layer between the first oxide layer and the second oxide layer; the source/drain contact[0027,0033] is disposed in the first oxide layer and the local contact is disposed in the second oxide layer and the amorphous silicon layer; the air gap is between the metal-comprising layer(412)[0034] and the amorphous silicon layer; and the air gap is between the ruthenium-comprising layer(422)[0034] and the second oxide layer.
Re claim 4 Bao and Bu and Fan disclose the interconnect structure of claim 3, wherein the air gap has a third width, the amorphous silicon layer has a thickness, and the third width is about equal to the thickness.
Re claim 5 Bao and Bu and Fan disclose the interconnect structure of claim 1, wherein: the insulator layer[0035] includes a first oxide layer, a second oxide layer, and an amorphous carbon layer between the first oxide layer and the second oxide layer; the source/drain contact[0027,0033] is disposed in the first oxide layer and the local contact is disposed in the second oxide layer and the amorphous carbon layer; the air gap is between the metal-comprising layer(412)[0034] and the amorphous carbon layer; and the air gap is between the ruthenium-comprising layer(422)[0034] and the second oxide layer.
Re claim 6 Bao and Bu and Fan disclose the interconnect structure of claim 5, wherein the air gap has a third width, the amorphous carbon layer has a thickness, and the third width is about equal to the thickness.
Re claim 7 Bao and Bu and Fan disclose the interconnect structure of claim 1, wherein: the insulator layer[0035] includes a first oxide layer, a second oxide layer, a third oxide layer, and a metal oxide layer(424/414/454)[0038] layer between the second oxide layer and the third oxide layer; the source/drain contact[0027,0033] is disposed in the first oxide layer and the local contact is disposed in the second oxide layer; and a thickness of the metal oxide layer(424/414/454)[0038] layer is less than a distance between a top surface of the second oxide layer and a top surface of the ruthenium layer.
Re claim 8 Bao and Bu and Fan disclose the interconnect structure of claim 1, wherein the metal-comprising layer(412)[0034] has a first thickness, the ruthenium-comprising layer(422)[0034] has a second thickness, and a ratio of the first thickness to the second thickness is about 1:2 to about 1:50.
Re claim 9 Bao and Bu and Fan disclose the interconnect structure of claim 8, wherein the first thickness is about 1 nm to about 5 nm, and the second thickness is about 10 nm to about 50 nm.
Re claim 10 Bao discloses in Fig 4 an interconnect structure comprising: a device-level contact layer(412); a local contact layer disposed directly on the device-level contact layer(412), wherein the local contact layer includes a ruthenium-comprising contact(422)[0034] disposed in a first dielectric layer(dielectric in 432/422/410)[0035][0035], the ruthenium-comprising contact(422)[0034] has a first thickness, wherein the metal oxide layer(424/414/454)[0038] layer is between the first dielectric layer(dielectric in 432/422/410)[0035][0035] and the second dielectric layer(dielectric in 432/422/410)[0035] and the metal oxide layer(424/414/454)[0038] layer is disposed on a top and sidewalls of the first dielectric layer(dielectric in 432/422/410)[0035][0035].
Bao does not discloses wherein air gaps are disposed between sidewalls of the ruthenium-comprising contact(422)[0034] and the first dielectric layer(dielectric in 432/422/410)[0035][0035], the ruthenium-comprising contact(422)[0034] has a first thickness, the first dielectric layer(dielectric in 432/422/410)[0035][0035] has a second thickness, and the first thickness is less than the first thickness; anda global contact layer disposed directly on the local contact layer, wherein the global contact layer includes a global contact disposed in a second dielectric layer(dielectric in 432/422/410)[0035] and a metal oxide layer(424/414/454)[0038] layer,
Bu discloses wherein air gaps(45 of Bu)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Bu to the teachings of Bao in order to minimize wiring capacitance [0002, Bu]. In doing so, wherein air gaps(45 of Bu) are disposed between sidewalls of the ruthenium-comprising contact(422)[0034] and the first dielectric layer(dielectric in 432/422/410)[0035][0035],
Bao and Bu does not discloses the ruthenium-comprising contact(422)[0034] has a first thickness, the first dielectric layer(dielectric in 432/422/410)[0035][0035] has a second thickness, and the first thickness is less than the first thickness;
anda global contact layer disposed directly on the local contact layer, wherein the global contact layer includes a global contact disposed in a second dielectric layer(dielectric in 432/422/410)[0035] and a metal oxide layer(424/414/454)[0038] layer,
Fan discloses a global contact layer(210/218) disposed directly on the local contact layer(210/218), wherein the global contact layer(210/218) includes a global contact disposed in a second dielectric layer(102a-102b)[0002]
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Fan to the teachings of Bao in order to minimize parasitic resistance [0013, Fan]. In doing so, wherein the global contact layer(210/218) includes a global contact disposed in a second dielectric layer(102a-102b)[0002] and a metal oxide layer(424/414/454 of Bao)[0038] layer,
Bao and Bu and Fan does not discloses the ruthenium-comprising contact(422)[0034] has a first thickness, the first dielectric layer(dielectric in 432/422/410)[0035][0035] has a second thickness, and the first thickness is less than the first thickness;
Although the combination of Bao and Bu and Fan does not discloses the ruthenium-comprising contact(422)[0034] has a first thickness, the first dielectric layer(dielectric in 432/422/410)[0035][0035] has a second thickness, and the first thickness is less than the first thickness, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to disclose he ruthenium-comprising contact(422)[0034] has a first thickness, the first dielectric layer(dielectric in 432/422/410)[0035][0035] has a second thickness, and the first thickness is less than the first thickness as the result effective variable meet the claims as varied through routine experimentation in order to optimize the functionality of the device and when the prior art discloses the general conditions of the claimed invention, discovering the optimum or workable ranges involves only ordinary skill in the art to optimize minimize parasitic resistance [0013, Fan]. See MPEP 2144.05.
Further, the specification contains no disclosure of either the critical nature of the claimed invention or any unexpected results arising therefrom. The law is replete with cases in which the difference between the claimed invention and the prior art is some range or other variable within the claims. In such a situation, the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In reWoodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990)
Regarding the limitation “a global contact layer disposed directly on the local contact layer ". The interpretation of "on" is being interpreted as used to indicate immediate proximity. This interpretation is being based from a general purpose dictionary (see www.Dictionary.com) is the evidence that's being relied upon to show that it's a reasonable interpretation.
Re claim 11 Bao and Bu and Fan disclose the interconnect structure of claim 10, wherein the device-level contact layer(412) includes a source/drain contact[0027,0033] disposed in a third dielectric layer(dielectric in 432/422/410)[0035], wherein the ruthenium-comprising contact(422)[0034] is disposed directly on the source/drain contact[0027,0033] and the first dielectric layer(dielectric in 432/422/410)[0035][0035] is disposed directly on the third dielectric layer(dielectric in 432/422/410)[0035].
Re claim 12 Bao and Bu and Fan disclose the interconnect structure of claim 10, wherein the device-level contact layer(412) includes a source/drain contact[0027,0033] disposed in a third dielectric layer(dielectric in 432/422/410)[0035] and the local contact layer further includes an amorphous material layer, wherein the ruthenium-comprising contact(422)[0034] is disposed directly on the source/drain contact[0027,0033], the amorphous material layer is between the first dielectric layer(dielectric in 432/422/410)[0035][0035] and the third dielectric layer(dielectric in 432/422/410)[0035], and the air gaps are disposed between the sidewalls of the ruthenium-comprising contact(422)[0034] and the amorphous material layer.
Re claim 13 Bao and Bu and Fan disclose the interconnect structure of claim 10, wherein the metal oxide layer(424/414/454)[0038] layer is a first metal oxide layer(424/414/454)[0038] layer, the device-level contact layer(412) includes a source/drain contact[0027,0033] disposed in a third dielectric layer(dielectric in 432/422/410)[0035], and the local contact layer further includes a second metal oxide layer(424/414/454)[0038] layer, wherein the ruthenium-comprising contact(422)[0034] is disposed directly on the source/drain contact[0027,0033], the second metal oxide layer(424/414/454)[0038] layer is between the first dielectric layer(dielectric in 432/422/410)[0035][0035] and the third dielectric layer(dielectric in 432/422/410)[0035], the air gaps are disposed between the sidewalls of the ruthenium-comprising contact(422)[0034] and the second metal oxide layer(424/414/454)[0038] layer, and the first metal oxide layer(424/414/454)[0038] layer includes a first metal that is different than a second metal of the second metal oxide layer(424/414/454)[0038] layer.
Re claim 14 Bao and Bu and Fan disclose the interconnect structure of claim 10, wherein the device-level contact layer(412) includes a source/drain contact[0027,0033] disposed in a third dielectric layer(dielectric in 432/422/410)[0035] and the local contact layer further includes a silicon-and-nitrogen-comprising layer, wherein the ruthenium- comprising contact is disposed directly on the source/drain contact[0027,0033], the silicon-and-nitrogen- comprising layer is between the first dielectric layer(dielectric in 432/422/410)[0035][0035] and the third dielectric layer(dielectric in 432/422/410)[0035], and the air gaps are disposed between the sidewalls of the ruthenium-comprising contact(422)[0034] and the silicon- and-nitrogen-comprising layer.
Re claim 15 Bao and Bu and Fan disclose the interconnect structure of claim 10, wherein the ruthenium- comprising contact includes a ruthenium plug disposed over a titanium-comprising layer, wherein the titanium-comprising layer is between the ruthenium plug and the device-level contact layer(412).
Re claim 21 Bao discloses in Fig 4 an device structure comprising: a multilayer interconnect (MLI) structure that includes routing layers and via layers(444), wherein a given routing layer of the routing layers includes:an insulation layer(dielectric in 432/422/410)[0035] and ruthenium- comprising interconnect structures(422)[0034] disposed in the insulation layer(dielectric in 432/422/410)[0035], andwherein, in a cross-sectional view, a first top of a first one of the ruthenium- comprising interconnect structures(422)[0034] is covered by a via of a given via layer of the via layers(444) of the MLI structure, a second top of a second one of the ruthenium- comprising interconnect structures(422)[0034] is covered by a metal oxide layer(424/414/454)[0038] layer,and the top of the insulation layer(dielectric in 432/422/410)[0035] is covered by the metal oxide layer(424/414/454)[0038] layer.
Bao does not discloses wherein sidewalls of the ruthenium- comprising interconnect structures(422)[0034] are separated from the insulation layer(dielectric in 432/422/410)[0035] by air gaps,wherein the insulation layer(dielectric in 432/422/410)[0035] has a first thickness, the ruthenium- comprising interconnect structures(422)[0034] have a second thickness, and the second thickness is less than the first thickness, such that tops of the ruthenium- comprising interconnect structures(422)[0034] are recessed a distance below a top of the insulation layer(dielectric in 432/422/410)[0035],
Bu discloses air gaps(45 of Bu) ;
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Bu to the teachings of Bao in order to minimize wiring capacitance [0002, Bu]. In doing so, wherein sidewalls of the ruthenium- comprising interconnect structures(422)[0034] are separated from the insulation layer(dielectric in 432/422/410)[0035] by air gaps(45 of Bu),
Bao and Bu does not discloses wherein the insulation layer(dielectric in 432/422/410)[0035] has a first thickness, the ruthenium- comprising interconnect structures(422)[0034] have a second thickness, and the second thickness is less than the first thickness, such that tops of the ruthenium- comprising interconnect structures(422)[0034] are recessed a distance below a top of the insulation layer(dielectric in 432/422/410)[0035],
Fan discloses such that tops of the ruthenium- comprising(422)[0034] interconnect structures(210 of Fan) are recessed a distance below a top of the insulation layer(dielectric in 432/422/410)[0035],
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Fan to the teachings of Bao in order to minimize parasitic resistance [0013, Fan]. In doing so, such that tops of the ruthenium- comprising(422)[0034] interconnect structures(210 of Fan) are recessed a distance below a top of the insulation layer(dielectric in 432/422/410)[0035],
Bao and Bu and Fan does not discloses wherein the insulation layer(dielectric in 432/422/410)[0035] has a first thickness, the ruthenium- comprising interconnect structures(422)[0034] have a second thickness, and the second thickness is less than the first thickness,
Although the combination of Bao and Bu and FAn does not discloses wherein the insulation layer(dielectric in 432/422/410)[0035] has a first thickness, the ruthenium- comprising interconnect structures(422)[0034] have a second thickness, and the second thickness is less than the first thickness, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to disclose wherein the insulation layer(dielectric in 432/422/410)[0035] has a first thickness, the ruthenium- comprising interconnect structures(422)[0034] have a second thickness, and the second thickness is less than the first thickness as the result effective variable meet the claims as varied through routine experimentation in order to optimize the functionality of the device and when the prior art discloses the general conditions of the claimed invention, discovering the optimum or workable ranges involves only ordinary skill in the art to optimize m minimize parasitic resistance [0013, Fan. See MPEP 2144.05.
Further, the specification contains no disclosure of either the critical nature of the claimed invention or any unexpected results arising therefrom. The law is replete with cases in which the difference between the claimed invention and the prior art is some range or other variable within the claims. In such a situation, the applicant must show that the particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In reWoodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990)
Re claim 22 Bao and Bu disclose the device structure of claim 21, wherein the given routing layer of the routing layers is a bottommost routing layer of the MLI structure and the given via layer of the via layers(444) of the MLI structure is a bottommost via layer of the MLI structure.
Re claim 23 Bao and Bu disclose the device structure of claim 21, wherein the first one of the ruthenium- comprising interconnect structures(422)[0034] is disposed between the via of the given via layer of the via layers(444) of the MLI structure and a source/drain contact[0027,0033].
Re claim 24 Bao and Bu disclose the device structure of claim 21, wherein a third thickness of the metal oxide layer(424/414/454)[0038] layer is less than the distance that the tops of the ruthenium- comprising interconnect structures(422)[0034] are recessed below the top of the insulation layer(dielectric in 432/422/410)[0035].
Re claim 25 Bao and Bu disclose the device structure of claim 21, wherein the insulation layer(dielectric in 432/422/410)[0035] includes a silicon oxide layer disposed over an amorphous silicon layer.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-15, 21-25 have been considered but are moot because the arguments do not apply to any of the references being used in the current rejection.
Conclusion
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/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
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