Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Cui et al. (US Pat. Pub. 2009/0309230).
Regarding claim 1, Cui teaches an integrated circuit device, comprising:
a metal interconnect over a substrate [fig. 1, 105, 110, 115, 120, 121, 123, 125 over substrate 101]; and
a cavity within the metal interconnect [fig. 9, 955];
wherein a first dielectric layer provides a roof for the cavity [fig. 10b, 1060];
a second dielectric layer provides a floor for the cavity [fig. 9, 105]; and
an oxide semiconductor provides a side edge for the cavity [fig. 10b, 1075, paragraph [0063] teaches 1075 is any materials taught for the IMD, ILD or cap, paragraph [0038] teaches the ILD is oxide].
Regarding claim 2, Cui discloses the integrated circuit device of claim 1, wherein the oxide semiconductor is a liner for a metal line or a metal via [fig. 10b, 1075 lines the sidewalls of the metal lines/vias].
Regarding claim 3, Cui teaches the integrated circuit device of claim 1, wherein the cavity has a height that is greater than a thickness of the first dielectric layer [fig. 10b, the height of the cavity is thicker than 1060].
Regarding claim 4, Cui discloses the integrated circuit device of claim 1, wherein the oxide semiconductor extends from the first dielectric to the second dielectric [fig. 10b, 1075 extends from 1060 to 105].
Claim(s) 13, 16, 18 and 19 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Oshida (US Pat. Pub. 2013/0207269).
Regarding claim 13, Oshida teaches an integrated circuit device, comprising:
a metal interconnect comprising a metallization layer over a substrate [fig. 1, metallization layers 240, 320, 440 over substrate 100];
a first metal line and a second metal line within the metallization layer, wherein a top height corresponds to a top of the first metal line and the second metal line, and a bottom height corresponds to a bottom of the first metal line and the second metal line [fig. 1, 240 with 320 above and adjacent 320 elements]; and
a cavity between the first metal line and the second metal line, wherein a first dielectric layer provides a ceiling for the cavity and a second dielectric layer provides a floor for the cavity, the floor is above the bottom height and the ceiling is below the top height, and the floor and the ceiling are flat [fig. 1, cavity 500, first dielectric 410 providing a ceiling, second dielectric 210 providing a floor, 240 extends below the floor while the ceiling is below the top height of 320, the floor and ceiling are flat].
Regarding claim 16, Oshida discloses the integrated circuit device of claim 13, wherein an oxide semiconductor provides a sidewall for the cavity [fig. 1, 310, paragraph [0036] teaches silicon oxide].
Regarding claim 18, Oshida teaches the integrated circuit device of claim 13, wherein the cavity reduces a capacitance of the BEOL transistor [paragraph [0043] teaches air gaps reduce inter-wiring capacitance].
Regarding claim 19, Oshida discloses the integrated circuit device of claim 13, wherein a third dielectric provides a sidewall for the cavity [fig. 1, 310].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Oshida as applied to claims 13, 16, 18 and 19 above, and further in view of Joi et al. (US Pat. Pub. 2018/0374747).
Regarding claim 17, Oshida teaches a liner on the first and second metal lines, however they fail to teach the liner is an oxide semiconductor.
Joi teaches an interconnect in a dielectric with a liner, the liner formed of semiconductor oxide [fig. 13c, paragraph [0101], zinc oxide liner].
It would have been obvious to one of ordinary skill in the art at the time of the invention to incorporate the teachings of Joi into the method of Oshida by forming the liner around the first and second metal layers out of zinc oxide (oxide semiconductor as taught in applicants instant specification, paragraph 0032) . The ordinary artisan would have been motivated to modify Oshida in the manner set forth above for at least the purpose of improving adhesion of the metal layer to the adjacent oxide layers [paragraph [0101].
Allowable Subject Matter
Claims 5-12 are allowed.
Claims 14, 15 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 5, the prior art fails to disclose or suggest the device as claimed. Specifically, the prior art fails to teach a layer of material that provides a gate dielectric for the transistor is directly over the first dielectric layer.
Conclusion
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/JOHN M PARKER/Examiner, Art Unit 2899