Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3 and 21 are is/are rejected under 35 U.S.C. 103 as being unpatentable over Cui et al. (US Pat. Pub. 2009/0309230) in view of Kim et al. (US Pat. Pub. 2019/0356293).
Regarding claim 1, Cui teaches an integrated circuit device, comprising:
a metal interconnect over a substrate [fig. 1, 105, 110, 115, 120, 121, 123, 125 over substrate 101]; and
a cavity within the metal interconnect [fig. 9, 955];
wherein a first dielectric layer provides a roof for the cavity [fig. 10b, 1060];
a second dielectric layer provides a floor for the cavity [fig. 9, 105]; and
an oxide provides a side edge for the cavity [fig. 10b, 1075, paragraph [0063] teaches 1075 is any materials taught for the IMD, ILD or cap, paragraph [0038] teaches the ILD is oxide].
Cui fails to teach the oxide 1075 is an oxide semiconductor instead teaching materials such as silicon nitride. However, Kim teaches a semiconductor device with metal contacts formed over a substrate and a cavity between said metal contacts, and a passivation layer formed between the metal contacts the passivation layer taught to be silicon nitride or alternatively a oxide semiconductor such as MgO, ZnO [fig. 1, metal contacts 195, cavity C, passivation 190, paragraph [0106] teaches SiN, MgO, ZnO among others, applicants own specification paragraph [0032] teaches oxide semiconductor is actually a metal oxide such as ZnO or MgO among others].
It would have been obvious to one of ordinary skill in the art at the time of the invention to incorporate the teachings of Kim into the method of Cui by forming the passivation layer from an oxide semiconductor such as ZnO or MgO. The ordinary artisan would have been motivated to modify Cui in the manner set forth above for at least the purpose of utilizing a known functional material to ensure successful device fabrication. Furthermore, as ZnO and MgO are known suitable alternatives to SiN as taught in Kim, this is motivation in itself as art recognized suitability for an intended purpose has been recognized to be motivation to combine. MPEP 2144.07.
Regarding claim 2, Cui in view of Kim discloses the integrated circuit device of claim 1, wherein the oxide semiconductor is a liner for a metal line or a metal via [fig. 10b, 1075 lines the sidewalls of the metal lines/vias].
Regarding claim 3, Cui in view of Kim teaches the integrated circuit device of claim 1, wherein the cavity has a height that is greater than a thickness of the first dielectric layer [fig. 10b, the height of the cavity is thicker than 1060].
Regarding claim 21, Cui in view of Kim discloses the integrated circuit device of claim 1, wherein the oxide semiconductor providing the side edge of the cavity has a thickness of at least 0.5nm [Cui, paragraph [0063] 5nm-20nm taught].
Allowable Subject Matter
Claims 5-19 are allowed.
Claim 22 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 5, the prior art fails to disclose or suggest the device as claimed. Specifically, the prior art fails to teach a layer of material that provides a gate dielectric for the transistor is directly over the first dielectric layer.
Regarding claim 13, the prior art fails to disclose or suggest the device as claimed. Specifically, the prior art fails to teach a cavity between the first metal line and the second metal line, wherein a first dielectric layer provides a ceiling for the cavity, a second dielectric layer provides a floor for the cavity, the first and second dielectric layers are discontinuous, the floor is above the bottom height and the ceiling is below the top height and the floor and the ceiling are flat.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot in view of the new grounds of rejection applied above.
Conclusion
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/JOHN M PARKER/Primary Examiner, Art Unit 2899
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