DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Arguments
Applicant’s arguments with respect to claims1, 9 and 16 (their dependent claims) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over Haratipour et al. (US PGpub: 2020/0312950 A1), herein after Haratipour, in view of other teaching from TANAKA et al. (US PGpub: 2014/0070289 A1), herein after TANAKA and in further view of other teaching from PARK et al. (US PGpub: 2021/0183992 A1 A1), herein after PARK.
Regarding claim 1, Haratipour teaches an integrated circuit (IC), comprising:
a substrate (201);
an electrode (207) disposed over the substrate (201);
a ferroelectric layer (211) vertically stacked with the electrode (207); and
a seed layer (209, FIG. 200B) comprising oxygen (Paragraph [0013]) and vertically stacked between the electrode and the ferroelectric layer, wherein the ferroelectric layer has a orthorhombic crystalline phase (Paragraph [0029], [0030], [0039]).
Haratipour does not explicitly teach wherein the ferroelectric layer has a substantially uniform orthorhombic crystalline phase, seed layer comprising a non-uniform oxygen distribution, wherein the seed layer has a higher concentration of oxygen proximate the electrode than proximate the ferroelectric layer.
However, TANAKA teaches the ferroelectric layer has a substantially uniform orthorhombic crystalline phase (Paragraphs [0176]-[0181]).
Hence, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use Haratipour’s integrated circuit with teaching from TANAKA so that it is possible to form at a high yield a ferroelectric memory including cells with improved cell characteristics, high capabilities and high integration density.
Haratipour or TANAKA does not explicitly teach seed layer comprising a non-uniform oxygen distribution, wherein the seed layer has a higher concentration of oxygen proximate the electrode than proximate the ferroelectric layer,
However, PARK teaches seed layer comprising a non-uniform oxygen distribution, wherein the seed layer has a higher concentration of oxygen proximate the electrode than proximate the ferroelectric layer (the seed layer 65 may have an oxygen concentration less than that of a ternary metal oxide having a chemical formula of ABO.sub.3 forming a perovskite structure. In an implementation, the seed layer 65 may include a material having an oxygen concentration less than that of the ternary metal oxide (ABO.sub.3) forming a perovskite structure. In an implementation, the seed layer 65 may include, e.g., (SrTiO.sub.3-x), (BaTiO.sub.3-x), or (CaTiO.sub.3-x), in which 0<x<3, x is a real number……. In an implementation, a concentration of oxygen at a portion of the seed layer 65 proximate to the lower electrode 55 may be less than a concentration of oxygen at a portion of the seed layer 65 distal to the lower electrode 55 paragraph [0031]-[0033])
Hence, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use Haratipour and TANAKA’s integrated circuit with teaching from PARK so that it is possible to improve device functionality
Regarding claim 2, Haratipour teaches the IC of claim 1, wherein the seed layer is configured to promote growth of orthorhombic phase crystals in the ferroelectric layer and inhibit growth of monoclinic phase crystals in the ferroelectric layer (Paragraph [0019], [0013], [0029], [0030]).
Regarding claim 3, Haratipour does not explicitly teach the IC of claim 1, further comprising: an inter-diffusion region (at the interface) between the seed layer (209) and the electrode (211), wherein the inter-diffusion region is configured to prevent a formation of charges at an interface of the seed layer and the electrode.
Claims 4-7 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Haratipour et al. (US PGpub: 2020/0312950 A1), herein after Haratipour, in view of other teaching from TANAKA , in view of PARK and in further view of other teaching from KANG et al. (US PGpub: 2020/0335333 A1), herein after KANG.
Regarding claim 4, Haratipour teaches (in view of KANG) the IC of claim 1, further comprising:
a pair of source/drain contacts (510/511) laterally separated and respectively on opposite sides of the semiconductor layer.
Haratipour or TANAKA or PARK does not explicitly teach a semiconductor layer (504, in KANG FIG. 20B) over the ferroelectric layer;.
However, KANG teaches a semiconductor layer (504, in KANG FIG. 20B) over the ferroelectric layer.
Hence, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use Haratipour, TANAKA and PARK’s’ s integrated circuit with teaching from KANG so that it is possible to increase the capacitance of the capacitor in order to meet device functionality.
Regarding claim 5, Haratipour teach the IC of claim 4, wherein the pair of source/drain contacts (510/511)are disposed on an opposite side of the semiconductor layer as the electrode.
Regarding claim 6, Haratipour teaches (in view of KANG) the IC of claim 4, wherein the pair of source/drain contacts (510/511 in KANG) are disposed on a same side of the semiconductor layer as the electrode.
Regarding claim 7, Haratipour teaches (in view of KANG and LEE) the IC of claim 1, further comprising: a semiconductor layer over the ferroelectric layer, wherein the semiconductor layer is amorphous Indium-Gallium-Zinc-Oxide (LEE in Paragraph [0104])).
Regarding claim 21, Haratipour teaches (in view of KANG) the IC of claim 4, wherein the semiconductor layer (504 in KANG ) continuously extends along a topmost surface of the ferroelectric layer.
Claims 9 and 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over Haratipour et al. (US PGpub: 2020/0312950 A1), herein after Haratipour, in view of other teaching from LEE; Jong-Ho (US PGpub: 2016/0056301 A1), herein after LEE and in further view of other teaching from SUZUKI et al (US PGpub: 20220302170 A1), herein after SUZUKI.
Regarding claim 9, Haratipour teaches an integrated circuit (IC), comprising:
a lower electrode (207) disposed over a substrate (201), wherein the lower electrode comprises a first conductive material;
a seed layer (209, FIG. 200B) arranged on the lower electrode, wherein the seed layer comprises oxygen and the first conductive material (Paragraph [0029], [0030], [0039]);
a ferroelectric layer (211) arranged on the seed layer;
source/drain contacts disposed on the semiconductor channel layer and laterally separated from one another (Paragraph [0047]).
Haratipour does not explicitly teach a semiconductor channel layer over the ferroelectric layer, wherein the ferroelectric layer comprises a plurality of crystalline phases, and wherein the ferroelectric layer has a predominant orthorhombic crystalline phase;
However, LEE teaches semiconductor channel layer over the ferroelectric layer (Paragraph [0128]).
Hence, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use Haratipour’s integrated circuit with teaching from LEE so that it is possible to conduct current between source and drain as known in the industry.
Haratipour or LEE does not explicitly teach, wherein the ferroelectric layer comprises a plurality of crystalline phases, and wherein the ferroelectric layer has a predominant orthorhombic crystalline phase.
However, SUZUKI teaches ferroelectric layer comprises a plurality of crystalline phases, and wherein the ferroelectric layer has a predominant orthorhombic crystalline phase (The second region 12b, which is a ferroelectric, contains a plurality of crystal grains. Each of the crystal grains serves as a polarization domain. The polarization state of each of the crystal grains depends on the crystal orientation and the electric field direction of each of the crystal grains. The electrostatic potential of the surface of the semiconductor layer 10 facing the second region 12b depends on the polarization state of each of the crystal grains….. A main constituent substance of the second region 12b is other than a crystal of an orthorhombic crystal system and a trigonal crystal system. Having a crystal other than the crystal of the orthorhombic crystal system and the trigonal crystal system as a main constituent substance means that a substance other than a crystal of the orthorhombic crystal system or the trigonal crystal system exhibits the highest abundance ratio among the substances constituting the second region 12b.);
Hence, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use Haratipour and LEE’s integrated circuit with teaching from SUZUKI so that it is possible that threshold voltage of the transistor is modulated by changing the polarization state of the ferroelectric layer.
Regarding claim 11, Haratipour teaches the IC of claim 9, wherein the seed layer has a predominantly crystalline phase (Paragraph [0029], [0030], [0039]).
Regarding claim 12, Haratipour teaches the IC of claim 9, wherein the seed layer (209, FIG. 200B) completely covers an upper surface of the lower electrode (207) and a lower surface of the ferroelectric layer (211).
Regarding claim 14, Haratipour (in view of KANG) teaches the IC of claim 9, wherein the lower electrode and the seed layer comprise tantalum (Kang in Paragraph [0044], [0054]).
Regarding claim 22, Haratipour teaches the IC of claim 9, wherein a thickness of the seed layer (209) is less than a thickness of the ferroelectric layer (211, FIG. 2).
Claim 15 are rejected under 35 U.S.C. 103 as being unpatentable over Haratipour, in view of other teaching from LEE and in further view of other teaching from Choi et al. (US PGpub: 2004/0102015 A1), herein after Choi.
Regarding claim 15, neither Haratipour nor LEE nor SUZUKI explicitly teach the IC of claim 9, wherein the seed layer comprises a thermal tantalum oxide .
However, Choi teaches the seed layer comprises a thermal tantalum oxide (Paragraphs [0052]-[0053], [0065]).
Hence, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use Haratipour and LEE (SUZUKI) ’s modified integrated circuit with teaching from Choi so that it is possible to relieve interface stresses between the upper electrode and the tantalum oxide layer.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Haratipour, in view of other teaching from LEE, in view of SUZUKI and in further view of other teaching from KANG et al. (US PGpub: 2020/0335333 A1), herein after KANG.
Regarding claim 10, Haratipour teaches the IC of claim 9, wherein the lower electrode is tantalum nitride (paragraph [0023]), the seed layer is tantalum oxide (KANG in Paragraph [0044], [0054]), the ferroelectric layer is hafnium zirconium oxide (Paragraph [0023]), and the semiconductor channel layer is Indium-Gallium-Zinc-Oxide (LEE in Paragraph [0104]).
Claims 16, 18-20 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Haratipour et al. (US PGpub: 2020/0312950 A1), herein after Haratipour, in view of other teaching from TANAKA et al. (US PGpub: 2014/0070289 A1), herein after TANAKA.
Regarding claim 16, Haratipour teaches an integrated circuit (IC), comprising:
an electrode (207) disposed over a substrate (201);
a seed structure (209, FIG. 200B) continuously extending along a topmost surface of the electrode;
a ferroelectric structure (211) disposed on the seed structure, wherein the seed structure is configured to promote growth of orthorhombic phase crystals in the ferroelectric structure (the ferroelectric layer 211 is a stronger ferroelectric than is provided in oxide layers (see ferroelectric high-k layer 109 in FIG. 1) utilized in previous approaches due to its controlled polar phase growth during the deposition. Paragraph [0029], [0030], [0039])) and
wherein the ferroelectric structure has a orthorhombic crystal phase (Paragraph [0029], [0030], [0039]); and
an upper conductor (215) disposed over the ferroelectric structure, wherein the ferroelectric structure continuously extends along a bottommost surface of the upper conductor.
Haratipour does not explicitly teach wherein the ferroelectric layer has a substantially uniform orthorhombic crystalline phase.
However, TANAKA teaches the ferroelectric layer has a predominately orthorhombic crystal phase (Paragraphs [0176]-[0181]).
Hence, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use Haratipour’s integrated circuit with teaching from TANAKA so that it is possible to form at a high yield a ferroelectric memory including cells with improved cell characteristics, high capabilities and high integration density.
Regarding claim 18, Haratipour (in view of KANG) teaches the IC of claim 16, wherein the electrode comprises tantalum nitride and the seed structure comprises tantalum oxide (KANG in Paragraph [0044], [0054]).
Regarding claim 19, Haratipour teaches (in view of KANG) the IC of claim 16, further comprising:
semiconductor layer (504, in KANG FIG. 20B) arranged over the substrate (502) ;
an insulating layer (507, FIG. 20C)) arranged over the semiconductor layer, wherein the electrode is separated from the semiconductor layer by the insulating layer; and
source/drain contacts (510/511) disposed on doped regions within the semiconductor layer and laterally separated from opposing sides of the electrode by an inter-level dielectric structure (506).
Regarding claim 20, Haratipour teaches (in view of KANG)the IC of claim 19, wherein the source/drain contacts vertically extend from the doped regions to an upper surface of the upper conductor(513 and 521, in KANG FIG. 20B).
Regarding claim 23, Haratipour teaches the IC of claim 16, wherein a spacer structure (In some implementations of the invention, a pair of sidewall spacers may be formed on opposing sides of the gate stack that bracket the gate stack. The sidewall spacers may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, or silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.)laterally encloses the electrode, the seed structure, the ferroelectric structure, and the upper conductor.
Conclusion
Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHEIKH MARUF whose telephone number is (571)270-1903. The examiner can normally be reached M-F, 8am-6pm EDT.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at 571-270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SHEIKH MARUF/Primary Examiner, Art Unit 2897
Prosecution Insights