DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 are rejected under 35 U.S.C. 103 as being unpatentable over Haratipour et al. (US PGpub: 2020/0312950 A1), herein after Haratipour, in view of other teaching from TANAKA et al. (US PGpub: 2014/0070289 A1), herein after TANAKA.
Regarding claim 1, Haratipour teaches an integrated circuit (IC), comprising:
a substrate (201);
an electrode (207) disposed over the substrate (201);
a ferroelectric layer (211) vertically stacked with the electrode (207); and
a seed layer (209, FIG. 200B) comprising oxygen (Paragraph [0013]) and vertically stacked between the electrode and the ferroelectric layer, wherein the ferroelectric layer has a orthorhombic crystalline phase (Paragraph [0029], [0030], [0039]).
Haratipour does not explicitly teach wherein the ferroelectric layer has a substantially uniform orthorhombic crystalline phase.
However, TANAKA teaches the ferroelectric layer has a substantially uniform orthorhombic crystalline phase (Paragraphs [0176]-[0181]).
Hence, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use Haratipour’s integrated circuit with teaching from TANAKA so that it is possible to form at a high yield a ferroelectric memory including cells with improved cell characteristics, high capabilities and high integration density.
Regarding claim 2, Haratipour teaches the IC of claim 1, wherein the seed layer is configured to promote growth of orthorhombic phase crystals in the ferroelectric layer and inhibit growth of monoclinic phase crystals in the ferroelectric layer (Paragraph [0019], [0013], [0029], [0030]).
Regarding claim 3, Haratipour does not explicitly teach the IC of claim 1, further comprising: an inter-diffusion region (at the interface) between the seed layer (209) and the electrode (211), wherein the inter-diffusion region is configured to prevent a formation of charges at an interface of the seed layer and the electrode.
Claims 4-8 are rejected under 35 U.S.C. 103 as being unpatentable over Haratipour et al. (US PGpub: 2020/0312950 A1), herein after Haratipour, in view of other teaching from TANAKA et al. (US PGpub: 2014/0070289 A1), herein after TANAKA and in further view of other teaching from KANG et al. (US PGpub: 2020/0335333 A1), herein after KANG.
Regarding claim 4, Haratipour teaches (in view of KANG) the IC of claim 1, further comprising:
a pair of source/drain contacts (510/511) laterally separated and respectively on opposite sides of the semiconductor layer.
Haratipour or TANAK does not explicitly teach a semiconductor layer (504, in KANG FIG. 20B) over the ferroelectric layer;.
However, KANG teaches a semiconductor layer (504, in KANG FIG. 20B) over the ferroelectric layer.
Hence, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use Haratipour and TANAKA’s integrated circuit with teaching from KANG so that it is possible to increase the capacitance of the capacitor in order to meet device functionality.
Regarding claim 5, Haratipour teach the IC of claim 4, wherein the pair of source/drain contacts (510/511)are disposed on an opposite side of the semiconductor layer as the electrode.
Regarding claim 6, Haratipour teaches (in view of KANG) the IC of claim 4, wherein the pair of source/drain contacts (510/511 in KANG) are disposed on a same side of the semiconductor layer as the electrode.
Regarding claim 7, Haratipour teaches (in view of KANG and LEE) the IC of claim 1, further comprising: a semiconductor layer over the ferroelectric layer, wherein the semiconductor layer is amorphous Indium-Gallium-Zinc-Oxide (LEE in Paragraph [0104])).
Regarding claim 8, Haratipour teaches the IC of claim 1, wherein the seed layer is tantalum oxide (KANG in Paragraph [0044], [0054]) and the ferroelectric layer is hafnium zirconium oxide (paragraph [0023]).
Claims 9 and 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over Haratipour et al. (US PGpub: 2020/0312950 A1), herein after Haratipour, in view of other teaching from LEE; Jong-Ho (US PGpub: 2016/0056301 A1), herein after LEE.
Regarding claim 9, Haratipour teaches an integrated circuit (IC), comprising:
a lower electrode (207) disposed over a substrate (201), wherein the lower electrode comprises a first conductive material;
a seed layer (209, FIG. 200B) arranged on the lower electrode, wherein the seed layer comprises oxygen and the first conductive material (Paragraph [0029], [0030], [0039]);
a ferroelectric layer (211) arranged on the seed layer;
source/drain contacts disposed on the semiconductor channel layer and laterally separated from one another (Paragraph [0047]).
Haratipour does not explicitly teach a semiconductor channel layer over the ferroelectric layer.
However, LEE teaches semiconductor channel layer over the ferroelectric layer (Paragraph [0128]).
Hence, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use Haratipour’s integrated circuit with teaching from LEE so that it is possible to conduct current between source and drain as known in the industry.
Regarding claim 11, Haratipour teaches the IC of claim 9, wherein the seed layer has a predominantly crystalline phase (Paragraph [0029], [0030], [0039]).
Regarding claim 12, Haratipour teaches the IC of claim 9, wherein the seed layer (209, FIG. 200B) completely covers an upper surface of the lower electrode (207) and a lower surface of the ferroelectric layer (211).
Regarding claim 13, Haratipour teaches the IC of claim 9, wherein the seed layer (209, FIG. 200B) continuously extends from a bottom surface physically contacting the lower electrode to a top surface physically contacting the ferroelectric layer (FIG. 200B).
Regarding claim 14, Haratipour (in view of KANG) teaches the IC of claim 9, wherein the lower electrode and the seed layer comprise tantalum (Kang in Paragraph [0044], [0054]).
Claim 15 are rejected under 35 U.S.C. 103 as being unpatentable over Haratipour, in view of other teaching from TANAKA and in further view of other teaching from Choi et al. (US PGpub: 2004/0102015 A1), herein after Choi.
Regarding claim 15, neither Haratipour nor TANAKA explicitly teach the IC of claim 9, wherein the seed layer comprises a thermal tantalum oxide .
However, Choi teaches the seed layer comprises a thermal tantalum oxide (Paragraphs [0052]-[0053], [0065]).
Hence, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use Haratipour and TANAKA’s modified integrated circuit with teaching from Choi so that it is possible to relieve interface stresses between the upper electrode and the tantalum oxide layer.
Claim10 is rejected under 35 U.S.C. 103 as being unpatentable over Haratipour, in view of other teaching from LEE and in further view of other teaching from KANG et al. (US PGpub: 2020/0335333 A1), herein after KANG.
Regarding claim 10, Haratipour teaches the IC of claim 9, wherein the lower electrode is tantalum nitride (paragraph [0023]), the seed layer is tantalum oxide (KANG in Paragraph [0044], [0054]), the ferroelectric layer is hafnium zirconium oxide (Paragraph [0023]), and the semiconductor channel layer is Indium-Gallium-Zinc-Oxide (LEE in Paragraph [0104]).
Claims 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Haratipour et al. (US PGpub: 2020/0312950 A1), herein after Haratipour, in view of other teaching from TANAKA et al. (US PGpub: 2014/0070289 A1), herein after TANAKA.
Regarding claim 16, Haratipour teaches an integrated circuit (IC), comprising:
an electrode (207) disposed over a substrate (201);
a seed structure (209, FIG. 200B) disposed on the electrode;
a ferroelectric structure (211) disposed on the seed structure, wherein the seed structure is configured to promote growth of orthorhombic phase crystals in the ferroelectric structure (the ferroelectric layer 211 is a stronger ferroelectric than is provided in oxide layers (see ferroelectric high-k layer 109 in FIG. 1) utilized in previous approaches due to its controlled polar phase growth during the deposition. Paragraph [0029], [0030], [0039])) and
wherein the ferroelectric structure has a orthorhombic crystal phase (Paragraph [0029], [0030], [0039]); and
an upper conductor (215) disposed over the ferroelectric structure.
Haratipour does not explicitly teach wherein the ferroelectric layer has a substantially uniform orthorhombic crystalline phase.
However, TANAKA teaches the ferroelectric layer has a predominately orthorhombic crystal phase (Paragraphs [0176]-[0181]).
Hence, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use Haratipour’s integrated circuit with teaching from TANAKA so that it is possible to form at a high yield a ferroelectric memory including cells with improved cell characteristics, high capabilities and high integration density.
Claim17 is rejected under 35 U.S.C. 103 as being unpatentable over Haratipour, in view of other teaching from TANAKA and in further view of other teaching from KANG et al. (US PGpub: 2020/0335333 A1), herein after KANG.
Regarding claim 17, Haratipour (in view of KANG) teaches the IC of claim 16, wherein the electrode and the seed structure comprise a same conductive material (KANG in Paragraph [0044], [0054]).
Regarding claim 18, Haratipour (in view of KANG) teaches the IC of claim 16, wherein the electrode comprises tantalum nitride and the seed structure comprises tantalum oxide (KANG in Paragraph [0044], [0054]).
Regarding claim 19, Haratipour teaches (in view of KANG) the IC of claim 16, further comprising:
semiconductor layer (504, in KANG FIG. 20B) arranged over the substrate (502) ;
an insulating layer (507, FIG. 20C)) arranged over the semiconductor layer, wherein the electrode is separated from the semiconductor layer by the insulating layer; and
source/drain contacts (510/511) disposed on doped regions within the semiconductor layer and laterally separated from opposing sides of the electrode by an inter-level dielectric structure (506).
Regarding claim 20, Haratipour teaches (in view of KANG)the IC of claim 19, wherein the source/drain contacts vertically extend from the doped regions to an upper surface of the upper conductor(513 and 521, in KANG FIG. 20B).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See form PTO-892.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHEIKH MARUF whose telephone number is (571)270-1903. The examiner can normally be reached on M-F, 8am-6pm EDT.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on 571-270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHEIKH MARUF/Primary Examiner, Art Unit 2897