Prosecution Insights
Last updated: August 17, 2026
Application No. 18/357,361

Semiconductor Device and Method of Integrating eWLB with E-bar Structures and RF Antenna Interposer

Non-Final OA §103
Filed
Jul 24, 2023
Examiner
CHOUDHRY, MOHAMMAD M
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Stats Chippac Pte. Ltd.
OA Round
3 (Non-Final)
82%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
576 granted / 703 resolved
+13.9% vs TC avg
Moderate +12% lift
Without
With
+11.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
31 currently pending
Career history
737
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
75.6%
+35.6% vs TC avg
§102
10.9%
-29.1% vs TC avg
§112
4.1%
-35.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 703 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/29/2026 has been entered. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. Claims 1, and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Yang et al. (US 2020/0013738, hereinafter Yang) in view of Hashemi et al. (US 2018/0019216, hereinafter Hashemi). With respect to claim 1, Yang discloses a semiconductor device (Fig. 4e), comprising: an e-bar substrate (components 170/132/180 are part of the substrate) including a continuous core layer (180) and a plurality of e-bar structures (132) formed through the core layer (fig. 4e); an electrical component (104) disposed within an opening of the e-bar structures substrate (Fig. 4e), wherein the e-bar structures extend around the electrical component (Fig. 4e); a SIP disposed in direct contact with the e-bar structures (Para 0034; 0040-0041). Yang does not explicitly disclose that the SIP comprises of an antenna interposer. In an analogous art, Hashemi discloses that the SIP comprises of an antenna interposer (Para 0003). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Yang’s device by having Hashemi’s disclosure in order to route electrical signals efficiently in a semiconductor device. With respect to claim 4, Yang/Hashemi discloses the semiconductor device of claim 1. Yang further discloses including an encapsulant (192 of Fig. 4g) deposited over the electrical component (192 is deposited over 104). Claims 2-3 and 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Yang/Hashemi in view of Lee (KR 20200012440, hereinafter Lee). With respect to claim 2, Yang/Hashemi discloses the semiconductor device of claim 1. Yang/Hashemi does not explicitly disclose a redistribution layer formed over a second surface of the e-bar substrate opposite the antenna interposer first surface of the substrate. In an analogous art, Lee discloses: PNG media_image1.png 320 688 media_image1.png Greyscale a redistribution layer (290 & 255 of fig. 500B) formed over a second surface of the e-bar substrate opposite the antenna interposer first surface of the substrate (290 & 255 are opposite the antenna interposer first surface of the substrate). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Yang/Hashemi’s device by having Lee’s disclosure in order to route electrical signals efficiently in a semiconductor device. With respect to claim 3, Yang/Hashemi/Lee discloses the semiconductor device of claim 2. Yang further discloses wherein the redistribution layer includes: a conductive layer (172); and an insulating layer (174) formed over the conductive layer (Fig. 4e). With respect to claim 5, Yang/Hashemi discloses the semiconductor device of claim 1. Yang does/Hashemi not explicitly disclose wherein the antenna interposer includes: a first conductive layer; an insulating layer formed over the first conductive layer; and a second conductive layer formed over the insulating layer. In an analogous art, Lee discloses wherein the antenna interposer includes: a first conductive layer (lower subset of layers 112 of Fig. 500B); an insulating layer (111) formed over the first conductive layer (layer 111 is formed over the lower subset of layers 112); and a second conductive layer (upper subset of layers 112) formed over the insulating layer (upper subset of layers 112 is formed over 111). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Yang/Hashemi’s device by having Lee’s disclosure in order to route electrical signals efficiently in a semiconductor device. With respect to claim 6, Yang/Hashemi/Lee discloses the semiconductor device of claim 5. Yang/Hashemi does not explicitly disclose wherein the second conductive layer operates as an antenna. In an analogous art, Lee discloses wherein the second conductive layer operates as an antenna (Page 24; para 01 and Page 30; para 01). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Yang/Hashemi’s device by having Lee’s disclosure in order to route electrical signals efficiently in a semiconductor device. Claims 7-12 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Yang in view of Lee. With respect to claim 7, Yang discloses a semiconductor device (Fig. 4e), comprising: an electrical component (104); an e-bar substrate (components 170/132/180 are part of the substrate) including an opening to contain the electrical component (opening to have 104) and a plurality of e-bar structures (132) disposed around adjacent to the electrical component (Fig. 4e). Yang does not explicitly disclose an antenna interposer disposed in contact with the e-bar structures. In an analogous art, Lee discloses: PNG media_image1.png 320 688 media_image1.png Greyscale an antenna interposer (100 of Fig. 500B) disposed in contact with the e-bar structures (100 is in contact with e-bar structures via other layers). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Yang’s device by having Lee’s disclosure in order to route electrical signals efficiently in a semiconductor device. With respect to claim 8, Yang/Lee discloses the semiconductor device of claim 7. Yang does not explicitly disclose including a redistribution layer formed over a surface of the e-bar substrate opposite the antenna interposer. In an analogous art, Lee discloses a redistribution layer (290 & 255) formed over a surface of the e-bar structures opposite the antenna interposer (290 & 255 is formed on the backside). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Yang’s device by having Lee’s disclosure in order to route electrical signals efficiently in a semiconductor device. With respect to claim 9, Yang/Lee discloses the semiconductor device of claim 8. Yang further discloses wherein the redistribution layer includes: a conductive layer (172); and an insulating layer (174) formed over the conductive layer (Fig. 4e). With respect to claim 10, Yang/Lee discloses the semiconductor device of claim 7. Yang further discloses including an encapsulant (192 of Fig. 4g) deposited over the electrical component (192 is deposited over 104). With respect to claim 11, Yang/Lee discloses the semiconductor device of claim 7. Yang does not explicitly disclose wherein the antenna interposer includes: a first conductive layer; an insulating layer formed over the first conductive layer; and a second conductive layer formed over the insulating layer. In an analogous art, Lee discloses wherein the antenna interposer includes: a first conductive layer (lower subset of layers 112); an insulating layer (111) formed over the first conductive layer (layer 111 is formed over the lower subset of layers 112); and a second conductive layer (upper subset of layers 112) formed over the insulating layer (upper subset of layers 112 is formed over 111). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Yang’s device by having Lee’s disclosure in order to route electrical signals efficiently in a semiconductor device. With respect to claim 12, Yang/Lee discloses the semiconductor device of claim 11. Yang does not explicitly disclose wherein the second conductive layer is arranged as a plurality of islands. In an analogous art, Lee discloses that the semiconductor device wherein the second conductive layer is arranged as a plurality of islands (Fig. 9; top part of 112 is arranged in a plurality of islands). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Yang’s device by having Lee’s disclosure in order to route electrical signals efficiently in a semiconductor device. With respect to claim 26, Yang/Lee discloses the semiconductor device of claim 7. Yang further discloses wherein the e- bar substrate includes a continuous core layer (180 of Fig. 4e) with the plurality of e-bar structures (132) formed through the core layer (fig. 4e). Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Yang/Lee in view of Pavate et al. (US 2010/0127084, hereinafter Pavate). With respect to claim 13, Yang/Lee discloses the semiconductor device of claim 11. Yang/Lee does not explicitly disclose wherein the second conductive layer is arranged in a serpentine pattern. In an analogous art, Pavate discloses wherein the second conductive layer is arranged in a serpentine pattern (Para 0060; 452/456 of Figs 4C-4D). Therefore, it would have been obvious to one of an ordinary skilled in the art before the effective filing date of the claimed invention to modify Yang/Lee’s device by having Pavate’s disclosure in order to create an antenna of low profile, light weight with easy construction. Response to Arguments Based on new ground of rejection, applicant’s arguments regarding amended claims submitted on 06/29/2026 are moot. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M CHOUDHRY whose telephone number is (571)270-5716. The examiner can normally be reached Monday - Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fairbanks Brent can be reached at 408-918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MOHAMMAD M CHOUDHRY/Primary Examiner, Art Unit 2899
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Prosecution Timeline

Jul 24, 2023
Application Filed
Dec 02, 2025
Non-Final Rejection mailed — §103
Jan 19, 2026
Response Filed
May 27, 2026
Final Rejection mailed — §103
Jun 29, 2026
Request for Continued Examination
Jul 01, 2026
Response after Non-Final Action
Jul 15, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
82%
Grant Probability
94%
With Interview (+11.9%)
2y 9m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 703 resolved cases by this examiner. Grant probability derived from career allowance rate.

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