Attorney’s Docket Number: 123329-11615
Filing Date: 07/24/2023
Claimed Priority Date: 06/15/2020 (CON of 16/901,680 now PAT 11,749,753)
Applicants: Lin et al.
Examiner: Younes Boulghassoul
DETAILED ACTION
This Office action responds to the application filed on 07/24/2023.
Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . The application serial no. 18/357,797 filed on 07/24/2023 has been entered. Pending in this Office Action are claims 1-20.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 17 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US2019/0165114).
Regarding Claim 17, Lee (see, e.g., Figs. 1-2 and 4-10 and Par. [0037]-[0054]) shows all aspects of the instant invention, including a method of forming a semiconductor device, comprising:
- forming a pair of source/drain regions (e.g., source/drain regions SD) separated by a channel region in a semiconductor fin (e.g., top portion of fin-shaped active pattern ACT), forming a gate trench (e.g., gap 180) over the channel region and surrounded by gate spacers (e.g., gate spacer GSP) (see, e.g., Figs. 4-6 and Par. [0042]: sacrificial gate pattern 160 is removed, resulting in the forming of gap 180 between gate spacers GSP)
- forming a gate structure (e.g., gate dielectric pattern GI and a gate electrode GE) within a lower portion of the gate trench (see, e.g., Fig. 6 and Par. [0043])
- depositing a first dielectric layer (e.g., lower capping layer 182) over the gate structure in an upper portion of the gate trench, wherein sidewalls of the first dielectric layer are vertically connected with sidewalls of the gate structure (see, e.g., Fig. 7 and Par. [0044])
- forming a sacrificial layer (e.g., mask pattern 185) over the first dielectric layer to fill the gate trench (see, e.g., Fig. 7 and Par. [0045]: 185 is formed by initially filling the reminder of 180)
- removing a portion of the sacrificial layer (e.g., 185) to expose the first dielectric layer (e.g., 182) (see, e.g., Fig. 7 and Par. [0046]: 185 is etched until it reaches a desired thickness)
- removing the exposed first dielectric layer such that a remaining portion of the first dielectric layer (e.g., 182/110) is coplanar with a remaining portion of the sacrificial layer (see, e.g., Fig. 8 and Par. [0046]: portions of 182 not covered with 185 are etched to define a remaining 110)
- removing the remaining portion of the sacrificial layer (e.g., 185) to expose the remaining portion of the first dielectric layer (e.g., 182/110) (see, e.g., Fig. 9)
- depositing a second dielectric layer (e.g., upper capping layer 187) over the remaining portion of the first dielectric layer (see, e.g., Fig. 9)
- planarizing the second dielectric layer (e.g., 187) to shorten the gate spacers (e.g., GSP) (see, e.g., Fig. 10).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3, 5-6, 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US2019/0165114) in view of Chu et al. (US2020/0335602).
Regarding Claim 1, Lee (see, e.g., Figs. 1-2 and 4-10 and Par. [0037]-[0054]) shows most aspects of the instant invention, including a method of forming a semiconductor device, comprising:
- forming a gate trench (e.g., gap 180) over a semiconductor fin (e.g., fin-shaped active pattern ACT), the gate trench being lined with gate spacers (e.g., gate spacer GSP) (see, e.g., Figs. 4-6 and Par. [0042]: sacrificial gate pattern 160 is removed, resulting in the forming of gap 180 between gate spacers GSP)
- forming a gate structure (e.g., gate dielectric pattern GI and a gate electrode GE) within a lower portion of the gate trench to expose the gate spacers in an upper portion of the gate trench (see, e.g., Fig. 6 and Par. [0043])
- depositing a blanket dielectric layer (e.g., lower capping layer 182) in the upper portion of the gate trench (see, e.g., Fig. 7 and Par. [0044])
- depositing a mask layer (e.g., mask pattern 185) over the blanket dielectric layer to completely fill the upper portion of the gate trench (see, e.g., Fig. 7 and Par. [0045]: 185 is formed by initially filling the reminder of 180)
- etching the mask layer (e.g., 185) to partially expose the blanket dielectric layer (e.g., 182) in the gate trench (see, e.g., Fig. 7 and Par. [0046]: 185 is etched until it reaches a desired thickness)
- removing the exposed blanket dielectric layer (e.g., 182) to partially expose the gate spacers (e.g., GSP) (see, e.g., Fig. 8 and Par. [0046]: portions of 182 not covered with 185 are etched to define a remaining 110)
- removing a remaining portion of the mask layer (e.g., 185) to expose the blanket dielectric layer (e.g., 182/110), wherein the gate spacers vertically extend above the blanket dielectric layer (see, e.g., Fig. 9)
However, while Lee (see, e.g., Par. [0045]) discloses that mask pattern 185 may include a spin-on-hardmask (SOH) material (e.g., a carbon-containing layer), he does not explicitly disclose that said mask pattern 185 is a polymer layer. Chu (see, e.g., Figs. 6A-B to 10A-B, and Par. [0030],[0032]), on the other hand and in the same field of endeavor, teaches steps of etching-back conformal layers formed inside a gate opening 265 using sacrificial planarization layers 279, wherein the planarization layers can be organic planarization layers, e.g., an amorphous carbon layer, an amorphous silicon layer, a polymer layer or any other suitable planarization layer.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have a step of depositing a polymer layer in the method of Lee, because polymer material is a known suitable material for implementing sacrificial planarization layers to etch-back conformal layers formed inside a gate opening, as suggested by Chu, and selecting a known material based on its suitability for its intended use would have been obvious to the skilled artisan. See, Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945).
Regarding Claim 2, Lee (see, e.g., Figs. 6-7 and Par. [0026]) shows, wherein forming the gate structure includes forming a metal gate (e.g., metal gate electrode GE) over a gate dielectric layer (e.g., gate dielectric pattern GI), and wherein sidewalls of the blanket dielectric layer (e.g., 182) extend vertically from sidewalls of the gate dielectric layer.
Regarding Claim 3, Lee (see, e.g., Fig. 7) shows that the blanket dielectric layer (e.g., 182) directly contacts top surfaces of the metal gate and the gate dielectric layer.
Regarding Claim 5, Lee (see, e.g., Fig. 8 and Par. [0046]) shows that portions of lower capping layer 182, which is not covered with mask pattern 185, may be removed to form a lower capping pattern 110. Additionally, Chu (see, e.g., Par. [0030], [0032]) teaches that layers on the sidewalls of gate opening 265 and exposed from planarization layers 279 can be selectively removed using an isotropic etch process. Therefore, Lee in view of Chu teaches that removing the exposed blanket dielectric layer includes performing an isotropic etching process.
Regarding Claim 6, Lee (see, e.g., Fig. 9 and Par. [0047]) shows that mask pattern 185 may be removed by performing an ashing process. Additionally, Chu (see, e.g., Figs. 6A-B to 10A-B, and Par. [0030],[0032]) teaches that sacrificial planarization layers 279 can be a polymer layer. Therefore, Lee in view of Chu teaches that etching the polymer layer includes performing an ashing process.
Regarding Claim 8, Lee (see, e.g., Fig. 7 and Par. [0044]) shows that the blanket dielectric layer (e.g., 182/110) includes at least one material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride.
Regarding Claim 9, Lee (see, e.g., Fig. 8 and Par. [0046]) shows that removing the exposed blanket dielectric layer (e.g., 182/110) results in a top surface of the blanket dielectric layer to be coplanar with a top surface of the etched mask layer (e.g., mask pattern 185). Additionally, Chu (see, e.g., Figs. 6A-B to 10A-B, and Par. [0030],[0032]) teaches that sacrificial planarization layers 279 can be a polymer layer. Therefore, Lee in view of Chu teaches that removing the exposed blanket dielectric layer results in a top surface of the blanket dielectric layer to be coplanar with a top surface of the etched polymer layer.
Claims 4 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US2019/0165114) in view of Chu et al. (US2020/0335602), and in further view of Wu et al. (US2020/0105931).
Regarding Claim 4, Lee (see, e.g., Fig. 6 and Par. [0026]) shows that the gate dielectric layer (e.g., GI) includes a high-k dielectric material. However, Lee discloses that lower capping layer 182/110 may include, e.g., silicon nitride. Therefore, Lee in view of Chu is silent about the blanket dielectric layer including the same high-k dielectric material as the gate dielectric layer. Wu (see, e.g., Fig. 5 and Par. [0049]), on the other hand and in the same field of endeavor, teaches that silicon nitride or a high-k material (e.g., metal oxide of Al) are both suitable materials for forming the U-shaped first hard mask layers 142 over gate structure 138.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have either silicon nitride or a high-k dielectric material as the material of the blanket dielectric layer in the method of Lee in view of Chu, because these are known in the semiconductor manufacturing art as being equivalent and suitable materials for forming a dielectric protection layer over a gate structure, as suggested by Wu, and selecting among them would have been obvious to the skilled artisan. See In re KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007). Therefore, Lee in view of Chu, and in further view of Wu teaches that the blanket dielectric layer includes the same high-k dielectric material as the gate dielectric layer.
Regarding Claim 7, Lee (see, e.g., Fig. 7 and Par. [0044]) shows that the blanket dielectric layer (e.g., 182/110) includes silicon nitride. Therefore, Lee in view of Chu is silent about the blanket dielectric layer including at least one material selected from the group consisting of a metal oxide or a metal silicate, the metal oxide or the metal silicate including at least one element selected from the group consisting of Hf, Al, Zr, La, Mg, Ba, Ti, or Pb. Wu (see, e.g., Fig. 5 and Par. [0049]), on the other hand and in the same field of endeavor, teaches that silicon nitride or aluminum oxide (i.e., metal oxide of Al) are suitable materials for forming the U-shaped first hard mask layers 142 over gate structure 138.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have either silicon nitride or aluminum oxide as the material of the dielectric protection layer in the method of Lee in view of Chu, because these are known in the semiconductor manufacturing art as being equivalent and suitable materials for forming a blanket dielectric layer over a gate structure, as suggested by Wu, and selecting among them would have been obvious to the skilled artisan. See In re KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007). Therefore, Lee in view of Chu, and in further view of Wu teaches that the blanket dielectric layer includes at least one material selected from the group consisting of a metal oxide or a metal silicate, the metal oxide or the metal silicate including at least one element selected from the group consisting of Hf, Al, Zr, La, Mg, Ba, Ti, or Pb.
Claims 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US2019/0165114) in view of Liou et al. (US2016/0284641).
Regarding Claim 18, Lee (see, e.g., Fig. 11) shows a step of forming a pair of source/drain contacts (e.g., contacts 140) each electrically connected to a corresponding one of the pair of source/drain regions (e.g., SD). However, while Lee does not explicitly show a step of forming a gate contact electrically connected to the gate structure, wherein the gate contact extends through the second dielectric layer and the first dielectric layer, it would have been readily apparent to one of skill in the art that such gate contact must be made, so as to ensure the necessary voltage biasing of the gate electrode and achieve basic MOSFET functionality.
Additionally, such step is clearly suggested at least by Liou (see, e.g., Fig. 3 and Par. [0022]): forming a gate contact 50 electrically connected to a gate structure 38, wherein the gate contact extends through a second dielectric layer 46 and a first dielectric layer 44. Also see previously presented Wu et al. (US2020/0105931 at Fig. 5).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the step of forming a gate contact as claimed in the method of Lee, because it is known in the semiconductor manufacturing art that gate contacts are formed extending through portions of dielectric protection layers so as to electrically connect a gate structure, as suggested Liou, and applying a known method step for its conventional use/purpose would have been a common sense choice by the skilled artisan. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
Regarding Claim 19, Liou (see, e.g., Fig. 3 and Par. [0022]) teaches that the gate contact 50 is electrically isolated from any of the pair of source/drain contacts 50 by at least a portion of the first dielectric layer 44.
Allowable Subject Matter
Claims 10-16 are allowable.
Claim 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 10, the prior art of record fails to disclose or suggest a method of forming a semiconductor device, comprising the steps of: forming a second dielectric layer over the remaining portion of the first dielectric layer; and planarizing the second dielectric layer such that the gate spacers, the remaining portion of the first dielectric layer, and the second dielectric layer are coplanar.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Younes Boulghassoul at (571) 270-5514. The examiner can normally be reached on Monday-Friday 9am-6pm EST (Eastern Standard Time), or by e-mail via younes.boulghassoul@uspto.gov. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on (571) 272-1705. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/YOUNES BOULGHASSOUL/Primary Examiner, Art Unit 2814