DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 15, 2026 has been entered.
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed on January 15, 2026. Claims 1, 11, 17-18, 21 and 23-24 have been amended. New claim 25 has been added. Claims 2-3, 7, 19 and 22 have been canceled. Currently, claims 1, 4-6, 8-18, 20-21and 23-25 are pending.
Applicant’s amendment to claims 1, 18 and 23-24 successfully overcomes the 112(b) rejection of claims 1, 18 and 23-24, and dependent claims set forth in the previous Office Action.
Applicant’s amendment to claim 21 successfully overcomes the 112(d) rejection of claim 21 set forth in the previous Office Action.
Response to Arguments
Applicant’s arguments with respect to claims 1, 11 and 17 have been considered but are moot as applied to the newly added claim limitations because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Objections
Claims 1, 8 and 17 are objected to because of the following informalities:
For claim 1, “wherein of the dielectric spacer portions laterally surrounds a respective one of the MTJ memory cells” should read “wherein each of the dielectric spacer portions”. “removing portions of the buffer layer” should read “removing portion of the buffer layer”.
For claim 8, “buffer layer after the ion beam etch process comprise a recessed surface” should read” buffer layer after the ion beam etch process comprises a recessed surface”.
For claim 17, “connection-via-level dielectric layer coved by remaining..” should read, “ connection-via-level dielectric layer covered by remaining..”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 4-6, 8-10, 11-16, 21 and 23-25 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention.
Regarding claim 1, the claim recites, “forming dielectric spacer portions around the array of memory cells..” where memory cells are indefinite and lack antecedent basis.
Claims 4-6, 8-10, 21 and 23-25 depend upon claim 1 and do not rectify the problem therefore, they are also rejected.
Regarding claim 9, the claim recites, “a removing a first portion of the buffer layer from the logic region without removing a second portion from the memory array region”, which is indefinite as it is not clear what are the first and second portions. As per claim 1 buffer layer in the logic region has already been removed and the in the memory region recessed portions remain.
Claims 10 and 24 depend upon claim 9 and do not rectify the problem therefore they are also rejected.
Regarding claim 10, the claim recites, “a memory level dielectric layer directly on the top surface of the second portion of the buffer layer”, which is indefinite as the memory level dielectric layer as per claim 1 is in contact with the recessed buffer layer it is not clear what other second portion of the buffer layer it is in contact with.
Claim 24 depends upon claim 10 and does not rectify the problem therefore it is also rejected.
Regarding claim 11, the claim recites , “recessed horizontal surface segments of a top surface of the buffer layer are physically exposed between neighboring pairs among the dielectric spacers in the memory array region and portions of the buffer layer located in a logic region are removed entirely to physically expose a top surface of the connection-via- level dielectric layer while the connection-via-level dielectric layer is covered by remaining portions of the buffer layer in the memory array region”, which is indefinite as it is not clear at what step the buffer layer has the recessed horizontal surface segments which are exposed between neighboring pairs of dielectric spacers. It is also not clear what is the structural relationship between the recessed horizontal surface segments and the remaining portions of buffer layer in the memory array region.
The claim further recites, “wherein the second dielectric material of the memory-level dielectric layer ….and is vertically spaced from the buffer layer by the remaining portions of the buffer layer in the memory array region” which is indefinite as it is not clear how the memory level dielectric layer is vertically separated from the buffer layer as it is directly formed on the buffer layer.
The claim further recites, the horizontal surface of the connection-via-level dielectric layer, which is indefinite and lacks antecedent basis.
Claims 12-16 depend upon claim 11 and do not rectify the problem therefore, they are also rejected.
Regarding claims 14 and 15, the claims recite, “metallic etch mask portion”, which is indefinite and lacks antecedent basis since claim 11 recites “metallic etch mask portions”.
Regarding claim 17, the claim recites, “recessed horizontal surface segments of a top surface of the buffer layer are physically exposed between neighboring pairs among the dielectric spacers in the memory array region, wherein the anisotropic etch process removes a portion of the buffer layer in a logic region that is adjacent to the memory array region, whereby a top surface of the connection-via-level dielectric layer is physically exposed in the logic region while the connection-via-level dielectric layer is coved by remaining portions of the buffer layer in the memory array region”, which is indefinite as it is not clear at what step the buffer layer has the recessed horizontal surface segments which are exposed between neighboring pairs of dielectric spacers. It is also not clear what is the structural relationship between the recessed horizontal surface segments and the remaining portions of buffer layer in the memory array region formed by the anisotropic etch process.
Regarding claim 23, the claim recites, a top electrode of the MTJ memory cells, which is indefinite as the structural relationship of the top electrode with respect to the bottom electrode, MTJ layers and metallic etch mask portions recited in claim 1 is not clear.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-6, 8-10 and 23-25 are rejected under 35 U.S.C. 103 as being unpatentable over Noh (US 2018/021210 A1) in view of Tseng et al. (US 2019/0148625 A1; hereafter Tseng) Lin et al. (US 2022/0045266 A1; hereafter Lin).
Regarding claim 1, Noh teaches a method of forming a memory device (see e.g., Figures 10-15), the method comprising:
forming a dielectric layer stack (see e.g., mold insulating layer 130 including first and second mold insulating layers 132 and 134, Para [0045], Figures 10-15) comprising a connection-via-level dielectric layer comprising a first dielectric oxide material (see e.g., first mold insulating layer 132 made of for example silicon oxide, Para [0045], Figures 10-15) and a buffer layer comprising a second dielectric oxide material (see e.g., second mold insulating layer 134 made of for example silicon oxynitride, Para [0045], Figures 10-15);
forming connection via structures through the dielectric layer stack (see e.g., bottom electrode contact BEC extending through the mold insulating layer 130, Para [0045], Figure 10);
forming a bottom electrode layer comprising titanium nitride (see e.g., a bottom electrode layer BEL may be formed of or include at least one of conductive metal nitrides e.g., titanium nitride, Para [0049], Figures 12-13) and magnetic tunnel junction (MTJ) layers over the dielectric layer stack (see e.g., a bottom electrode layer BEL and a magnetic tunnel junction layer MTJL are formed over the mold insulating layer 130, Para [0068], Figure 11);
forming metallic etch mask portions over the MTJ layers; (see e.g., the top electrode TE made of a conductive metal nitride for example, titanium nitride, tantalum nitride or tungsten nitride is used as a mask to etch the magnetic tunnel junction layer MTJL and the bottom electrode layer BEL, Paras [0068] - [0070], Figure 12)
patterning the MTJ layers and the bottom electrode layer into an array of magnetic tunnel junction (MTJ) memory cells in a memory array region by performing an ion beam etch process (see e.g., the etching of the magnetic tunnel junction layer MTJL and the bottom electrode layer BEL may be performed using, for example, an ion beam etching process to form the memory elements ME including the bottom electrode BE and the magnetic tunnel junction MTJ, Para [0070], Figure 13),
forming dielectric spacer portions around the array of memory cells, wherein of the dielectric spacer portions laterally surrounds a respective one of the MTJ memory cells (see e.g., capping insulating layer 140 laterally surrounds the memory elements ME, Paras [0051], [0071], Figures 14-15);
anisotropically etching portions of the buffer layer that are not masked by the memory cells to form recessed surfaces of the buffer layer between neighboring pairs of bottom electrodes within the memory array region (see e.g., an ion beam etching process is performed to etch the memory elements and top surface of the second mold insulating layer 134 in regions not masked by the memory elements to form recessed top surfaces 134a, Para [0070], Figure 13) while removing portions of the buffer layer in a logic region to physically expose a top surface of the connection-via-level dielectric layer in the logic region; and (see e.g., the second mold layer 134b may be wholly removed from the second region R2 (not shown in drawings) to physically expose the top surface of the first mold insulating layer 132 in the second region R2, Para [0070], Figure 13)
depositing a memory-level dielectric layer … on the recessed surfaces of the buffer layer within the memory array region and directly on the physically exposed top surface of the connection-via-level dielectric layer within the logic region (see e.g., an insulating gap fill layer 150 may be formed to fill gap regions between memory elements in the first region R1. In case when the second mold layer 134 is wholly removed from the second region R2 the insulating gap fill layer 150 would be directly on the physically exposed top surface of the first mold insulating layer 132b in the second region R2, Para [0073], Figure 15).
Noh does not explicitly teach
“a first dielectric oxide material which is selected from undoped silicate glass or a doped silicate glass ……….a second dielectric oxide material which is selected from A1203 or Ta205”;
Although Noh’s disclosure does not explicitly teach the specific combination of a first dielectric oxide material selected from undoped or doped silicate glass and a second dielectric oxide material selected from AL2O3 or Ta2O5. However, Noh’s first molding insulating layer 132 (equivalent to instant application’s connection-via-level dielectric layer) is made of to be silicon oxide which is functionally equivalent to fluorine doped silicate glass and Noh’s second mold insulating layer 134 (equivalent to instant application’s buffer layer) is formed of dielectric material such as silicon nitride which is functionally equivalent to aluminum oxide layer as taught by Tseng.
In a similar field of endeavor Tseng teaches a first interlayer insulating layer ILD 210 made of one or more dielectric layers, such as silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics such as carbon doped oxides, extremely low-k dielectrics such as porous carbon doped silicon dioxide, a polymer such as polyimide, combinations of these, or the like. The first etch stop layer 220 includes a material different from the first ILD layer 210 and includes silicon carbide, silicon nitride, aluminum oxide or any other suitable material in some embodiments (see e.g., Paras [0040], [0050]).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Tseng’s teachings of a first dielectric oxide material which is selected from undoped silicate glass or a doped silicate glass… a second dielectric oxide material which is selected from A1203 or Ta205 in the method of Noh in order to use any of the alternatively usable materials and arrive at the claimed invention.
Noh does not explicitly teach
“etching portions of the buffer layer that are not masked by … the dielectric spacer portions to form recessed surfaces of the buffer layer between neighboring pairs of bottom electrodes within the memory array region
depositing a memory-level dielectric layer directly on the recessed surfaces of the buffer layer within the memory array region”.
Lin teaches alternative configurations for the stress compressive layer 22, either surrounding only the MTJ sidewalls (see e.g., Figure 8) or also covering the bottom of the gaps 18 (see e.g., Figure 9). Therefore, showing flexibility to optimize etch profiles according to specific device requirements.
In a similar field of endeavor Lin
etching portions of the buffer layer that are not masked by …. the dielectric spacer portions to form recessed surfaces of the buffer layer between neighboring pairs of bottom electrodes within the memory array region (see e.g., as shown in Figure 8, top surface of the dielectric layer 10 that is not masked by the MRAMs and the spacers (etched portions of first compressive stress layer 22) is etched between neighboring pairs of bottom electrodes 15 within the memory cell region A, Para [0035])
depositing a memory-level dielectric layer directly on the recessed surfaces of the buffer layer within the memory array region (see e.g., as shown in Figure 10 tensile stress pieces 26 are deposited directly on the recessed surfaces of the dielectric layer 10 within the memory array region A, Para [0038]).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Lin’s teachings of etching portions of the buffer layer that are not masked by … the dielectric spacer portions to form recessed surfaces of the buffer layer between neighboring pairs of bottom electrodes within the memory array region
depositing a memory-level dielectric layer directly on the recessed surfaces of the buffer layer within the memory array region in the method of Noh in order to reduce the compressive stress applied to the MTJ sidewalls.
Regarding claim 4, Noh, as modified by Tseng and Lin, teaches the limitations of claim 1 as mentioned above. Noh further teaches
wherein the dielectric layer stack further comprises a dielectric capping layer that underlies the connection-via-level dielectric layer (see e.g., etch stop layer 128 underlying the mold insulating layer 130 and includes silicon nitride or silicon carbonitride, Para [0066], Figures 10-15).
Regarding claim 5, Noh, as modified by Tseng and Lin, teaches the limitations of claim 4 as mentioned above. Noh further teaches
wherein the dielectric capping layer comprises a material selected from silicon nitride and silicon carbide (see e.g., etch stop layer 128 underlying the mold insulating layer 130 and includes silicon nitride or silicon carbonitride, Para [0066], Figures 10-15).
Regarding claim 6, Noh, as modified by Tseng and Lin, teaches the limitations of claim 1 as mentioned above. Noh further teaches
further comprising: a semiconductor substrate (see e.g., silicon, germanium or a silicon-germanium substrate 100, Para [0044], Figures 10-15) underlying the dielectric layer stack (see e.g., the substrate 100 underlies the mold insulating layer 130); and dielectric material layers (see e.g., lower insulating layer 120 which maybe a multi-layered structure, Para [0064], Figures 10-15) embedding metal interconnect structures (see e.g., the first lower interconnect structure, formed in the lower insulating layer 120, includes cell contact plugs 122 and lower conductive patterns 124, Para [0064], Figures 10-15) and located between the semiconductor substrate and the dielectric layer stack (see e.g., the lower insulating layer 120 is located between the substrate 100 and the mold insulating layer 130, Figures 10-15), wherein the dielectric layer stack is formed over a topmost surface of the dielectric material layers (see e.g., the mold insulating layer130 is formed over the lower interlayered insulating layer 120, Para [0064], Figures 10-15).
Regarding claim 8, Noh, as modified by Tseng and Lin, teaches the limitations of claim 1 as mentioned above. Noh further teaches
wherein the buffer layer (see e.g., second mold insulating layer 134, Para [0045], Figures 10- 13) after the ion beam etch process (see e.g., etching of the magnetic tunnel junction layer MTJL and the bottom electrode layer BEL is performed using for example, ion beam etching, Para [0070], Figure 13) comprise a recessed surface (see e.g., the ion beam etching process is performed in such a way that an etch rate of the second mold insulating layer 134 is higher than that of the magnetic tunnel junction layer MTJL. Thus, between the magnetic tunnel junctions MTJ, a top surface of the second mold insulating layer 134 may be recessed during the formation of the memory elements ME. Owing to a difference in pattern density between the first and second regions R1 and R2, the recess depth of the top surface of the second mold insulating layer 134 may be greater on the second region R2 than on the first region R1. Accordingly, the second mold insulating layer 134 may be formed to have recessed top surfaces 134a and 134b whose levels are different from each other. The recessed top surface 134b of the second mold insulating layer 134 on the second region R2 may be lower than the recessed top surface 134a of the second mold insulating layer 134 on the first region R1. The second mold insulating layer 134 may be wholly removed from the second region R2, Para [0070], Figure 13) that is formed above a horizontal plane including a bottom surface of the remaining portion of the buffer layer (see e.g., the recessed portions 134a and 134b are formed above the bottom surface of the remaining portion of the second mold insulating layer 134 as shown in Figure 13).
Regarding claim 9, Noh, as modified by Tseng and Lin, teaches the limitations of claim 1 as mentioned above. Noh further teaches
further comprising removing a first portion of the buffer layer from a logic region to expose a top surface of the connection-via-level dielectric layer without removing a second portion of the buffer layer from a memory array region that includes the MTJ memory cell (see e.g., ion beam etching process forms recessed portion 134a in the memory region R1 and 134b in the logic region. The second mold insulating layer 134 may be wholly removed from the second region R2 in which case it would exposé a top surface of the first mold insulating layer 132, Para [0070], Figure 13).
Regarding claim 10, Noh, as modified by Tseng and Lin, teaches the limitations of claim 9 as mentioned above. Noh further teaches
further comprising forming a memory level dielectric layer directly on the top surface of the contact-via-level dielectric layer and the second portion of the buffer layer (see e.g., upper interlayered insulating layer 150 formed on the recessed portions 134a of the second mold insulating layer portions 134. In case the recessed portion 134b is wholly removed from the logic region the upper interlayered insulating layer 150 would be directly on the top surface of first mold insulating layer 132, Para [0070], Figure 15).
Regarding claim 23, Noh, as modified by Tseng and Lin, teaches the limitations of claim 1 as mentioned above. Noh further teaches
further comprising forming a memory-level dielectric layer around the MTJ memory cells (see e.g., capping insulating layer 140 formed around the memory elements, Para [0071], Figure 15);
Noh does not explicitly teach
“forming a via-level dielectric layer over the memory-level dielectric layer; and
forming an array of contact via structures through the via-level dielectric layer, wherein each contact via structure is electrically connected to a respective top electrode of the MTJ memory cells within the array”.
In a similar field of endeavor Lin teaches
forming a via-level dielectric layer over the memory-level dielectric layer; and (see e.g. the top portion of the interlayer dielectric 32, Para [0031], Figure 10)
forming an array of contact via structures through the via-level dielectric layer (see e.g., metal interconnections 34 pass through the top portion of the interlayer dielectric 34, Para [0031], Figure 10), wherein each contact via structure is electrically connected to a respective top electrode of the MTJ memory cells within the array (see e.g., each of the metal interconnections 34 contact the top electrode 12 of the MRAM, Para [0031], Figure 10)
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement forming a via-level dielectric layer over the memory-level dielectric layer; and forming an array of contact via structures through the via-level dielectric layer, wherein each contact via structure is electrically connected to a respective top electrode of the MTJ memory cells within the array in the method of Noh in order to connect to other devices in the integrated circuit.
Regarding claim 24, Noh, as modified by Tseng and Lin, teaches the limitations of claim 10 as mentioned above. Noh further teaches
further comprising:
depositing a material layer comprising a metal nitride over the magnetic tunnel junction (MTJ) layers and the bottom electrode layer (see e.g., the top electrode layer TEL comprising titanium nitride or tantalum nitride is deposited over the magnetic tunnel junction layer MTJL and the bottom electrode layer BEL, Paras [0054], [0068], [0069], Figure 11);
forming a patterned photoresist mask over the material layer; and etching unmasked portions of the material layer using an ion beam etch process to form the metallic etch mask portions over the MTJ layers (see e.g., the formation of the top electrode TE may include forming a mask pattern on the top electrode layer TEL and etching the top electrode layer TEL using the mask pattern as an etch mask. The etching of the top electrode layer TEL may be performed using a dry etching process, such as a plasma etching process or a reactive ion etching process. The memory elements ME may be formed on the bottom electrode contacts BEC by sequentially etching the magnetic tunnel junction layer MTJL and the bottom electrode layer BEL using the top electrode TE as a mask, Paras [0069] – [0070], Figure 12).
Regarding claim 25, Noh, as modified by Tseng and Lin, teaches the limitations of claim 1 as mentioned above. Noh does not explicitly teach
“wherein the dielectric spacer portions are laterally spaced apart among one another and are not in direct contact among one another”.
In a similar field of endeavor Lin teaches
wherein the dielectric spacer portions are laterally spaced apart among one another and are not in direct contact among one another (see e.g., as shown in Figure 8, the spacers (etched portions of first compressive stress layer 22) are laterally spaced apart and are not in direct contact with each other, Para [0035]).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Lin’s teachings of wherein the dielectric spacer portions are laterally spaced apart among one another and are not in direct contact among one another in the method of Noh in order to reduce the compressive stress applied to the MTJ sidewalls.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Noh (US 2018/021210 A1) in view of Tseng et al. (US 2019/0148625 A1; hereafter Tseng) Lin et al. (US 2022/0045266 A1; hereafter Lin) and further in view of Wang et al. (US 10,727,397 B1; hereafter Wang).
Regarding claim 21, Noh, as modified by Tseng and Lin, teaches the limitations of claim 1 as mentioned above. Noh further teaches
further comprising conformally depositing a first dielectric material over the array of MTJ memory cells (see e.g., the capping layer 140 is conformally deposited over the array of memory elements, Para [0071], Figure 14).
Noh does not explicitly teach
“etching a first dielectric material over the array of MTJ memory cells, wherein remaining portions of the first dielectric material comprise the dielectric spacer portions, the dielectric spacer portions are laterally spaced apart among one another”.
In a similar field of endeavor Lin teaches
etching a first dielectric material over the array of MTJ memory cells, wherein remaining portions of the first dielectric material comprise the dielectric spacer portions, the dielectric spacer portions are laterally spaced apart among one another (see e.g., as shown in Figure 8 the first compressive stress layer 22 is etched to form spacers laterally spaced apart from one another)
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Lin’s teachings of etching a first dielectric material over the array of MTJ memory cells, wherein remaining portions of the first dielectric material comprise the dielectric spacer portions, the dielectric spacer portions are laterally spaced apart among one another in the method of Noh in order to reduce the compressive stress applied to the MTJ sidewalls.
Noh does not explicitly teach
“anisotropically etching a first dielectric material over the array of MTJ memory cells”,
In a similar field of endeavor Wang teaches
anisotropically etching a first dielectric material over the array of MTJ memory cells (see e.g., the spacer layer 340 is etched by anisotropic dry etching to form spacers around the MTJ stack, Figure 1),
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Wang’s teachings of anisotropically etching a first dielectric material over the array of MTJ memory cells in the method of Noh as anisotropic etching provides selective removal of material along specific orientations or directions.
Claims 11 and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Noh (US 2018/021210 A1) in view of Lin et al. (US 2022/0045266 A1; hereafter Lin) and Dai et al. (US 2019/0148633 A1; hereafter Dai).
Regarding claim 11, Noh teaches a method of forming a memory device (see e.g., Figures 10-15), the method comprising:
forming first metal line structures (see e.g., first lower interconnect structure including cell contact plugs 122 and lower conductive patterns 124, Para [0064], Figures 10-15) in a dielectric material layer (see e.g., the first lower interconnect structure formed in the lower interlayered insulating layer 120, Para [0064], Figures 101-5) overlying a substrate (see e.g., the lower interlayered insulating layer formed on a substrate 100);
forming a dielectric layer stack (see e.g., etch stop layer 128 and the mold insulating layer 130, Para [0066], Figures 10-15) including, from bottom to top, a dielectric cap layer (see e.g., bottommost layer the etch stop layer 128, Para [0066], Figures 10-15), a connection-via-level dielectric layer (see e.g., first mold insulating layer 132, Para [0066], Figures 10-15), and a buffer layer (see e.g., the second mold insulating layer 134 the top most layer, Para [0066], Figures 10-15) over the first metal line structures and the dielectric material layer and;(see e.g., the etch stop layer 128 and the mold insulating layer 130 formed over the first lower interconnect structure and the lower interlayered insulating layer 120, Figures 10-15)
forming connection via structures (see e.g., the bottom electrode contacts BEC, Para 0067], Figures 10-15) through the dielectric layer stack (see e.g., the bottom electrode contact BEC penetrates the etch stop layer 128 and the mold insulating layer 130, Figures 10-15) on top surfaces of the first metal line structures (see e.g., the bottom electrode contacts BEC formed on top surfaces of the lower conductive pattern 124, Para [0067], Figures 10-15);
forming a bottom electrode layer (see e.g., bottom electrode layer BEL, Para [0068], Figure 11) and magnetic tunnel junction (MTJ) layers (see e.g., the magnetic tunnel junction layer MTJL, Para [0068], Figure 11) over the dielectric layer stack (see e.g., the bottom electrode layer BEL and the magnetic tunnel junction layer MTJL formed over the etch stop layer 128 and the mold insulating layer 130, Figure 11);
forming metallic etch mask portions over the MTJ layers in a memory array region; and (see e.g., the top electrode TE, made of a conductive metal nitride such as titanium nitride or tungsten nitride, is used as an etch mask over the magnetic tunnel junction layer MTJL and the bottom electrode layer BEL in the memory region R1, Paras [0068], [0070], Figure 12)
patterning the MTJ layers and the bottom electrode layer into an array of magnetic tunnel junction (MTJ) memory cells by performing an ion beam etch process (see e.g., ion beam etching process is used to pattern the magnetic tunnel junction layer MTJL and the bottom electrode layer BEL to form memory elements with a bottom electrode BE and magnetic tunnel junction MTJ, Para [0070], Figure 13);
conformally depositing a first dielectric material over the array of MTJ memory cells, wherein … first dielectric material comprise dielectric spacers each laterally surrounding a respective one of the MTJ memory cells; and (see e.g., cap insulating layer 140 is formed covering the top and side surfaces of the memory elements ME. The cap insulating layer maybe formed or include silicon nitride, Para [0071], Figure 14) and portions of the buffer layer located in a logic region are removed entirely to physically expose a top surface of the connection-via- level dielectric layer (see e.g., the second mold layer 134b may be wholly removed from the second region R2 (not shown in drawings) to physically expose the top surface of the first mold insulating layer 132 in the second region R2, Para [0070], Figure 13) while the connection-via-level dielectric layer is covered by remaining portions of the buffer layer in the memory array region; and (see e.g., recessed second mold layer 134a covers the first mold layer 132, Para [0070], Figure 13)
forming a memory-level dielectric layer (see e.g., upper interlayered insulating layer 150, Para [0073], Figure 15) comprising a second dielectric material (see e.g., the upper interlayered insulating layer 150 is made of an insulating material, Para [0073], Figure 15) around the dielectric spacers (see e.g., the upper interlayered insulating layer 150 surround the capping insulating layer 140, Figure 15), wherein the second dielectric material of the memory-level dielectric layer is formed on the recessed horizontal surface segments of the top surface of the buffer layer (see e.g., the upper interlayered insulating layer 150 is formed on the recessed portion 134a of the second mold insulating layer 134 in the memory region R1, Figure 15), and directly contacts the horizontal surface of the connection-via-level dielectric layer in a logic region (see e.g., the upper interlayered insulating layer 150 will be directly on the top surface of the first mold insulating layer 132 in case the recessed portion 134b is wholly removed from the logic region R2, Para [0070], Figure 15) that is laterally spaced from the memory array region (see e.g., the logic region R2 is laterally spaced from the memory region R1, Figure 15), and is vertically spaced from the buffer layer by the remaining portions of the buffer layer in the memory array region (see e.g., upper interlayered insulating layer 150 is vertically separated from the first mold layer 132 by the recessed second mold layer 134a, Figure 15; Examiner’s interpretation: the memory level dielectric layer is separated vertically from the connection-via-level dielectric layer by the recessed buffer layer 134a)
Noh does not explicitly teach
“etching a first dielectric material over the array of MTJ memory cells, wherein remaining portions of the etched first dielectric material comprise dielectric spacer each laterally surrounding a respective one of the MTJ memory cells; and the dielectric spacers are laterally spaced apart from one another, and recessed surface segments of a top surface of the buffer layer are physically exposed between neighboring pairs of the dielectric spacers in the memory array region;….
wherein the second dielectric material of the memory-level dielectric layer is formed directly on the recessed surface segments of the top surface of the buffer layer between the neighboring pairs of the dielectric spacers in the memory array region”.
In a similar field of endeavor Lin teaches
etching a first dielectric material over the array of MTJ memory cells, wherein remaining portions of the etched first dielectric material comprise dielectric spacer each laterally surrounding a respective one of the MTJ memory cells; and the dielectric spacers are laterally spaced apart from one another (see e.g., The etched portions of first compressive stress layer 22, forming spacers, surround the sidewalls of the MRAMs. These spacers are laterally spaced apart from one another, Para [0035], Figure 10), and recessed surface segments of a top surface of the buffer layer are physically exposed between neighboring pairs of the dielectric spacers in the memory array region;….(see e.g., as shown in Figure 10 the recessed surface segments of the dielectric layer 10 are physically exposed between neighboring pairs of the spacers)
wherein the second dielectric material of the memory-level dielectric layer is formed directly on the recessed surface segments of the top surface of the buffer layer between the neighboring pairs of the dielectric spacers in the memory array region (see e.g., tensile stress pieces 26 are disposed in the gaps 18 and are formed directly on the recessed surface segments of the dielectric layer 10 between the neighboring pairs of spacers in the memory region, Para [0038], Figure 10)
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Lins’ teachings of wherein remaining portions of the etched first dielectric material comprise dielectric spacer each laterally surrounding a respective one of the MTJ memory cells; and the dielectric spacers are laterally spaced apart from one another, and recessed surface segments of a top surface of the buffer layer are physically exposed between neighboring pairs of the dielectric spacers in the memory array region;….
wherein the second dielectric material of the memory-level dielectric layer is formed directly on the recessed surface segments of the top surface of the buffer layer between the neighboring pairs of the dielectric spacers in the memory array region in the method of Noh in order to reduce the compressive stress applied to the MTJ sidewalls.
Noh does not explicitly teach
“anisotropically etching a first dielectric material over the array of MTJ memory cells,”
In a similar field of endeavor Dai teaches
anisotropically etching a first dielectric material over the array of MTJ memory cells (see e.g., a capping layer 600 is blanket deposited over the MTJ structures 500. An anisotropic etch back process can be used to remove portions of the capping layer 600 on horizontal surfaces of MTJ structures 500 in second area A2 above interconnect layer 310 (e.g., in an MRAM cell area of the die) to form spacers 700, Paras [0038], [0039], Figure 6),
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Dai’s teachings of anisotropically etching a first dielectric material over the array of MTJ memory cells in the method of Noh as selective removal can be carried out by anisotropic etching.
Regarding claim 14, Noh, as modified by Dai and Lin, teaches the limitations of claim 11 as mentioned above. Noh further teaches
further comprising planarizing the memory-level dielectric layer such that the top surface of the memory-level dielectric layer is formed in a horizonal plane including a top surface of the metallic etch mask portion (see e.g., the upper interlayered insulating layer 150 is planarized such that its top surface is at a horizontal level with the top electrode TE, Para [0073], Figure 15).
Regarding claim 15, Noh, as modified by Dai and Lin, teaches the limitations of claim 14 as mentioned above. Noh does not explicitly teach
“further comprising depositing and patterning at least one dielectric etch stop layer such that the at least one dielectric etch stop layer covers the metallic etch mask portion and does not cover an area within the logic region”.
In a similar field of endeavor Lin teaches
further comprising depositing and patterning at least one dielectric etch stop layer such that the at least one dielectric etch stop layer covers the metallic etch mask portion and does not cover an area within the logic region (see e.g., a second compressive stress layer 28 covers the opening of each gap 18 and contacts the tensile stress piece 26. The second compressive stress layer 28 covers the top electrode 12 and is removed from the peripheral circuit region B, Para [0030], Figure 10).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Lins’ teachings of further comprising depositing and patterning at least one dielectric etch stop layer such that the at least one dielectric etch stop layer covers the metallic etch mask portion and does not cover an area within the logic region in the method of Noh so that it can prevent moisture or oxygen from entering the dielectric.
Regarding claim 16, Noh, as modified by Dai and Lin, teaches the limitations of claim 15 as mentioned above. Noh further teaches
forming a connection via structure (see e.g., peripheral via plug 155, Para [0075], Figure 15) and wherein the connection via structure vertically extends through, and contacts, the dielectric layer stack and contacts one of the first metal line structures (see e.g., peripheral via plug 155 vertically extends through and contacts the first mold insulating layer 132 and the etch stop layer 128 and contacts the lower interconnection line 125, Para [0075], Figure 15).
Noh does not explicitly teach
“further comprising: forming a via-level dielectric layer over the at least one dielectric etch stop layer; and forming a contact via structure and a connection via structure through the via-level dielectric layer, wherein the contact via structure vertically extends through, and contacts, the at least one dielectric etch stop layer and contacts a top surface of the metallic etch mask portion”.
In a similar field of endeavor Lin teaches
further comprising: forming a via-level dielectric layer over the at least one dielectric etch stop layer (see e.g., dielectric layer 32, Figure 10); and forming a contact via structure (see e.g., contact 36 in the memory cell region A, Figure 10) and a connection via structure (see e.g., contact 36 in the logic region B, Figure 10) through the via-level dielectric layer (see e.g., the contacts 36 pass through the dielectric 32 in both in the memory cell region A and the logic region B, Figure 10), wherein the contact via structure vertically extends through, and contacts, the at least one dielectric etch stop layer and contacts a top surface of the metallic etch mask portion (see e.g., the contact 36 in the memory cell region A vertically extends through the second stress compressive layer 28 and contacts the top electrode 12),
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively field to implement Sung’s teachings of further comprising: forming a via-level dielectric layer over the at least one dielectric etch stop layer; and forming a contact via structure and a connection via structure through the via-level dielectric layer, wherein the contact via structure vertically extends through, and contacts, the at least one dielectric etch stop layer and contacts a top surface of the metallic etch mask portion in the method of Noh in order to provide electrical connections.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Noh (US 2018/021210 A1) in view of Lin et al. (US 2022/0045266 A1; hereafter Lin) and Dai et al. (US 2019/0148633 A1; hereafter Dai) and further in view of Tseng et al. (US 2019/0148625 A1; hereafter Tseng).
Regarding claim 12, Noh, as modified by Dai and Lin, teaches the limitations of claim 11 as mentioned above. Noh does not explicitly teach
“wherein the buffer layer comprises aluminum oxide (Al2O3)”.
However, Noh’s second mold insulating layer 134 (equivalent to instant application’s buffer layer) is formed of dielectric material such as silicon nitride which is functionally equivalent to aluminum oxide layer as taught by Tseng.
In a similar field of endeavor Tseng teaches the first etch stop layer 220 includes a material different from the first ILD layer 210 and includes silicon carbide, silicon nitride, aluminum oxide or any other suitable material in some embodiments (see e.g., Para [0050]).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Tseng’s teachings of wherein the buffer layer comprises aluminum oxide (Al2O3) in the method of Noh in order to use any of the alternatively usable material and arrive at the claimed invention.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Noh (US 2018/021210 A1) in view of Lin et al. (US 2022/0045266 A1; hereafter Lin) and Dai et al. (US 2019/0148633 A1; hereafter Dai) and further in view of AVCI et al. (US 2020/0105743 A1; hereafter AVCI).
Regarding claim 13, Noh, as modified by Dai and Lin, teaches the limitations of claim 11 as mentioned above. Noh does not explicitly teach
“wherein the buffer layer comprises tantalum pentoxide (Ta2O5)”.
However, Noh’s second mold insulating layer 134 is made of dielectric material such as silicon nitride or silicon oxynitride is functionally equivalent to a tantalum pentoxide layer as taught by AVCI.
In a similar field of endeavor AVCI teaches a dielectric layer made from one or a combination of dielectric materials such as silicon dioxide (Si02), aluminum oxide (Al203), hafnium oxide (Hf02), zirconium dioxide (Zr02), tantalum pentoxide (Ta2O5), titanium dioxide (Ti02), and lanthanum oxide (La203), among others, a carbon (C)-doped oxide, a nitride, such as silicon nitride (Si3N4), or a carbide, such as silicon carbide (SiC) (see e.g., Para [0034]).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement AVCI’s teachings of wherein the buffer layer comprises tantalum pentoxide (Ta2O5) in the method of Noh in order to use any of the alternatively usable materials and arrive at the claimed invention.
Claims 17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Noh (US 2018/021210 A1) in view of Lin et al. (US 2022/0045266 A1; hereafter Lin), Dai et al. (US 2019/0148633 A1; hereafter Dai) and Hsu et al. (US 2024/0172456 A1; hereafter Hsu).
Regarding claim 17, Noh teaches a method of forming a memory device (see e.g., Figures 10-15), the method comprising:
forming metal line structures (see e.g., first lower interconnect structure including cell contact plugs 122 and lower conductive patterns 124, Para [0064], Figures 10-15) in a dielectric material layers (see e.g., the first lower interconnect structure formed in the lower interlayered insulating layer 120, Para [0064], Figures 101-5) overlying a substrate (see e.g., the lower interlayered insulating layer formed on a substrate 100);
forming a dielectric layer stack (see e.g., etch stop layer 128 and the mold insulating layer 130, Para [0066], Figures 10-15) including, from bottom to top, a dielectric cap layer, (see e.g., bottommost layer the etch stop layer 128, Para [0066], Figures 10-15), a connection-via-level dielectric layer (see e.g., first mold insulating layer 132, Para [0066], Figures 10-15), and a buffer layer (see e.g., the second mold insulating layer 134 the top most layer, Para [0066], Figures 10-15) over the dielectric material layers(see e.g., the etch stop layer 128 and the mold insulating layer 130 formed over the first lower interconnect structure and the lower interlayered insulating layer 120, Figures 10-15);
forming an array of connection via structures (see e.g., an array of the bottom electrode contact BEC, Para [0067], Figures 10-15) through the dielectric layer stack (see e.g., the bottom electrode contact BEC penetrates the etch stop layer 128 and the mold insulating layer 130, Figures 10-15) on a respective one of the metal line structures; and (see e.g., each of the bottom electrode contact BEC formed on a respective top surface of the lower conductive pattern 124, Para [0067], Figures 10-15)
forming a bottom electrode layer comprising titanium nitride (see e.g., bottom electrode layer BEL comprising titanium nitride, Paras [0049], [0068], Figure 11) and magnetic tunnel junction (MTJ) layers (see e.g., the magnetic tunnel junction layer MTJL, Para [0068], Figure 11) over the dielectric layer stack (see e.g., the bottom electrode layer BEL and the magnetic tunnel junction layer MTJL formed over the etch stop layer 128 and the mold insulating layer 130, Figure 11);
forming an array of metallic etch mask portions over the MTJ layers in a memory array region; and (see e.g., an array of the top electrode TE, made of a conductive metal nitride such as titanium nitride or tungsten nitride, is used as an etch mask over the magnetic tunnel junction layer MTJL and the bottom electrode layer BEL in the memory region R1, Paras [0068], [0070], Figure 12)
patterning the MTJ layers and the bottom electrode layer into an array of stacks of a bottom electrode and a magnetic tunnel junction (MTJ) memory cell by performing an ion beam etch process (see e.g., ion beam etching process is used to pattern the magnetic tunnel junction layer MTJL and the bottom electrode layer BEL to form memory elements ME with a bottom electrode BE and magnetic tunnel junction MTJ, Para [0070], Figure 13), wherein a recessed top surface of the buffer layer is formed between neighboring pairs of the bottom electrodes within the array of stacks (see e.g., the recessed portion 134a of the second mold insulating layer 134 is formed between neighboring pairs of bottom electrodes, Para [0070], Figure 15);
conformally depositing a first dielectric material over the array of MTJ memory cells, wherein … the first dielectric material comprise an array of dielectric spacers each laterally surrounding a respective one of the MTJ memory cells; and (see e.g., cap insulating layer 140 is formed covering the top and side surfaces of the memory elements ME. The cap insulating layer maybe formed or include silicon nitride, Para [0071], Figure 14)
forming an array of a dielectric spacer around the array of stacks (see e.g., cap insulating layer 140 covering the side surfaces of the memory elements ME, Para [0071], Figure 14);
wherein the anisotropic etch process removes a portion of the buffer layer in a logic region that is adjacent to the memory array region, whereby a top surface of the connection-via-level dielectric layer is physically exposed in the logic region while the connection-via-level dielectric layer covered by remaining portions of the buffer layer in the memory array region; and (see e.g., the logic region R2 is adjacent to the memory region R1. Second mold insulating layer 134 has a recessed portion 134b in the logic region which may be wholly removed in which case the top surface of the first mold layer 132 would be exposed in the logic region. The recessed second mold layer 134a in the memory region covers the underlying first mold layer 132, Para [0070], Figure 15)
forming a memory-level dielectric layer (see e.g., upper interlayered insulating layer 150, Para [0073], Figure 15) comprising a second dielectric material (see e.g., the upper interlayered insulating layer 150 is made of an insulating material, Para [0073], Figure 15) directly on the array of dielectric spacers (see e.g., the upper interlayered insulating layer 150 surround the capping insulating layer 140, Figure 15), segments of the recessed top surface of the buffer layer in the memory array region (see e.g., the upper interlayered insulating layer 150 is formed on the recessed portion 134a of the second mold insulating layer 134 in the memory region R1, Figure 15), and on the physically exposed top surface of the connection-via-level dielectric layer (see e.g., the upper interlayered insulating layer 150 will be directly on the top surface of the first mold insulating layer 132 in case the recessed portion 134b is wholly removed from the logic region R2, Para [0070], Figure 15), wherein the memory-level dielectric layer is vertically spaced from the connection-via-level dielectric layer by the remaining portions of the buffer layer in the memory array region (see e.g., insulating gap fill layer 150 is vertically spaced from the first mold layer 132 in the memory region by the recessed second mold layer 134a, Figure 15)
Noh does not explicitly teach
“performing an etch process that etches the first dielectric material, wherein the dielectric spacers are laterally spaced apart from one another, and recessed surface segments of a top surface of the buffer layer are physically exposed between neighboring pairs of the dielectric spacers in the memory array region;….
forming a memory-level dielectric layer …on the segments of the recessed top surface of the buffer layer located between the neighboring pairs among the dielectric spacers in the memory array region”.
In a similar field of endeavor Lin teaches
performing an etch process that etches the first dielectric material, wherein the dielectric spacers are laterally spaced apart from one another, and recessed surface segments of a top surface of the buffer layer are physically exposed between neighboring pairs of the dielectric spacers in the memory array region (see e.g., The etched portions of first compressive stress layer 22, forming spacers, surround the sidewalls of the MRAMs. These spacers are laterally spaced apart from one another, Para [0035], Figure 10), forming a memory-level dielectric layer …on the segments of the recessed top surface of the buffer layer located between the neighboring pairs among the dielectric spacers in the memory array region (see e.g., tensile stress pieces 26 are disposed in the gaps 18 and are formed directly on the recessed surface segments of the dielectric layer 10 between the neighboring pairs of spacers in the memory region, Para [0038], Figure 10)
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Lins’ teachings of performing an etch process that etches the first dielectric material, wherein the dielectric spacers are laterally spaced apart from one another, and recessed surface segments of a top surface of the buffer layer are physically exposed between neighboring pairs of the dielectric spacers in the memory array region;….
forming a memory-level dielectric layer …on the segments of the recessed top surface of the buffer layer located between the neighboring pairs among the dielectric spacers in the memory array region in the method of Noh in order to reduce the compressive stress applied to the MTJ sidewalls.
Noh does not explicitly teach
“performing anisotropic etch process that anisotropically etches the first dielectric material,”
In a similar field of endeavor Dai teaches
performing anisotropic etch process that anisotropically etches the first dielectric material (see e.g., a capping layer 600 is blanket deposited over the MTJ structures 500. An anisotropic etch back process can be used to remove portions of the capping layer 600 on horizontal surfaces of MTJ structures 500 in second area A2 above interconnect layer 310 (e.g., in an MRAM cell area of the die) to form spacers 700, Paras [0038], [0039], Figure 6),
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Dai’s teachings of performing anisotropic etch process that anisotropically etches the first dielectric material in the method of Noh so that selective removal can be carried out by anisotropic etching.
Noh does not explicitly teach
“wherein the anisotropic etch process removes a portion of the buffer layer in a logic region that is adjacent to the memory array region”,
In a similar field of endeavor Hsu teaches forming a capping layer 252 around the MRAM structures and on the dielectric layer 232. A photolithography process, which is understood to include an anisotropic etching, is performed to etch the cladding layer 252. While this cladding layer 252 is being etched the underlying dielectric layer 232 is also etched in the logic region 202 (see e.g., Para [0048], Figures 13 and 14).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement to remove the buffer layer in the logic region during the anisotropic etch process in order to remove material from the logic region that might not be suitable or properly patterned for the logic side.
Regarding claim 20, Noh, as modified by Dai, Lin and Hsu, teaches the limitations of claim 17 as mentioned above. Noh further teaches
wherein the dielectric capping layer comprises a material selected from silicon nitride and silicon carbide (see e.g., etch stop layer 128 made of silicon nitride or silicon carbide, Para [0066], Figures 10-15).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Noh (US 2018/021210 A1) in view of Lin et al. (US 2022/0045266 A1; hereafter Lin), Dai et al. (US 2019/0148633 A1; hereafter Dai), Hsu et al. (US 2024/0172456 A1; hereafter Hsu) and further in view of Tseng et al. (US 2019/0148625 A1; hereafter Tseng).
Regarding claim 18, Noh, as modified by Dai and Lin, teaches the limitations of claim 17 as mentioned above. Noh further teaches
wherein:
the connection-via-level dielectric layer comprises a first dielectric oxide material (see e.g., first mold insulating layer 132 made of for example silicon oxide, Para [0045], Figures 10-15);
the buffer layer comprises a second dielectric oxide material (see e.g., second mold insulating layer 134 made of for example silicon oxynitride, Para [0045], Figures 10-15);
the array of stacks is patterned by performing an ion beam etch process (see e.g., the etching of the magnetic tunnel junction layer MTJL and the bottom electrode layer BEL may be performed using, for example, an ion beam etching process to form the memory elements ME including the bottom electrode BE and the magnetic tunnel junction MTJ, Para [0070], Figure 13);
Noh does not explicitly teach
“a first dielectric oxide material which is selected from undoped silicate glass or a doped silicate glass ……….a second dielectric oxide material which is selected from A1203 or Ta205;”.
Although Noh’s disclosure does not explicitly teach the specific combination of a first dielectric oxide material selected from undoped or doped silicate glass and a second dielectric oxide material selected from AL2O3 or Ta2O5, nor does it specify the claimed etch rate ratios.
However, Noh’s first molding insulating layer 132 (equivalent to instant application’s connection-via-level dielectric layer) is made of to be silicon oxide which is functionally equivalent to fluorine doped silicate glass and Noh’s second mold insulating layer 134 (equivalent to instant application’s buffer layer) is formed of dielectric material such as silicon nitride which is functionally equivalent to aluminum oxide layer as taught by Tseng.
In a similar field of endeavor Tseng teaches a first interlayer insulating layer ILD 210 made of one or more dielectric layers, such as silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics such as carbon doped oxides, extremely low-k dielectrics such as porous carbon doped silicon dioxide, a polymer such as polyimide, combinations of these, or the like. The first etch stop layer 220 includes a material different from the first ILD layer 210 and includes silicon carbide, silicon nitride, aluminum oxide or any other suitable material in some embodiments (see e.g., Paras [0040], [0050]).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Tseng’s teachings of a first dielectric oxide material which is selected from undoped silicate glass or a doped silicate glass… a second dielectric oxide material which is selected from A1203 or Ta205 in the method of Noh in order to use any of the alternatively usable materials and arrive at the claimed invention.
Conclusion
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/FAKEHA SEHAR/ Examiner, Art Unit 2893
/YARA B GREEN/ Supervisor Patent Examiner, Art Unit 2893
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