DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Note by the Examiner
For clarity, references to specific claim numbers are presented in bold. Cited claim limitations are presented in bold the first time they are associated with a particular prior art disclosing the cited limitations, and subsequent reference to the already disclosed claim limitations are presented un-bolded. Certain elements from prior art which are not required by the claims are also presented un-bolded if they are particularly pertinent to understanding how the references are being combined. Item-to-item matching and Examiner explanations for 102 and/or 103 rejections have been provided in parenthesis.
Response to Amendment
The amendment filed February 26th, 2026, has been entered. Claims 1, 3-12, 14-18, and 20-27, are now pending in the application. Applicant’s amendments to the Specification and Claims have overcome each and every objection and 112(b) rejection previously set forth in the Non-Final Office Action mailed November 26th, 2025.
Information Disclosure Statement
The new information disclosure statement (IDS) submitted on February 26th, 2026, has been considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4-6, 9, 18, 21, and 25, are rejected under 35 U.S.C. 103 as unpatentable over Giacomini et al. (Giacomini, G. et al, “Fabrication and electrical characterization of High-Voltage silicon JFETs”, Journal of Instrumentation, Institute of Physics Publishing, Bristol, GB, vol. 14, no. 5, May 8, 2019, 15 pages), hereinafter referred to as “Giacomini”, in view of JP 2002043332 A, hereinafter referred to as “Horinouchi”.
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Regarding claim 1, Giacomini discloses a junction field effect transistor (JFET) (Giacomini Figure 1 (annotated above); see page 2, line 2), comprising: a drift region (see Giacomini Figure 1, “substrate”) disposed on a substrate (Giacomini Figure 1, “drain”; page 2, lines 5-10), the substrate including a drain region of the JFET (Giacomini page 2, lines 5-10); a lower gate region disposed on the drift region (see Giacomini Figure 1, “bottom gate”; page 2, lines 13-16); a source region disposed above the lower gate region (see Giacomini Figure 1, “source”; page 4, lines 3-5); an upper gate region at least partially surrounding the source region (see Giacomini Figure 1, “top gate”) and extending laterally beyond the lower gate region by a distance defining a gate offset width between the upper gate region and the lower gate region (see Giacomini Figure 1, “top gate” and gate offset width as shown in annotations above; page 2, lines 13-16 and page 4, lines 1-3); a channel region (see Giacomini Figure 1: the claimed channel region comprises a portion of the implant labeled “channel” as shown in the annotations above; see page 2, lines 13-16) extending from the source region and passing through a space between the upper gate region and the lower gate region (see Giacomini Figure 1);
Giacomini does not disclose a depletion limiter region disposed under the upper gate region, the depletion limiter region limiting a width of a depletion region formed under the upper gate region extending laterally beyond the lower gate region to preclude pinching off the channel region.
Horinouchi teaches a horizontal JFET (Horinouchi fig. 4(A); see page 8, lines 30-32) with a channel-forming region (Horinouchi fig. 4(A)-(B), 20) between the source region (Horinouchi fig. 4(A), 3) and drain region (Horinouchi fig. 4(A), 4) that has a doping concentration gradient such that the doping concentration decreases from source to drain (see Horinouchi fig. 4(A)-(B) (included above) and [0013], “the channel forming impurity region has an impurity concentration gradient that is higher on the source impurity region side and lower toward the drain impurity region side”).
The decreasing doping gradient teachings of Horinouchi are incorporated into the implant labeled “channel”: in the JFET device of Giacomini such that the doping concentration of the underlying semiconductor material decreases continuously from the source region in a direction towards the drain region along a source-to-drain current direction (i.e. towards the gap between “bottom gate” implants). In other words, the doping concentration gradient is disposed horizontally in the implant labeled “channel” wherein, within each JFET cell, a region within the “channel” implant below the source implant has a higher average doping concentration and a region below the top gate implant nearer to the backside drain along a source-to-drain current direction has a lower average doping concentration (see the above annotated Giacomini Figure 1 for reference; note that there is no substantial distinction between the “channel”, “substrate”, and “drain” implants of the n-type channel JFET device of Giacomini other than doping concentration which is achieved through individual ion implantations (see Giacomini page 7); in the combined device, the decreasing doping gradient of Horinouchi is applied horizontally within the “channel” implant with a gradient vector (within each JFET cell) aligned with the direction of the source-to-drain current in that JFET cell (which would flow during device operation)). The average doping profile of the channel implant with the doping gradient applied thereto is still higher than the doping concentration of the substrate as disclosed in Giacomini (see Giacomini pages 6 and 7 which discloses that the channel implant has a doping dosage such that its doping concentration is made to exceed the doping concentration of the base substrate (which includes the claimed drift region). Therefore, the combination discloses a depletion limiter region (see annotated Giacomini Figure 1 above; the claimed “depletion limiter region” is the indicated region directly below the top gate and adjacent to the indicated channel region) disposed under the upper gate region (see Giacomini Figure 1), the depletion limiter region limiting a width of a depletion region formed under the upper gate region extending laterally beyond the lower gate region to preclude pinching off the channel region (the indicated depletion limiter region would prevent channel pinch-off when the combined device is operating because the average doping concentration of said region is less than the average doping concentration of the adjacent channel region and greater than the average doping concentration of the drift region. This intermediate doping concentration would prevent the region from becoming fully depleted at reasonable gate-to-source operating voltages. Drain-to-source current would flow (and, thus, pinch-off would be prevented) as long as the indicated depletion limiter region is not fully depleted).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Giacomini with the decreasing doping gradient taught in Horinouchi to increase the cutoff frequency without shortening the gate length, and thereby improve the maximum available power gain of the device (see Horinouchi [0010]).
Regarding claim 4, Giacomini and Horinouchi disclose the JFET of claim 1, wherein the depletion limiter region (see indicated depletion limiter region in annotated Giacomini Figure 1 above) has a doping concentration that is greater than a doping concentration of the drift region (Giacomini Figure 1, “substrate”; see Giacomini pages 6-7 (“Fabrication” section) which discloses that the channel implant has a doping dosage such that its doping concentration is made to exceed the doping concentration of the base substrate (which includes the claimed drift region )) and less than a doping concentration of the channel region (see indicated channel region in annotated Giacomini Figure 1 above; in the combined device (in which the decreasing doping gradient of Horinouchi is applied in the channel implant within each JFET cell of the device of Giacomini), the average doping concentration of the indicated depletion limiter region is greater than the average doping concentration of the drift region (“substrate”) and less than the average doping concentration of the indicated channel region).
Regarding claim 5, Giacomini and Horinouchi disclose the JFET of claim 1, further comprising: a gate contact region (Giacomini Figure 1, “intermediate gate”; page 2, lines 20-22) that is in contact with the upper gate region (Giacomini Figure 1, “top gate”) and the lower gate region (Giacomini Figure 1, “bottom gate”) to provide a common gate contact to the upper gate region and the lower gate region (see Giacomini page 2, lines 18-22: “In the triode configuration, the shorting of the implants is achieved once the top gate implant is extended to the border of the device where it overlaps the bottom gate … an intermediate gate may be used to ohmically connect the two gates, as shown in figure 1”).
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Regarding claim 6, Giacomini and Horinouchi disclose the JFET of claim 5, wherein a source contact (see Giacomini Figure 3(d) (annotated above): source regions of each JFET cell are disposed below source contacts as shown) is disposed on the source region (Giacomini Figure 1, “source”) and the source contact and the common gate contact (Giacomini Figure 1, “intermediate gate”; page 2, lines 20-22) are disposed alternately in a layout of the JFET (Both page 5, lines 7-8, and page 7, lines 30-32, state that the “intermediate gate” of Figure 1 is disposed along the “edge” or “periphery” of the active area of the combined device, respectively; the “intermediate gate” acts as the common gate contact and alternates with the source regions in the combined device as indicated in the annotated Figure 1 from Giacomini above).
Regarding claim 9, Giacomini and Horinouchi disclose the JFET of claim 1, wherein the JFET is normally on (see Giacomini page 11, lines 4-5: “JFETs of both polarities, n and p-type, … are normally ON.”).
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Regarding claim 18, Giacomini discloses a method for forming a junction field effect transistor (JFET) (Giacomini Figure 1 (annotated above); see page 7, lines 1-2), comprising: disposing a drift region (Giacomini Figure 1, “substrate”) on a substrate (Giacomini Figure 1, “drain”; page 2, lines 5-10) including a drain region of the JFET (Giacomini page 2, lines 5-10); disposing a lower gate region on the drift region (see Giacomini Figure 1, “bottom gate”; page 2, lines 13-16); disposing a source region (Giacomini Figure 1, “source”; see page 7, lines 5-8) above the lower gate region; disposing an upper gate region (Giacomini Figure 1, “top gate”) at least partially surrounding the source region and extending laterally beyond the lower gate region by a distance defining a gate offset width between the upper gate region and the lower gate region (see Giacomini Figure 1, “top gate” and gate offset width as shown in annotations above; page 2, lines 13-16 and page 4, lines 1-3); forming a channel region (see Giacomini Figure 1: the claimed channel region comprises a portion the region labeled “channel” as shown in the annotations above; see page 2, lines 13-16) extending from the source region and passing through a space between the upper gate region and the lower gate region (see Giacomini Figure 1);
Giacomini fails to disclose disposing a depletion limiter region under the upper gate region, the depletion limiter region limiting a width of a depletion region formed under the upper gate region extending laterally beyond the lower gate region.
Horinouchi teaches a horizontal JFET (Horinouchi fig. 4(A); see page 8, lines 30-32) with a channel region (Horinouchi fig. 4(A)-(B), 20) that has a doping concentration gradient such that the doping concentration decreases from source to drain (see Horinouchi fig. 4(A)-(B) (included above) and [0013], “the channel forming impurity region has an impurity concentration gradient that is higher on the source impurity region side and lower toward the drain impurity region side”).
The decreasing doping gradient teachings of Horinouchi are incorporated into the implant labeled “channel: in the JFET device formed by the method of Giacomini such that the doping concentration of the underlying semiconductor material decreases continuously from the source region in a direction towards the drain region along a source-to-drain current direction (i.e. towards the gap between “bottom gate” implants). In other words, the doping concentration gradient is disposed horizontally in the implant labeled “channel” wherein, within each JFET cell, a region within the “channel” implant below the source implant has a higher average doping concentration and a region below the top gate implant nearer to the backside drain along a source-to-drain current direction has a lower average doping concentration (see the above annotated Giacomini Figure 1 for reference; note that there is no substantial distinction between the “channel”, “substrate”, and “drain” implants of the n-type channel JFET device of Giacomini other than doping concentration which is achieved through individual ion implantations (see Giacomini page 7); in the combined device, the decreasing doping gradient of Horinouchi is applied horizontally within the “channel” implant with a gradient vector (within each JFET cell) aligned with the direction of the source-to-drain current in that JFET cell (which would flow during device operation)). The average doping profile of the channel implant with the doping gradient applied thereto is still higher than the doping concentration of the substrate as disclosed in Giacomini (see Giacomini pages 6 and 7 which discloses that the channel implant has a doping dosage such that its doping concentration is made to exceed the doping concentration of the base substrate (which includes the claimed drift region). Therefore, the combination discloses disposing a depletion limiter region (see annotated Giacomini Figure 1 above; the claimed “depletion limiter region” is the indicated region directly below the top gate and adjacent to the indicated channel region) under the upper gate region (see Giacomini Figure 1), the depletion limiter region limiting a width of a depletion region formed under the upper gate region extending laterally beyond the lower gate region (the indicated depletion limiter region would limit the extent of a depletion region formed under the upper gate region extending laterally beyond the lower gate region when the combined device is operating because the average doping concentration of the depletion limiter region is less than the average doping concentration of the adjacent channel region and greater than the average doping concentration of the drift region. This intermediate doping concentration would prevent the region from becoming fully depleted at reasonable gate-to-source operating voltages and thereby accomplish the claimed effect).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method for forming the device of Giacomini with the decreasing doping gradient taught in Horinouchi to increase the cutoff frequency without shortening the gate length, and thereby improve the maximum available power gain of the device (see Horinouchi [0010]).
Regarding claim 21, Giacomini and Horinouchi disclose the method of claim 18, further comprising: forming a gate contact region (see Giacomini Figure 1, “intermediate gate”) that is in contact with the upper gate region (Giacomini Figure 1, “top gate”) and the lower gate region (Giacomini Figure 1, “bottom gate”) to provide a common gate contact to the upper gate region and the lower gate region (see Giacomini page 2, lines 18-22: “In the triode configuration, the shorting of the implants is achieved once the top gate implant is extended to the border of the device where it overlaps the bottom gate … an intermediate gate may be used to ohmically connect the two gates, as shown in figure 1”; also see page 7, lines 29-31).
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Regarding claim 25, Giacomini and Horinouchi disclose the JFET of claim 1, wherein a length of the channel region (see Giacomini Figure 1: the claimed channel region comprises a portion the region labeled “channel” as shown in the annotations above; see page 2, lines 13-16) extends to an upper portion of the drift region (Giacomini Figure 1, “substrate”) and to the depletion limiter region (see annotated Giacomini Figure 1 above; the claimed “depletion limiter region” is the indicated region directly below the top gate and adjacent to the indicated channel region; the length of the indicated channel region extends to an upper portion of the “substrate” and to the indicated depletion limiter region).
Claim 7 is rejected under 35 U.S.C. 103 as unpatentable over Giacomini in view of Horinouchi, further in view of Asano et al. (K. Asano et al., "5 kV 4H-SiC SEJFET with low RonS of 69m/spl Omega/cm/sup 2/," Proceedings of the 14th International Symposium on Power Semiconductor Devices and Ics, Sante Fe, NM, USA, 2002, pp. 61-64), hereinafter referred to as “Asano”.
The combined device of Giacomini and Horinouchi discloses the JFET of claim 1.
Giacomini and Horinouchi fail to disclose wherein the substrate is a silicon carbide (SiC) substrate.
Asano discloses a JFET wherein the substrate is a silicon carbide (SiC) substrate (see Asano section 3, line 1).
The SiC substrate of Asano is incorporated as the substrate of the combined device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined JFET device of Giacomini and Horinouchi with the silicon carbide (SiC) substrate of Asano because of SiC’s “superior electrical and physical properties” (see Asano section 1, lines 1-6);
and the combination is a simple substitution of one known element for another to obtain predictable results – simple substitution of the silicon substrate of the combined JFET device of Giacomini and Horinouchi (Giacomini page 2, lines 1-3) with the silicon carbide substrate of Asano (see Asano section 3, line 1) to obtain predictable results (Asano section 1, lines 1-6).
Claim 8 is rejected under 35 U.S.C. 103 as unpatentable over Giacomini in view Horinouchi, further in view of Disney et al. (US 20080230812 A1), hereinafter referred to as “Disney”.
The combined device of Giacomini and Horinouchi discloses the JFET of claim 1.
Giacomini and Horinouchi fail to explicitly disclose a JFET wherein the gate overlap width between the upper gate region and the lower gate region is 0.2 microns or greater.
Disney discloses a JFET (Disney fig. 4, 100) wherein the gate overlap width between the upper gate region (Disney fig. 4, 108) and the lower gate region (Disney fig. 4, 102) is preferably 1 to 20 microns (see Disney [0054] and fig. 4; “the length Lg, which defines the length of a top gate region disposed above and overlapping a bottom gate region, is disclosed as “preferably 1 to 20 microns”;
See MPEP 2144.05 I. "In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990)").
The gate overlap width teachings of Disney are incorporated into the combined device of Giacomini and Horinouchi.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined JFET device of Giacomini and Horinouchi with the gate overlap width teachings of Disney in order to easily turn off the JFET device through biasing the gates (see Disney [0053]).
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Claims 10-12, and 22-24 are rejected under 35 U.S.C. 103 as unpatentable over Giacomini in view of Horinouchi, further in view of Fisher et al. (US 20220020874 A1), hereinafter referred to as “Fisher”.
Regarding claim 10, Giacomini discloses a junction field effect transistor (JFET) (Giacomini Figure 1) comprising: a substrate including a drain region of the JFET (Giacomini Figure 1 (annotated above), “drain”; page 2, lines 5-10); a drift region (see Figure 1, “substrate”) disposed on the substrate; and a plurality of device cells disposed in an array on the drift region (Giacomini Figure 1 shows three JFET cells disposed on a common drift region (“substrate”) ; pages 4-7 describe how a plurality of JFET cells are disposed on a wafer constituting a common drift (“substrate”) region), with each device cell including: a lower gate region (Giacomini Figure 1, “bottom gate”) disposed on the drift region; a source region (Giacomini Figure 1, “source”) disposed above the lower gate region; an upper gate region (Giacomini Figure 1, “top gate”; page 2, lines 13-16) at least partially surrounding the source region and extending laterally beyond the lower gate region by a distance defining a gate offset width between the upper gate region and the lower gate region (see the gate offset width as shown in annotations of Giacomini Figure 1 above; see Giacomini page 4, lines 1-3); a channel region (see Giacomini Figure 1: the claimed channel region comprises a portion of the implant labeled “channel” as shown in the annotations above; see page 2, lines 13-16) extending from the source region and passing through a space between the upper gate region and the lower gate region (see annotated Giacomini Figure 1 above); and a gate contact disposed over the upper gate region (see Giacomini Figure 3(d); gate contacts are indicated by dark rectangles overlaying the ”metal for top gate” regions which themselves overlay the top gate regions (c.f. Giacomini Figure 1)).
Giacomini fails to disclose a depletion limiter region under the upper gate region, the depletion limiter region limiting a width of a depletion region formed under the upper gate region extending laterally beyond the lower gate region; and a gate terminal contact region disposed on a side of the array of the plurality of device cells, the gate contact disposed over the upper gate region in each of the plurality of device cells extending to and being connected to the gate terminal contact region.
Horinouchi teaches a horizontal JFET (Horinouchi fig. 4(A); see page 8, lines 30-32) with a channel-forming region (Horinouchi fig. 4(A)-(B), 20) between the source region (Horinouchi fig. 4(A), 3) and drain region (Horinouchi fig. 4(A), 4) that has a doping concentration gradient such that the doping concentration decreases from source to drain (see Horinouchi fig. 4(A)-(B) (included above) and [0013], “the channel forming impurity region has an impurity concentration gradient that is higher on the source impurity region side and lower toward the drain impurity region side”).
The decreasing doping gradient teachings of Horinouchi are incorporated into the implant labeled “channel” in the JFET device of Giacomini such that the doping concentration of the underlying semiconductor material decreases continuously from the source region in a direction towards the drain region along a source-to-drain current direction (i.e. towards the gap between “bottom gate” implants). In other words, the doping concentration gradient is disposed horizontally in the implant labeled “channel” wherein, within each JFET cell, a region within the “channel” implant below the source implant has a higher average doping concentration and a region below the top gate implant nearer to the backside drain along a source-to-drain current direction has a lower average doping concentration (see the above annotated Giacomini Figure 1 for reference; note that there is no substantial distinction between the “channel”, “substrate”, and “drain” implants of the n-type channel JFET device of Giacomini other than doping concentration which is achieved through individual ion implantations (see Giacomini page 7); in the combined device, the decreasing doping gradient of Horinouchi is applied horizontally within the “channel” implant with a gradient vector (within each JFET cell) aligned with the direction of the source-to-drain current in that JFET cell (which would flow during device operation)). The average doping profile of the channel implant with the doping gradient applied thereto is still higher than the doping concentration of the substrate as disclosed in Giacomini (see Giacomini pages 6 and 7 which discloses that the channel implant has a doping dosage such that its doping concentration is made to exceed the doping concentration of the base substrate (which includes the claimed drift region). Therefore, the combination discloses a depletion limiter region (see annotated Giacomini Figure 1 above; the claimed “depletion limiter region” is the indicated region directly below the top gate and adjacent to the indicated channel region) disposed under the upper gate region (see Giacomini Figure 1), the depletion limiter region limiting a width of a depletion region formed under the upper gate region extending laterally beyond the lower gate region (the indicated depletion limiter region would limit the width of a depletion region formed under the upper gate region when the combined device is operating because the average doping concentration of said region is less than the average doping concentration of the adjacent channel region and greater than the average doping concentration of the drift region (see Giacomini pages 6 and 7 disclosing the relative doping concentrations of the various implants); this intermediate doping concentration would prevent the region from becoming fully depleted at reasonable gate-to-source operating voltages so as to limit the extent of the depletion region formed under the upper gate region (laterally) beyond the lower gate region during device operation).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Giacomini with the decreasing doping gradient taught in Horinouchi to increase the cutoff frequency without shortening the gate length, and thereby improve the maximum available power gain of the device (see Horinouchi [0010]).
Fisher discloses a gate terminal and contact structure for a transistor array device (see Fisher fig. 1) comprising a gate terminal contact region (Fisher fig. 1, gate pad 12; see [0005]) disposed on a side of the array of the plurality of device cells with gate contacts (Fisher fig. 1, gate fingers 16) extending over and coupling said plurality of device cells to the gate terminal contact region (see Fisher [0004]-[0005]; see Fisher fig. 1: gate fingers 16 extend to and are connected to gate pad 12 via gate bus 14; box 40 indicates the position of one unit cell of an implied plurality of transistor cells such, the gate electrode(s) of said unit cell being coupled to gate pad 12 and the gate electrode(s) of adjacent device cells).
The gate terminal and contact structure of Fisher is incorporated into combined device of Giacomini and Horinouchi wherein the combination discloses a gate terminal contact region disposed on a side of the array of the plurality of device cells, the gate contact disposed over the upper gate region in each of the plurality of device cells extending to and being connected to the gate terminal contact region (Fisher fig. 1, 12; in the combined device, the gate contact (Fisher fig. 1, 16) is disposed over the upper gate region (Giacomini Figure 1, “top gate”) in each JFET cell, extending to and being connected to said gate terminal contact region).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined device of Giacomini and Horinouchi with the gate terminal and contact structure of Fisher in order to increase the effective gate periphery of the device by electrically connecting a plurality of JFETs in parallel and thereby increasing the output power of the device (see Fisher [0004]). It should also be noted that the benefits of electrically connecting cell input terminals for transistor arrays to more efficiently couple with external power sources is well known in the art as demonstrated by Fisher’s discussion of prior art.
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Regarding claim 11, Giacomini, Horinouchi, and Fisher, disclose the JFET of claim 10, wherein each device cell (see Giacomini Figure 1; each device cell is characterized by a single source region) includes a gate contact region (Giacomini Figure 1, “intermediate gate”; page 2, lines 20-22) that is in contact with the upper gate region (Giacomini Figure 1, “top gate”) and the lower gate region (Giacomini Figure 1, “bottom gate”) to provide a common gate contact to the upper gate region and the lower gate region in each device cell (both Giacomini page 5, lines 7-8, and page 7, lines 30-32, state that the “intermediate gate” of Figure 1 is disposed along the “edge” or “periphery” of the active area of the reference device, respectively. The encircling “intermediate gate” acts as a gate contact region to ohmically connect the top gate regions and bottom gate regions in each JFET cell within an array of said JFET cells as taught in Giacomini Figure 1).
Regarding claim 12, Giacomini, Horinouchi, and Fisher, disclose the JFET of claim 10, wherein the upper gate region (Giacomini Figure 1, “top gate”) is disposed between two source regions (Giacomini Figure 1, “source”) of two adjacent device cells (see Giacomini Figure 1; the top gate region is disposed between source regions in each JFET cell in accordance with an interdigitated top gate and source configuration as described in Giacomini page 2, lines 29-31).
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Regarding claim 22, Giacomini discloses a method for forming junction field effect transistor (JFET) (Giacomini Figure 1; see Giacomini page 7, lines 1-4) comprising: disposing a drift region (Giacomini Figure 1, “substrate”) on a substrate (Giacomini Figure 1 (annotated above), “drain”; page 2, lines 5-10) including a drain region of the JFET (see Giacomini Figure 1 and page 2, lines 5-10); disposing a plurality of device cells in an array on the drift region (Giacomini Figure 1 shows three JFET cells disposed on a common drift region (“substrate”) ; pages 4-7 describe how a plurality of JFET cells are disposed on a wafer constituting a common drift (“substrate”) region), each device cell including: a lower gate region (Giacomini Figure 1, “bottom gate”) disposed on the drift region, a source region (Giacomini Figure 1, “source”) disposed above the lower gate region, an upper gate region (Giacomini Figure 1, “top gate”; page 2, lines 13-16) at least partially surrounding the source region, and extending laterally beyond the lower gate region to define a gate offset width between the upper gate region and the lower gate region (see the gate offset width as shown in annotations of Giacomini Figure 1 above; see Giacomini page 4, lines 1-3), a channel region (see Giacomini Figure 1: the claimed channel region comprises a portion of the implant labeled “channel” as shown in the annotations above; see page 2, lines 13-16) extending from the source region and passing through a space between the upper gate region and the lower gate region (see annotated Giacomini Figure 1 above), and a gate contact disposed over the upper gate region (see Giacomini Figure 3(d); gate contacts are indicated by dark rectangles overlaying the ”metal for top gate” regions which themselves overlay the top gate regions (c.f. Giacomini Figure 1)).
Giacomini fails to explicitly disclose a depletion limiter region disposed under the upper gate region, the depletion limiter region limiting a width of a depletion layer formed under the upper gate region extending laterally beyond the lower gate region; and disposing a gate terminal contact region on a side of the array of the plurality of device cells, the gate contact disposed over the upper gate region in each of the plurality of device cells extending to and being connected to the gate terminal contact region.
Horinouchi teaches a horizontal JFET (Horinouchi fig. 4(A); see page 8, lines 30-32) with a channel region (Horinouchi fig. 4(A)-(B), 20) that has a doping concentration gradient such that the doping concentration decreases from source to drain (see Horinouchi fig. 4(A)-(B) (included above) and [0013], “the channel forming impurity region has an impurity concentration gradient that is higher on the source impurity region side and lower toward the drain impurity region side”).
The decreasing doping gradient teachings of Horinouchi are incorporated into the implant labeled “channel” in the JFET device formed by the method of Giacomini such that the doping concentration of the underlying semiconductor material decreases continuously from the source region in a direction towards the drain region along a source-to-drain current direction (i.e. towards the gap between “bottom gate” implants). In other words, the doping concentration gradient is disposed horizontally in the implant labeled “channel” wherein, within each JFET cell, a region within the “channel” implant below the source implant has a higher average doping concentration and a region below the top gate implant nearer to the backside drain along a source-to-drain current direction has a lower average doping concentration (see the above annotated Giacomini Figure 1 for reference; note that there is no substantial distinction between the “channel”, “substrate”, and “drain” implants of the n-type channel JFET device of Giacomini other than doping concentration which is achieved through individual ion implantations (see Giacomini page 7); in the combined device, the decreasing doping gradient of Horinouchi is applied horizontally within the “channel” implant with a gradient vector (within each JFET cell) aligned with the direction of the source-to-drain current in that JFET cell (which would flow during device operation)). The average doping profile of the channel implant with the doping gradient applied thereto is still higher than the doping concentration of the substrate as disclosed in Giacomini (see Giacomini pages 6 and 7 which discloses that the channel implant has a doping dosage such that its doping concentration is made to exceed the doping concentration of the base substrate (which includes the claimed drift region). Therefore, the combination discloses disposing a depletion limiter region (see annotated Giacomini Figure 1 above; the claimed “depletion limiter region” is the indicated region directly below the top gate and adjacent to the indicated channel region) under the upper gate region (see Giacomini Figure 1), the depletion limiter region limiting a width of a depletion region formed under the upper gate region extending laterally beyond the lower gate region (the indicated depletion limiter region would limit the extent of a depletion region formed under the upper gate region extending laterally beyond the lower gate region when the combined device is operating because the average doping concentration of the depletion limiter region is less than the average doping concentration of the adjacent channel region and greater than the average doping concentration of the drift region. This intermediate doping concentration would prevent the region from becoming fully depleted at reasonable gate-to-source operating voltages and thereby accomplish the claimed effect).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method for forming the device of Giacomini with the decreasing doping gradient taught in Horinouchi to increase the cutoff frequency without shortening the gate length, and thereby improve the maximum available power gain of the device (see Horinouchi [0010]).
Fisher discloses a gate terminal and contact structure for a transistor array device (see Fisher fig. 1) comprising a gate terminal contact region (Fisher fig. 1, gate pad 12; see [0005]) disposed on a side of the array of the plurality of device cells with gate contacts (Fisher fig. 1, gate fingers 16) extending over and coupling said plurality of device cells to the gate terminal contact region (see Fisher [0004]-[0005]; see Fisher fig. 1: gate fingers 16 extend to and are connected to gate pad 12 via gate bus 14; box 40 indicates the position of one unit cell of an implied plurality of transistor cells such, the gate electrode(s) of said unit cell being coupled to gate pad 12 and the gate electrode(s) of adjacent device cells).
The gate terminal and contact structure of Fisher is incorporated into the device formed by the combined method of Giacomini and Horinouchi wherein the present combination discloses disposing a gate terminal contact region on a side of the array of the plurality of device cells, the gate contact disposed over the upper gate region in each of the plurality of device cells extending to and being connected to the gate terminal contact region (Fisher fig. 1, 12; in the combined device, the gate contact (Fisher fig. 1, 16) is disposed over the upper gate region (Giacomini Figure 1, “top gate”) in each JFET cell, extending to and being connected to said gate terminal contact region).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined method of Giacomini and Horinouchi with the gate terminal and contact structure of Fisher in order to increase the effective gate periphery of the device by electrically connecting a plurality of JFETs in parallel and thereby increasing the output power of the device (see Fisher [0004]). It should also be noted that the benefits of electrically connecting cell input terminals for transistor arrays to more efficiently couple with external power sources is well known in the art as demonstrated by Fisher’s discussion of prior art.
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Regarding claim 23, Giacomini, Horinouchi, and Fisher, disclose the method of claim 22, further comprising, in each device cell, forming a gate contact region (see Giacomini Figure 1, “intermediate gate”; page 2, lines 20-22) that is in contact with the upper gate region (Giacomini Figure 1, “top gate”) and the lower gate region (Giacomini Figure 1, “bottom gate”) to provide a common gate contact to the upper gate region and the lower gate region in each device cell (both Giacomini page 5, lines 7-8, and page 7, lines 30-32, state that the “intermediate gate” of Figure 1 is disposed along the “edge” or “periphery” of the active area of the reference device respectively. With respect to the above annotated figure, the encircling “intermediate gate” acts as a gate contact region to ohmically connect the top gate regions and bottom gate regions in each JFET cell within an array of said JFET cells as taught in Giacomini Figure 1).
Regarding claim 24, Giacomini, Horinouchi, and Fisher, disclose the method of claim 22, wherein the upper gate region (Giacomini Figure 1, “top gate”) is disposed between two source regions (Giacomini Figure 1, “source”) of two adjacent device cells (see Giacomini Figure 1; the top gate region is disposed between source regions in each JFET cell in accordance with an interdigitated top gate and source configuration as described in Giacomini page 2, lines 29-31).
Claim 14 is rejected under 35 U.S.C. 103 as unpatentable over Giacomini in view of Horinouchi, further in view of Fisher, further in view of Asano.
The combined device of Giacomini, Horinouchi, and Fisher, discloses the JFET of claim 10.
Giacomini, Horinouchi, and Fisher, fail to disclose wherein the substrate is a silicon carbide (SiC) substrate.
Asano discloses a JFET wherein the substrate is a silicon carbide (SiC) substrate (see Asano section 3, line 1).
The SiC substrate of Asano is incorporated as the substrate of the combined device.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined JFET device of Giacomini, Horinouchi, and Fisher, with the silicon carbide (SiC) substrate of Asano because of SiC’s “superior electrical and physical properties” (see Asano section 1, lines 1-6);
and the combination is a simple substitution of one known element for another to obtain predictable results – simple substitution of the silicon substrate of the combined JFET device of Giacomini, Horinouchi, and Fisher, (Giacomini page 2, lines 1-3) with the silicon carbide substrate of Asano (see Asano section 3, line 1) to obtain predictable results (Asano section 1, lines 1-6).
Claim 15 is rejected under 35 U.S.C. 103 as unpatentable over Giacomini in view of Horinouchi, further in view of Fisher, further in view of Asano, further in view of Boos (US 5196358 A), hereinafter referred to as “Boos”.
The combined device of Giacomini, Horinouchi, Fisher, and Asano, discloses the JFET of claim 14.
Giacomini, Horinouchi, Fisher, and Asano, fail to disclose wherein, at a gate to source voltage of 10 V, an input gate resistance of the JFET is 0.5 ohms or less.
Boos discloses an exemplary JFET having a total gate resistance that is completely dominated by the gate ohmic contact resistance, wherein such a contact resistance has been measured in the low 10E-5 ohms/cm2 range (Boos Col. 5, Lines 29-34).
Absent a showing of criticality with respect to the input gate resistance (a result effective variable), it would have been obvious to a person of ordinary skill in the art at the time of the invention to adjust the thickness through routine experimentation in order to achieve varying gate material, size, and gate contact conductors resulting in varying gate delay and frequency responses. Furthermore, the gate to source voltage is a user selectable application during use of the device which would not structurally distinguish from the disclosed structure. It has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980). Furthermore, note that Boos discloses a gate resistance in a low range which can be variably selected.
Boos discloses the claimed invention except for the gate to source voltage of 10V and resulting exact range of 0.5 ohms or less. It would have been obvious to one of ordinary skill in the art at the time the invention was made to select a gate to source voltage of 10V since it is a user selectable application which can be tuned to arrive at a desired gate resistance. Thus, it would have also been obvious to one of ordinary skill in the art at the time the invention was made to optimize the resulting gate resistance range, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
The gate to source voltage and resulting range of the input gate resistance as taught by Boos is applied to the combined device of Giacomini, Horinouchi, Fisher, and Asano.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Boos regarding input gate resistance with the combined JFET device of Giacomini, Horinouchi, Fisher, and Asano to improve the JFET frequency response (Boos, Col. 5, Lines 34-38).
Claim 16 is rejected under 35 U.S.C. 103 as unpatentable over Giacomini in view of Horinouchi, further in view of Fisher, further in view of JP S6177372 A, hereinafter referred to as “Yoshimitsu”.
The combined device of Giacomini, Horinouchi, and Fisher, discloses the JFET of claim 10.
Giacomini, Horinouchi, and Fisher, fail to disclose wherein a pitch of the JFET defined between adjacent device cells is 5 microns or less.
Yoshimitsu discloses an exemplary JFET wherein a pitch of the JFET defined between adjacent device cells is one micron (see Yoshimitsu page 2, lines 7-9: “Although it becomes the width of the distance between gates, i.e., a channel, by many channels JFET, the distance between this gate is a unit of a micron”; also see Yoshimitsu Figures 2-4;
See MPEP 2144.05 I. "In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990)").
The JFET cell pitch teachings of Yoshimitsu are incorporated into the combined device of Giacomini, Horinouchi, and Fisher.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the JFET cell pitch teachings of Yoshimitsu into the combined JFET device of Giacomini, Horinouchi, and Fisher, to more easily control the channel width (see Yoshimitsu page 2, lines 7-13: “The 2nd problem is control of channel width. … [T]his invention … sets it as that purpose to provide a semiconductor device without a problem”.).
Claim 17 is rejected under 35 U.S.C. 103 as unpatentable over Giacomini in view of Horinouchi, further in view of Fisher, further in view of Disney.
The combined device of Giacomini, Horinouchi, and Fisher, discloses the JFET of claim 11.
Giacomini, Horinouchi, and Fisher, fail to disclose wherein the overlap between the upper and lower gates is 0.2 microns or greater.
Disney discloses a JFET (Disney fig. 4, 100) wherein the gate overlap width between the upper gate region (Disney fig. 4, 108) and the lower gate region (Disney fig. 4, 102) is preferably 1 to 20 microns (see Disney [0054] and fig. 4; “the length Lg, which defines the length of a top gate region disposed above and overlapping a bottom gate region, is disclosed as “preferably 1 to 20 microns”;
See MPEP 2144.05 I. "In the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990)").
The gate overlap width teachings of Disney are incorporated into the combined device of Giacomini, Horinouchi, and Fisher.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combined JFET device of Giacomini, Horinouchi, and Fisher, with the gate overlap width teachings of Disney in order to easily turn off the JFET device through biasing the gates (see Disney [0053]).
Allowable Subject Matter
Claims 3, 20, 26, and 27, are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art made of record, either singularly or in combination, does not disclose or suggest at least the claim limitations of:
Claim 3, “wherein the depletion limiter region has a depth that is less than a depth of the channel region between the upper gate region and the lower gate region” – as instantly claimed and in combination with the additionally claimed limitations.
Claim 20, “wherein the depletion limiter region has a depth that is less than a depth of the channel region between the upper gate region and the lower gate region” – as instantly claimed and in combination with the additionally claimed limitations.
Claims 26 and 27 would be allowable because they are dependent on claim 3 and, thus, incorporate the same allowable subject matter.
Response to Arguments
Applicant's arguments filed February 26th, 2026, have been fully considered by the examiner, a minority of said arguments being persuasive and the others being unpersuasive.
On pages 9-10 of applicant’s response, applicant alleges that the combination of Giacomini and Horinouchi fails to disclose or suggest all of the limitations of claims 1 and 18 including, namely, “a depletion limiter region disposed under the upper gate region, the depletion limiter region limiting a width of a depletion region formed under the upper gate region extending laterally beyond the lower gate region to preclude pinching off the channel region”. Applicant immediately follows this allegation, on page 10 of applicant’s response, with a coincident allegation that the proposed modification of Giacomini with the relevant features of Horinouchi, and thus, the present obviousness rejection does not satisfy the requirements for prima facie obviousness under 35 U.S.C. 103. In support of these allegations, applicant provides several reasons which the examiner will now address individually.
On page 10 of applicant’s response, applicant alleges that it is improper for the Office to interpret the claimed “depletion limiter region” as a subunit of the claimed “channel region” in presently amended claims 1, 10, 18, and 22 and that, therefore, the Office’s prevailing interpretation of the claims exceeds what is permissible by the doctrine of broadest reasonable interpretation. In support of this allegation, applicant reasons that the decreasing doping gradient of Horinouchi, when combined with the JFET device of Giacomini, must be implemented to vary either horizontally or vertically with respect to the device pitch. Applicant presumes that the Office is interpreting the combined doping gradient as a horizontally varying gradient and that the Office Action then selects a portion of the region in which the gradient is applied as a “channel region” and an adjacent portion of that same region as a “depletion limiter region”. Applicant then notes that this is improper since the regions are named separately in the same claim and that, when read in light of the present specification, one would not reasonably interpret “the depletion limiter region” as a subregion of the “channel region”. Applicant further notes that either the horizontal or vertical interpretation of the combined doping gradient would be problematic for the obviousness rejection of claim 4. Applicant then requests that, if the obviousness rejection of the present claim 1 is maintained, the Office provide explanations as to (1) the orientation of the doping gradient applied from Horinouchi into the combined device, (2) how a subregion of said gradient can be interpreted as a region distinct from the channel itself, (3) how the Office’s interpretation can be reconciled with present claim 3, and (4) how the Office’s interpretation can be reconciled with present claim 4.
The examiner has thoroughly considered the above arguments yet finds them unpersuasive. The examiner has attempted to provide a better explanation of the Office’s interpretation of the combined JFET device of Giacomini and Horinouchi in the present obviousness rejection of claim 1 given in this Office Action. In summary, Horinouchi teaches a decreasing doping gradient in a horizontal JFET device with a doping concentration that varies from source to drain. It is well within the constraints of the prevailing doctrine of broadest reasonable interpretation (see MPEP 2111) and ordinary skill in the art to apply this horizontal decreasing doping gradient to the JFET device of Giacomini within the channel implant along a source-to-drain current direction going from the source region towards the backside drain region (i.e. in the direction of the gap between the lower gate regions). Applicant’s presumption is correct that the doping gradient would vary horizontally within each JFET cell. This modification creates various regions having distinct doping profiles within the channel implant: a region nearer to the source with a higher average doping concentration is a channel region and a region under the upper gate region (“top gate”) with a lower average doping concentration is a depletion limiter region. The average doping concentrations of both of these regions are still greater than the doping concentration of the drift region (“substrate” in Giacomini) as disclosed in Giacomini pages 6-7. This interpretation is consistent with the present specification which discloses that the only distinction between the relevant regions of the JFET device is doping concentration (along with any structural distinction that would come with changing the underlying semiconductor material’s doping concentration, yet said structural distinctions would also be present in the combined device of Giacomini and Horinouchi). PHOSITA would modify the channel implant of the JFET device of Giacomini with the proposed doping gradient in order to increase the cutoff frequency of the device and thereby improve the maximum available power gain as suggested by Horinouchi. In the Office’s interpretation, the depletion limiter region in the combined device is not a subregion of the channel region but, rather, a distinct region adjacent to the channel region. The Office’s interpretation is consistent with the present obviousness rejection of claim 4 in that the claimed doping concentration relationship among the relevant regions is present in the combined device. The interpretation at issue is not reconciled with the interpretation of claim 3, however, since the subject matter of claim 3 has been determined allowable aside from the rejected base claim. The Office maintains the obviousness rejection of present claims 1 and 18.
On pages 11-12 of applicant’s response, applicant alleges that the simple substitution rationale provided previously for the combination of Giacomini and Horinouchi is insufficient to justify combination. In support, applicant argues that neither Giacomini nor Horinouchi suggests a doping gradient that is both horizontal and vertical and that the level of experimentation suggested by Giacomini to arrive at an optimized doping profile and geometry could not be characterized as simple. Applicant also argues that implementing the proposed doping gradient into the JFET device of Giacomini would require technical engineering that would go beyond simple substitution.
Examiner finds applicant’s argument regarding the impropriety of the previous simple substitution rationale persuasive. Thus, examiner has withdrawn that motivation to combine the teachings of Horinouchi to the disclosure of Giacomini from the current rejection. However, the present rejection still relies on Horinouchi’s suggestion that incorporating a decreasing doping gradient within the channel implant of the device of Giacomini would increase the cutoff frequency and improve the maximum available power gain of the JFET device. It is well within PHOSITA’s technical ability to implement the horizontal doping gradient of Horinouchi into the JFET device of Giacomini to achieve this improvement, Therefore, the obviousness rejections of claim 1 and 18 are maintained.
On page 12 of applicant’s response, applicant alleges that the combination of Giacomini and Horinouchi does not yield predictable results as set forth in the previous Office Action. Applicant supports this allegation by arguing that “[t]he lateral depletion width is not a simple function of local doping; it is constrained by the vertical field component arising from the gate overhang” and that the effect of the depletion limiter region not being fully depleted at reasonable operating voltages is speculation rather than a disclosed teaching. Applicant acknowledges that Horinouchi’s suggestion that the decreasing doping gradient would optimize cutoff frequency and power gain does appear to impart an advantage to the JFET device of Giacomini but calls into question whether said advantage would justify other technical modifications that applicant asserts that the doping gradient modification would require.
Examiner finds applicant’s argument regarding the impropriety of the previous determination of predictable results persuasive. Thus, examiner has withdrawn the “simple substitution” motivation to combine the teachings of Horinouchi to the disclosure of Giacomini from the current rejection. As for applicant’s argument that it is speculation to assume that the depletion limiter region in the combined device of Giacomini and Horinouchi would predictably limit lateral depletion, examiner disagrees to some extent. Examiner has withdrawn the motivation to combine relying on simple substitution leading to predictable result because examiner agrees that implementing the decreasing doping gradient of Horinouchi into the JFET device of Giacomini cannot be characterized as a simple substitution leading to a predictable result. Yet, the predictable result that examiner was referring to in the “simple substitution” motivation to combine was the device improvement suggested by Horinouchi (i.e. increased cutoff frequency and improved power gain), not the claimed effect of the depletion limiter region which may or may not be predictable. In any case, applicant’s argument that it is speculation to assert that the depletion limiter region would accomplish the claimed effect in the combined device bears no weight when considering the patentability of the claimed invention.
See MPEP 2112.01 (I): “[w]here the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977)”. Examiner maintains that the claimed structure is present within the combined device of Giacomini and Horinouchi, and, therefore, a prima facie case of obviousness is established.
Aside from the previous determination of simple substitution leading to a predictable result, the present obviousness rejection still relies on Horinouchi’s suggestion that incorporating a decreasing doping gradient within the channel implant of the device of Giacomini would increase the cutoff frequency and improve the maximum available power gain of the JFET device. While this modification might require other technical modifications to the device design, current obviousness doctrine only requires that there be some suggestion that would lead PHOSITA to make the modification and a reasonable expectation of success in doing so (see MPEP 2143(I)(G)). This suggestion to combine comes from Horinouchi as shown in the present Office Action and acknowledged by applicant. PHOSITA certainly has the technical prowess necessary to enact the combination as can be seen in the current state of the art of semiconductor devices (PHOSITA is certainly capable of altering and experimenting with doping concentration as can be shown in Giacomini); with such technical prowess, there is a reasonable expectation of success in enacting the combination to increase the cutoff frequency and improve power gain. The present obviousness rejection of claims 1 and 18 is maintained.
On pages 13-14 of applicant’s response, applicant argues that the Office’s prevailing obviousness rejections utilizing Giacomini and Horinouchi rely improperly on hindsight reconstruction using applicant’s disclosure and claim language. In support, applicant argues that “the path from the references to the claimed structure becomes apparent only after the claim language is known. This suggests hindsight reconstruction”. Applicant also asserts that “the ability to define a region after viewing the combined structure does not demonstrate that the references teach or suggest that region”.
See MPEP 2145(X)(A): “’[a]ny judgment on obviousness is in a sense necessarily a reconstruction based on hindsight reasoning, but so long as it takes into account only knowledge which was within the level of ordinary skill in the art at the time the claimed invention was made and does not include knowledge gleaned only from applicant’s disclosure, such a reconstruction is proper.’ In re McLaughlin, 443 F.2d 1392, 1395, 170 USPQ 209, 212 (CCPA 1971)”.
Examiner finds applicant’s argument of improper hindsight reasoning unpersuasive. The examiner’s interpretation of the combined device of Giacomini and Horinouchi is consistent with the present specification which discloses that the only physical distinction between the relevant regions of the JFET device is doping concentration (along with any structural distinction that would come with changing the underlying semiconductor material’s doping concentration, yet said structural distinction would also be present in the combined device of Giacomini and Horinouchi). In one sense, the distinctness of “regions” within monolithically-formed planar semiconductor devices lies in the difference in doping concentration (and any structural differences in crystalline semiconductor structure the result from doping) among the “regions”. The combined device employs the decreasing doping gradient of Horinouchi which creates various “regions” having distinct (average) doping concentrations. These “regions” (namely the channel region and the depletion limiter region) read on the present claims under broadest reasonable interpretation doctrine (see MPEP 2111). Any “hindsight reasoning” that was used to arrive at this determination only takes into account knowledge available to one having ordinary skill in the art at the time that the present application was filed.
In light of the Office’s position with regard to applicant’s arguments set forth above, examiner determines that applicant’s arguments concerning the combination of Giacomini and Horinouchi failing to disclose or suggest all of the limitations of claims 1 and 18 and concerning the present obviousness rejection not satisfying the requirements for prima facie obviousness under 35 U.S.C. 103 are unpersuasive. The present obviousness rejections of claims 1 and 18 are maintained in this Office Action.
On page 14 of applicant’s response, applicant calls into question the previous obviousness rejections of claims 3 and 20 by pointing out that (1) the teachings of Kitabatake are inconsistent with the combination of Giacomini and Horinouchi and (2) it is unclear how the overall combination justifies the previous obviousness rejections.
Examiner finds applicant’s arguments regarding the obviousness rejections of claims 3 and 20 generally persuasive. After reviewing these arguments and reconsidering the prior art, examiner determines that the subject matter of dependent claims 3 and 20 is allowable except for the respective independent base claims which are still subject to obviousness rejections under 35 U.S.C. 103 (see the above discussion of allowable subject matter).
On pages 14-15 of applicant’s response, applicant alleges that the teachings of Asano and Disney fail to cure the above-identified deficiencies of Giacomini and Horinouchi in claims 7 and 8, respectively.
Examiner disagrees with the deficiencies that applicant has identified in the combined device of Giacomini and Horinouchi for the above-mentioned reasons. The obviousness rejections of claims 7 and 8 are maintained in the present Office Action.
On page 15 of applicant’s response, applicant alleges that the teachings of Fisher fail to cure the above-identified deficiencies of Giacomini and Horinouchi in claims 10-12 and 22-24.
Examiner disagrees with the deficiencies that applicant has identified in the combined device of Giacomini and Horinouchi for the above-mentioned reasons. The obviousness rejections of claims 10-12 and 22-24 are maintained in the present Office Action.
On page 15 of applicant’s response, applicant alleges that the teachings of Asano, Disney, Boos, and Yoshimitsu fail to cure the deficiencies of Giacomini and Horinouchi for claims 14-17.
Examiner disagrees with the deficiencies that applicant has identified in the combined device of Giacomini and Horinouchi for the above-mentioned reasons. The obviousness rejections of claims 14-17 are maintained in the present Office Action.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAMNER F COLLINS whose telephone number is (571)272-5187. The examiner can normally be reached M-F, 8am-5pm.
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/HAMNER FITZHUGH COLLINS IV/Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
Prosecution Insights