Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1, 12 and 21 have been amended, claims 5 and 15-20 have been canceled, and new claim 27 has been added. Currently, claims 1-5, 6-14 and 21-27 are pending.
DETAILED ACTION
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 12-14 and 21-26 are rejected under 35 U.S.C. 103 as being unpatentable over More et al. (Pub. No. US 2021/0408001 A1, herein More) in view of Tiwari et al. (Pub. No. US 2021/0408282 A1, herein Tiwari).
Regarding claim 12, More discloses a method comprising: forming a first semiconductor region NFET and a second semiconductor region PFET; forming an interfacial layer 81 comprising: a first portion on the first semiconductor region; and a second portion on the second semiconductor region (More: Figs. 1A-3F, 5B and paragraphs [0023], [0068]); depositing a dipole film 82 comprising: a first portion on the first portion of the interfacial layer; and a second portion on the second portion of the interfacial layer (More: Figs. 1A-3F, 5B-6B and paragraphs [0054], [0076]-[0077]); removing the second portion of the dipole film to reveal the second portion of the interfacial layer (More: Figs. 7A-7I and paragraphs [0072]-[0077]); depositing a high-k dielectric layer 282 comprising: a first portion on the first portion of the dipole film; and a second portion on the second portion of the interfacial layer; and depositing a work-function layer 86 on the high-k dielectric layer (More: Figs. 7A-7I and paragraphs [0023], [0061], [0073]-[0075]).
More does not specifically show depositing a high-k dielectric layer over the first portion of the dipole film, wherein the high-k dielectric layer comprises a material selected from the group consisting of hafnium oxide, zirconium oxide, or combination thereof.
However, in the same field of endeavor, Tiwari teaches a field effect transistor having a gate dielectric with a dipole layer and having a gate stressor layer, comprising: depositing a high-k dielectric layer over the first portion of the dipole film, wherein the high-k dielectric layer comprises a material selected from the group consisting of hafnium oxide, zirconium oxide, or combination thereof (Tiwari: paragraphs [0043]-[0044] and claim 1) to tune the threshold voltage and thus provide a multi-threshold voltage solution for scaled logic transistor (Tiwari: paragraph [0047]).
Therefore, given the teachings of Tiwari, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying More in view of Tiwari by employing distinct materials for the high-k dielectric layer and dipole film.
Regarding claim 13, More in view of Tiwari teaches the method of claim 12, further comprising forming an n-type source/drain region on a side of the first semiconductor region, wherein the dipole film comprises an n-type dipole dopant (More: Figs. 4A-4C and paragraphs [0023], [0073]-[0075]).
Regarding claim 14, More in view of Tiwari teaches the method of claim 12, further comprising forming a p-type source/drain region on a side of the first semiconductor region, wherein the dipole film comprises a p-type dipole dopant (More: Figs. 4A-4C and paragraphs [0023], [0073]-[0075]).
Regarding claim 21, More discloses a method comprising: forming a first gate stack NFET comprising: forming a first interfacial layer 81 on a first semiconductor region (More: Figs. 1A-3F and paragraph [0023]); depositing a dipole film 82 on the first interfacial layer; depositing a first high-k dielectric layer 282 on the dipole film; depositing a first work-function layer 86 on the first high-k dielectric layer; and forming a first filling metal region 87/89 over the first work-function layer (More: Figs. 7A-7I and paragraphs [0023], [0061], [0073]-[0075]); and forming a second gate stack PFET comprising: forming a second interfacial layer 81 on a second semiconductor region; depositing a second high-k dielectric layer 282 over and in contact with the second interfacial layer; depositing a second work-function layer 86 on the second high-k dielectric layer; and forming a second filling metal region 87/89 over the second work-function layer, wherein the first filling metal region and the second filling metal region are joined with each other and are formed of a same metallic material (More: Figs. 5B-7I and paragraphs [0023], [0061], [0073]-[0075]).
More does not specifically show after the dipole film is deposited, depositing a high-k dielectric layer on the dipole film, wherein the first and second high-k dielectric layers are free from dipole elements therein.
However, in the same field of endeavor, Tiwari teaches a field effect transistor having a gate dielectric with a dipole layer and having a gate stressor layer, comprising: depositing a high-k dielectric layer on the dipole film, wherein the dipole material layer 230A is distinct from the high-k dielectric layer 228 (Tiwari: paragraphs [0043]-[0044] and claim 1) to tune the threshold voltage and thus provide a multi-threshold voltage solution for scaled logic transistor (Tiwari: paragraph [0047]).
Therefore, given the teachings of Tiwari, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying More in view of Tiwari by employing distinct materials for the high-k dielectric layer and dipole film.
Regarding claim 22, More in view of Tiwari teaches the method of claim 21, wherein the first filling metal region and the second filling metal region are portions of a continuous and homogeneous metal region (More: Figs. 5B-7I and paragraphs [0023], [0061], [0073]-[0075]).
Regarding claim 23, More in view of Tiwari teaches the method of claim 21, wherein a peak concentration of a dipole dopant in the dipole film is at middle of the dipole film (More: paragraphs [0076]-[0077], [0079]).
Regarding claim 24, More in view of Tiwari teaches the method of claim 21, wherein the first work-function layer is a p-type work- function layer, and the dipole film comprises an n-type dipole dopant (More: Figs. 4A-4C and paragraphs [0023], [0073]-[0075]).
Regarding claim 25, More in view of Tiwari teaches the method of claim 21, wherein the first work-function layer is an n-type work- function layer, and the dipole film comprises a p-type dipole dopant (More: Figs. 4A-4C and paragraphs [0023], [0073]-[0075]).
Regarding claim 26, More in view of Tiwari teaches the method of claim 21 further comprising depositing a third high-k dielectric layer between the first work-function layer and the first high-k dielectric layer, wherein the first high-k dielectric layer is formed of a same material as the third high-k dielectric layer (More: Fig. 1A, and paragraph [0065]).
Regarding claim 27, More in view of Tiwari teaches the method of claim 21, wherein the first high-k dielectric layer and the second high-k dielectric layer comprise a material selected from the group consisting of hafnium oxide, zirconium oxide and combination thereof (Tiwari: paragraphs [0043]-[0044] and claim 1).
Allowable Subject Matter
Claims 1-4 and 6-11 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 1, the prior art of record alone or in combination do not teach or fairly suggest, in combination with other elements of the claim, further comprising: forming a second source/drain region based on a first portion of a second semiconductor region; forming a second interfacial layer based on a second portion of the second semiconductor region; forming a second dipole film on the second interfacial layer, wherein the first dipole film and the second dipole film are formed in a common deposition process; removing the second dipole film, wherein the first dipole film remains; depositing a second high-k dielectric layer on the second interfacial layer; and depositing a second work-function layer on the second high-k dielectric layer. Claims 2-4 and 6-11 are included likewise as they depend from claim 1.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant’s arguments with respect to claims 12-14 and 21-27 have been fully considered, but are found to be moot in view of the new grounds of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MALIHEH MALEK whose telephone number is (571)270-1874. The examiner can normally be reached M/T/W/R/F, 8:30-5.
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August 18, 2026
/MALIHEH MALEK/Primary Examiner, Art Unit 2813
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