DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 & 16-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bettencourt (US 7,852,136 B2).
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Regarding claim 1, Bettencourt (Fig. 2) discloses a biasing circuit for biasing an output transistor (transistor Q1) in a radio frequency (RF) amplifier, the biasing circuit comprising:
a first field-effect transistor (FET) (transistor Q2, Fig. 2) monolithically integrated with the output transistor (Col. 1, lines 56-58, integrated circuit), the first FET (transistor Q2) including a first source/drain connected to a first voltage source (reference potential ground, it noted that the transistor Q2 having analogous arrangement as the transistor MBIAS of the Fig. 3 of the application), a gate connected to a gate of the output transistor (transistor Q1), and a
second source/drain connected to a current source (resistor R1 connected to VDD) configured to supply a prescribed current to the first FET; and
a voltage divider (resistor R2 and R3 form as a voltage divider) coupled to the current source and configured to control a voltage at the gate of the first FET for setting a direct current (DC) quiescent current in the output transistor (transistor Q1).
Regarding claim 2, Bettencourt (Fig. 2) discloses wherein the voltage divider includes a first resistor (R2) connected between the second source/drain and the gate of the first FET (transistor Q2), and a second resistor (resistor R3) connected between the gate of the first FET and a second voltage source (reference potential at node n3).
Regarding claim 3, Bettencourt (Fig. 2) discloses wherein the first and second resistors (R2 and R3) are formed of the same material and are disposed proximate to one another.
Regarding claim 16, Bettencourt (Fig. 2) discloses wherein the first source/drain of the first FET is connected to a first source/drain of the output transistor (both source terminals of transistors Q2 & Q1 connected to common ground / both drain terminals of transistors Q2 and Q1 connected to same supply source VDD), such that the first FET (transistor Q2) and the output transistor (transistor Q1) are connected together in a current mirror configuration (Col. 3, lines 55-57, Q2 and Q1 are in a current mirror configuration).
Regarding claim 17, Bettencourt (Fig. 2) discloses a biasing circuit for biasing an output transistor (transistor Q1) in a radio frequency (RF) amplifier, the biasing circuit comprising:
a first field-effect transistor (FET) (transistor Q2) monolithically integrated (Col. 1, lines 56-58, integrated circuit), with the output transistor, the first FET being connected to the output transistor in a current mirror configuration (Col. 3, lines 55-57, Q2 and Q1 are in a current mirror configuration), such that a gate-to-source voltage of the first FET is the same as a gate-to-source voltage of the output transistor, and a drain current in the first FET (transistor Q2) is matched to a drain current in the output transistor (transistor Q1) and scaled proportionally according to a size of the first FET relative to a size of the output transistor; and
a voltage divider (resistors R2 and R3 forms a voltage divider) integrated with the first FET (transistor Q2) and connected to a current source (resistor R1 connected to VDD), the voltage divider (resistors R2 and R3) being configured to generate a voltage that is substantially independent of temperature variations for controlling the drain current in the first FET (transistor Q2).
Regarding claim 18, Bettencourt (Fig. 2) discloses wherein the first FET (transistor Q2) includes a first source/drain connected to a first voltage source (reference potential ground, it noted that the transistor Q2 having analogous arrangement as the transistor MBIAS of the Fig. 3 of the application), a gate connected to a gate of the output transistor (transistor Q1), and a second source/drain connected to the current source.
Regarding claim 19, Bettencourt (Fig. 2) discloses wherein the voltage divider includes a first resistor (resistor R2) connected between the second source/drain and the gate of the first FET (transistor Q2), and a second resistor (resistor R3) connected between the gate of the first FET and a second voltage source (reference potential at node 3).
Allowable Subject Matter
Claims 4-15, 21, 25, 29 & 31 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 33 is allowed.
Upon conclusion of a comprehensive search of the pertinent prior art, the Office indicates that the claims are allowable.
The prior art when taken alone, or, in combination, cannot be construed as reasonably teaching or suggesting all of the elements of the claimed invention as arranged, disposed, or provided in the manner as claimed by the Applicant. Added primarily for emphasis, the claim recitations “ an impedance presented to a gate of the output transistor by the biasing circuit is configured to be about 0 to 10 ohms per millimeter of gate width of the output transistor” in claim 33 is not found in the prior art of record.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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/KHIEM D NGUYEN/Examiner, Art Unit 2843