DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant's response to the Office Non-Final Action filed on 7/28/2026 is acknowledged.
Applicant amended claim 17; and cancelled claim 20.
Applicant added claim 21.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 17-19 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Su et al. (US 2021/0376076) (hereafter Su), in view of Lin et al. (US 2021/0242093) (hereafter Lin), in further view of Chanemougame et al. (US 2020/0035567) (hereafter Chanemougame).
Regarding claim 17, Su the discloses an integrated circuit device, comprising:
a plurality of first channel layers (88 on the left region of 50N in Fig. 29B, paragraph 0053) vertically spaced apart from each other;
a plurality of second channel layers (88 on the right region of 50P in Fig. 29B, paragraph 0053) vertically spaced apart from each other;
a shallow trench isolation (STI) structure (element number is not shown in Fig. 29B but see 84C in Fig. 14, paragraph 0044) disposed at a level lower than the first channel layers (88 on the left region of 50N in Fig. 29B) and the second channel layers (88 on the right region of 50P in Fig. 29B);
a first gate structure (122 and 124 in Fig. 29B, paragraph 0013) surrounding the first channel layers (88 on the left region of 50N in Fig. 29B) and the second channel layers (88 on the right region of 50P in Fig. 29B), wherein the first gate structure (122 and 124 in Fig. 29B) comprises a gate dielectric layer 122 (Fig. 29B, paragraph 0068) and a gate metal layer 124 (Fig. 29B, paragraph 0068) over the gate dielectric layer 122 (Fig. 29B);
a dielectric feature (element number is not shown in Fig. 29B but see 84A and 84B in Fig. 12, paragraph 0041) in the first gate structure (122 and 124 in Fig. 29B), wherein the dielectric feature (element number is not shown in Fig. 29B but see 84A and 84B in Fig. 12) is between the first channel layers (88 on the left region of 50N in Fig. 29B) and the second channel layers (88 on the right region of 50P in Fig. 29B), and the gate metal layer 124 (Fig. 29B) has a first portion below (see Fig. 29B, wherein a portion of 124 is located lower than the dielectric feature) the dielectric feature (element number is not shown in Fig. 29B but see 84A and 84B in Fig. 12), wherein the dielectric feature (element number is not shown in Fig. 29B but see 84A and 84B in Fig. 12) is embedded in a recessed region of the gate metal layer (122 and 124 in Fig. 29B) and has a bottom surface facing the STI structure (element number is not shown in Fig. 29B but see 84C in Fig. 14) and wrapped by the gate metal layer (122 and 124 in Fig. 29B).
Su does not disclose the bottom surface of the dielectric feature is separated from the STI structure by the first portion of the gate metal layer.
Lin discloses the bottom surface of the dielectric feature (34 and 38 in Fig. 28A, paragraph 0085) is separated from the STI structure 56 (Fig. 28A, paragraph 0094) by the first portion of the gate metal layer 94 (Fig. 28A, paragraph 0094).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Su to form the bottom surface of the dielectric feature is separated from the STI structure by the first portion of the gate metal layer, as taught by Lin, since the dielectric material 38 (Lin, Fig. 26A, paragraph 0076) may provide isolation between adjacent FinFETs.
Su and Lin do not disclose the first portion of the gate metal layer is in contact with the bottom surface of the dielectric feature and electrically connects a portion of the gate metal layer surrounding the first channel layers to a portion of the gate metal layer surrounding the second channel layers.
Chanemougame discloses the first portion 210 (Fig. 20B, paragraph 0066) of the gate metal layer (210, 230, and 180 in Fig. 20B) is in contact with the bottom surface of the dielectric feature 160 (Fig. 20B, paragraph 0069) and electrically connects a portion 230 (Fig. 20B) of the gate metal layer surrounding the first channel layers (126 of 120N in Fig. 20B, paragraph 0047) to a portion 180 (Fig. 20B) of the gate metal layer surrounding the second channel layers (126 of 120P in Fig. 20B, paragraph 0047).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Su in view of Lin to form the first portion of the gate metal layer is in contact with the bottom surface of the dielectric feature and electrically connects a portion of the gate metal layer surrounding the first channel layers to a portion of the gate metal layer surrounding the second channel layers, as taught by Chanemougame, since second metal 210 (Chanemougame, Fig. 20B, paragraph 0066) extends over isolation pillar 160 (Chanemougame, Fig. 20B, paragraph 0066) and active nanostructures 120N, 120P (Chanemougame, Fig. 20B, paragraph 0066) to electrically connect gate 246 (Chanemougame, Fig. 20B, paragraph 0066) for PFET 222 (Chanemougame, Fig. 20B, paragraph 0066) and gate 242 (Chanemougame, Fig. 20B, paragraph 0066) for NFET 224 (Chanemougame, Fig. 20B, paragraph 0066) together.
Regarding claim 18, Su further discloses the integrated circuit device of claim 17, wherein the dielectric feature (element number is not shown in Fig. 29B but see 84A and 84B in Fig. 12) is spaced apart from the first channel layers (88 on the left region of 50N in Fig. 29B) by a second portion (portion of 124 between the dielectric feature (element number is not shown in Fig. 29B but see 84A and 84B in Fig. 12) and the first channel layers (88 on the left region of 50N in Fig. 29B)) of the gate metal layer (122 and 124 in Fig. 29B) and spaced apart from the second channel layers (88 on the right region of 50P in Fig. 29B) by a third portion (portion of 124 between the dielectric feature (element number is not shown in Fig. 29B but see 84A and 84B in Fig. 12) and the second channel layers (88 on the right region of 50P in Fig. 29B)) of the gate metal layer (122 and 124 in Fig. 29B), the second portion (portion of 124 between the dielectric feature (element number is not shown in Fig. 29B but see 84A and 84B in Fig. 12) and the first channel layers (88 on the left region of 50N in Fig. 29B)) of the gate metal layer 124 (Fig. 29B) comprises a first-type work function metal layer (see “work function tuning layers” in paragraph 0074; and see paragraph 0014, wherein “The n-type region 50N includes n-type devices, such as NMOS transistors, e.g., n-type nano-FETs” such that 124 of 50N has work n-type function tuning layers), and the third portion (portion of 124 between the dielectric feature (element number is not shown in Fig. 29B but see 84A and 84B in Fig. 12) and the second channel layers (88 on the right region of 50P in Fig. 29B)) of the gate metal layer (122 and 124 in Fig. 29B) comprises a second-type work function metal layer (see “work function tuning layers” in paragraph 0074; and see paragraph 0014, wherein “the p-type region 50P includes p-type devices, such as PMOS transistors, e.g., p-type nano-FETs” such that 124 of 50P has work p-type function tuning layers) different from the first-type work function metal layer.
Regarding claim 19, Su (utilized different elements for first channel layers, second channel layers, and a first gate structure as applied in claim 17 in the above) discloses an integrated circuit device, comprising:
a plurality of first channel layers (88 on the right region of 50N in Fig. 29B, paragraph 0053) vertically spaced apart from each other;
a plurality of second channel layers (88 on the right region of 50P in Fig. 29B, paragraph 0053) vertically spaced apart from each other;
a shallow trench isolation (STI) structure (element number is not shown in Fig. 29B but see 84C in Fig. 14, paragraph 0044) disposed at a level lower than the first channel layers (88 on the right region of 50N in Fig. 29B) and the second channel layers (88 on the right region of 50P in Fig. 29B);
a first gate structure (122 and 124 in Fig. 29B, paragraph 0013) surrounding the first channel layers (88 on the right region of 50N in Fig. 29B) and the second channel layers (88 on the right region of 50P in Fig. 29B), wherein the first gate structure (122 and 124 in Fig. 29B) comprises a gate dielectric layer 122 (Fig. 29B, paragraph 0068) and a gate metal layer 124 (Fig. 29B, paragraph 0068) over the gate dielectric layer 122 (Fig. 29B); and
a dielectric feature (element number is not shown in Fig. 29B but see 84A and 84B in Fig. 12, paragraph 0041) in the first gate structure (122 and 124 in Fig. 29B), wherein the dielectric feature (element number is not shown in Fig. 29B but see 84A and 84B in Fig. 12) is between the first channel layers (88 on the right region of 50N in Fig. 29B) and the second channel layers (88 on the right region of 5PN in Fig. 29B), and the gate metal layer 124 (Fig. 29B) has a first portion below (see Fig. 29B, wherein a portion of 124 of 50N is located lower than the dielectric feature) the dielectric feature (element number is not shown in Fig. 29B but see 84A and 84B in Fig. 12), wherein the dielectric feature (element number is not shown in Fig. 29B but see 84A and 84B in Fig. 12) is embedded in a recessed region of the gate metal layer 124 (Fig. 29B) and has a bottom surface facing the STI structure (element number is not shown in Fig. 29B but see 84C in Fig. 14) and wrapped by the gate metal layer 124 (Fig. 29B); and
wherein a plurality of third channel layers (88 on the left region of 50N in Fig. 29B) vertically spaced apart from each other, wherein the first channel layers (88 on the right region of 50N in Fig. 29B) is between the second channel layers (88 on the left region of 50P in Fig. 29B) and the third channel layers (88 on the left region of 50N in Fig. 29B);
a second gate structure (122 and 124 of left region of 50N in Fig. 29B, paragraph 0013) surrounding the third channel layers (88 on the left region of 50N in Fig. 29B); and a dielectric wall 68 (Fig. 29B, paragraph 0102) spacing the first gate structure (122 and 124 of right region of 50P in Fig. 29B) apart from the second gate structure (122 and 124 of left region of 50N in Fig. 29B).
Su does not disclose the bottom surface of the dielectric feature is separated from the STI structure by the first portion of the gate metal layer.
Lin discloses the bottom surface of the dielectric feature (34 and 38 in Fig. 28A, paragraph 0085) is separated from the STI structure 56 (Fig. 28A, paragraph 0094) by the first portion of the gate metal layer 94 (Fig. 28A, paragraph 0094).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Su to form the bottom surface of the dielectric feature is separated from the STI structure by the first portion of the gate metal layer, as taught by Lin, since the dielectric material 38 (Lin, Fig. 26A, paragraph 0076) may provide isolation between adjacent FinFETs.
Su and Lin do not disclose the first portion of the gate metal layer is in contact with the bottom surface of the dielectric feature and electrically connects a portion of the gate metal layer surrounding the first channel layers to a portion of the gate metal layer surrounding the second channel layers.
Chanemougame discloses the first portion 210 (Fig. 20B, paragraph 0066) of the gate metal layer (210, 230, and 180 in Fig. 20B) is in contact with the bottom surface of the dielectric feature 160 (Fig. 20B, paragraph 0069) and electrically connects a portion 230 (Fig. 20B) of the gate metal layer surrounding the first channel layers (126 of 120N in Fig. 20B, paragraph 0047) to a portion 180 (Fig. 20B) of the gate metal layer surrounding the second channel layers (126 of 120P in Fig. 20B, paragraph 0047).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Su in view of Lin to form the first portion of the gate metal layer is in contact with the bottom surface of the dielectric feature and electrically connects a portion of the gate metal layer surrounding the first channel layers to a portion of the gate metal layer surrounding the second channel layers, as taught by Chanemougame, since second metal 210 (Chanemougame, Fig. 20B, paragraph 0066) extends over isolation pillar 160 (Chanemougame, Fig. 20B, paragraph 0066) and active nanostructures 120N, 120P (Chanemougame, Fig. 20B, paragraph 0066) to electrically connect gate 246 (Chanemougame, Fig. 20B, paragraph 0066) for PFET 222 (Chanemougame, Fig. 20B, paragraph 0066) and gate 242 (Chanemougame, Fig. 20B, paragraph 0066) for NFET 224 (Chanemougame, Fig. 20B, paragraph 0066) together.
Regarding claim 21, Su in view of Lin and Chanemougame discloses the integrated circuit device of claim 18, however Su and Lin do not disclose the bottom surface of the dielectric feature is in contact with the first-type work function metal layer and the second-type work function metal layer.
Chanemougame discloses the bottom surface of the dielectric feature 160 (Fig. 20B, paragraph 0069) is in contact with the first-type work function metal layer 210 (Fig. 20B, paragraph 0066, wherein “NFET work function metal”) and the second-type work function metal layer 180 (Fig. 20B, paragraph 0062, wherein “PFET WFM“).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Su in view of Lin to form the bottom surface of the dielectric feature is in contact with the first-type work function metal layer and the second-type work function metal layer, as taught by Chanemougame, since second metal 210 (Chanemougame, Fig. 20B, paragraph 0066) extends over isolation pillar 160 (Chanemougame, Fig. 20B, paragraph 0066) and active nanostructures 120N, 120P (Chanemougame, Fig. 20B, paragraph 0066) to electrically connect gate 246 (Chanemougame, Fig. 20B, paragraph 0066) for PFET 222 (Chanemougame, Fig. 20B, paragraph 0066) and gate 242 (Chanemougame, Fig. 20B, paragraph 0066) for NFET 224 (Chanemougame, Fig. 20B, paragraph 0066) together.
Allowable Subject Matter
Claims 1-16 are allowed. The following is an examiner’s statement of reasons for allowance: a closest prior art, You et al. (US 20220045051), discloses depositing a gate metal layer 266 (Fig. 16, paragraph 0032) over the gate dielectric layer 264 (Fig. 16); and etching (see Fig. 19 and paragraph 0036) a recess 274 (Fig. 19, paragraph 0036) in the gate metal layer 266 (Fig. 19) and between the first set (left 2080 in Fig. 19) of the second semiconductor layers and the second set (right 2080 in Fig. 19) of the second semiconductor layers but fails to disclose the gate metal layer has a first portion below the recess. Additionally, the prior art does not teach or suggest a method for manufacturing an integrated circuit device, comprising: the gate metal layer has a first portion below the recess in combination with other elements of claim 1.
In addition, a closest prior art, You et al. (US 20220045051), discloses removing (see Fig. 14 and paragraph 0030) a first portion of the dummy gate electrode 230 (Fig. 13) and a first portion of the dummy gate dielectric layer 228 (Fig. 13) to expose a first side (upper side of 206 and 208 in Fig. 14) of the semiconductor fin (206 and 208 in Fig. 14); and removing (see Fig. 15 and paragraph 0031) the first semiconductor layers 206 (Fig. 14) in the semiconductor fin (206 and 208 in Fig. 14), while leaving the second semiconductor layers 2080 (Fig. 15) but fails to teach a second side of the semiconductor fin is covered by a second portion of the dummy gate dielectric layer; wherein ends of the second semiconductor layers adjoins the second portion of the dummy gate dielectric layer; and after removing the first semiconductor layers in the semiconductor fin, trimming the second portion of the dummy gate dielectric layer. Additionally, the prior art does not teach or suggest a method for manufacturing an integrated circuit device, comprising: a second side of the semiconductor fin is covered by a second portion of the dummy gate dielectric layer; wherein ends of the second semiconductor layers adjoins the second portion of the dummy gate dielectric layer; and after removing the first semiconductor layers in the semiconductor fin, trimming the second portion of the dummy gate dielectric layer in combination with other elements of claim 10.
A closest prior art, You et al. (US 20220045051), discloses a method for manufacturing an integrated circuit device, comprising: depositing an epitaxial stack 204 (Fig. 2, paragraph 0015) over a semiconductor substrate 202 (Fig. 2, paragraph 0015), wherein the epitaxial stack 204 (Fig. 2) comprises a plurality of first 206 (Fig. 2, paragraph 0016) and second semiconductor layers 208 (Fig. 2, paragraph 0016) alternatively arranged over the semiconductor substrate 202 (Fig. 2); patterning (see Fig. 3 and paragraph 0018) the epitaxial stack 204 (Fig. 2) to form a first semiconductor fin (left 212 in Fig. 3, paragraph 0018) and a second semiconductor fin (right 212 in Fig. 3, paragraph 0018); removing (see Fig. 15 and paragraph 0031) the first semiconductor layers 206 (Fig. 14) in the first (left 206 and left 208 in Fig. 14) and second semiconductor fins (right 206 and right 208 in Fig. 14), while leaving a first set (left 2080 in Fig. 15, paragraph 0031) of the second semiconductor layers (left 208 in Fig. 14) in the first semiconductor fin (left 206 and left 208 in Fig. 14) and a second set (right 2080 in Fig. 15, paragraph 0031) of the second semiconductor layers (right 208 in Fig. 14) in the second semiconductor fin (right 206 and right 208 in Fig. 14); forming a gate dielectric layer 264 (Fig. 16, paragraph 0032) around the first (left 2080 in Fig. 16) and second sets (right 2080 in Fig. 16) of the second semiconductor layers; depositing a gate metal layer 266 (Fig. 16, paragraph 0032) over the gate dielectric layer 264 (Fig. 16); etching (see Fig. 19 and paragraph 0036) a recess 274 (Fig. 19, paragraph 0036) in the gate metal layer 266 (Fig. 19) and between the first set (left 2080 in Fig. 19) of the second semiconductor layers and the second set (right 2080 in Fig. 19) of the second semiconductor layers; and forming a dielectric feature 280 (Fig. 20, paragraph 0046) in the recess 274 (Fig. 19) of the gate metal layer 266 (Fig. 19) but fails to teach the gate metal layer has a first portion below the recess as the context of claim 1. The other allowed claims each depend from one of these claims, and each is allowable for the same reasons as the claim from which it depends. Claims 2-9 depend on claim 1.
In addition, a closest prior art, You et al. (US 20220045051), discloses a method for manufacturing an integrated circuit device, comprising: depositing an epitaxial stack 204 (Fig. 2, paragraph 0015) over a semiconductor substrate 202 (Fig. 2, paragraph 0015), wherein the epitaxial stack 204 (Fig. 2) comprises a plurality of first 206 (Fig. 2, paragraph 0016) and second semiconductor layers 208 (Fig. 2, paragraph 0016) alternatively arranged over the semiconductor substrate 202 (Fig. 2); patterning (see Fig. 3 and paragraph 0018) the epitaxial stack 204 (Fig. 2) to form a semiconductor fin 212 (Fig. 3, paragraph 0018); forming a dummy gate structure (228 and 230 in Fig. 10, paragraph 0024) over the semiconductor fin (element number is not shown in Fig. 10 but see 212 in Fig. 5), wherein the dummy gate structure (228 and 230 in Fig. 10) comprises a dummy gate dielectric layer 228 (Fig. 10, paragraph 0024) and a dummy gate electrode 230 (Fig. 10, paragraph 0024) over the dummy gate dielectric layer 228 (Fig. 10); removing (see Fig. 14 and paragraph 0030) a first portion of the dummy gate electrode 230 (Fig. 13) and a first portion of the dummy gate dielectric layer 228 (Fig. 13) to expose a first side (upper side of 206 and 208 in Fig. 14) of the semiconductor fin (206 and 208 in Fig. 14); removing (see Fig. 15 and paragraph 0031) the first semiconductor layers 206 (Fig. 14) in the semiconductor fin (206 and 208 in Fig. 14), while leaving the second semiconductor layers 2080 (Fig. 15); and forming a high-k/metal gate structure (264 and 266 in Fig. 16, paragraph 0032) around the second semiconductor layers 2080 (Fig. 16) but fails to teach a second side of the semiconductor fin is covered by a second portion of the dummy gate dielectric layer; wherein ends of the second semiconductor layers adjoins the second portion of the dummy gate dielectric layer; and after removing the first semiconductor layers in the semiconductor fin, trimming the second portion of the dummy gate dielectric layer as the context of claim 10. The other allowed claims each depend from one of these claims, and each is allowable for the same reasons as the claim from which it depends. Claims 11-16 depend on claim 10.
Response to Arguments
1. Applicant's arguments filed 7/28/2026 have been fully considered.
2. Applicant's arguments with respect to claims 17-20 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/ Supervisory Patent Examiner, Art Unit 2813
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