Prosecution Insights
Last updated: May 29, 2026
Application No. 18/358,525

INTERCONNECT STRUCTURE AND FABRICATION METHOD THEREOF

Final Rejection §103
Filed
Jul 25, 2023
Examiner
LUKE, DANIEL M
Art Unit
2896
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Company Ltd.
OA Round
2 (Final)
71%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
90%
With Interview

Examiner Intelligence

Grants 71% — above average
71%
Career Allowance Rate
487 granted / 688 resolved
+2.8% vs TC avg
Strong +20% interview lift
Without
With
+19.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
19 currently pending
Career history
719
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
81.1%
+41.1% vs TC avg
§102
10.5%
-29.5% vs TC avg
§112
7.3%
-32.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 688 resolved cases

Office Action

§103
DETAILED ACTION This office action is in response to the amendment filed 1/21/2026. Currently, claims 1-6, 8-17 and 21-24 are pending. Drawings The drawings were received on 1/21/2026. These drawings are acceptable. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 21, 23 and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Hsueh et al. (US 2021/0287994) in view of Lanzillo et al. (US 2023/0144842). Pertaining to claim 21, Hsueh shows, with reference to FIG. 7-15 and 3A, a method, comprising: depositing a first dielectric layer (104a) over a substrate (102); forming a first conductive feature (106) in the first dielectric layer; depositing a first conductive capping layer (112) over the first conductive feature; depositing an etch stop layer (105) over the first conductive capping layer; depositing a second dielectric layer (104b) over the etch stop layer; etching through the second dielectric layer and the etch stop layer to form an opening exposing a top surface of the first conductive capping layer (FIG. 9); depositing an inhibitor film (1002) on the top surface of the first conductive capping layer; depositing a barrier layer (118) on sidewalls of the opening; after the depositing of the barrier layer, removing the inhibitor film (FIG. 12); depositing a liner (122) on the barrier layer and the top surface of the first conductive capping layer (para. [0062] – [0063]); depositing a seed layer (para. [0064]) on the liner; and depositing a conductive filling layer (120) in the opening and over the seed layer. Hsueh fails to show the step of depositing a second conductive capping layer over the conductive filling layer, wherein the top surface of the barrier layer and the top surface of the second conductive capping layer are coplanar. However, Lanzillo teaches in FIG. 5D that, for a similar interconnect structure, a conductive capping layer 536 is formed over the filling layer 420 such that the top surface of the barrier layer 412 and the top surface of the conductive capping layer are coplanar. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Hsueh to include a step of forming a conductive capping layer over the conductive filling layer, as taught by Lanzillo, with the motivation that the cap prevents electromigration of the conductive fill material into surrounding materials (para. [0036]). Pertaining to claim 23, in the case that the step of depositing second barrier layer 310 is omitted as described in para. [0062], liner 122 would instead occupy the space occupied by barrier layer 310 in FIG. 13, including a portion that separates the barrier layer 118 from contacting the first conductive capping layer 112. Pertaining to claim 24, Lanzillo teaches, prior to the depositing of the second conductive capping layer, recessing a top surface of the conductive filling layer below the top surface of the barrier layer (para. [0059], FIG. 5A). Allowable Subject Matter Claims 1-6 and 8-17 are allowed. Claim 22 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: With regards to claim 1 and claims dependent thereon, Applicant’s arguments filed 1/21/2026 are persuasive. With regards to claims 12-17 and 22, refer to the previous office action. Response to Arguments Applicant’s arguments with regards to claim 1 is found persuasive, as indicated above. With regards to claim 21, Applicant’s arguments have been considered but are moot because the new ground of rejection does not rely on Hsueh to teach the second conductive capping layer. Rather, this is taught by Lanzillo as discussed in the rejections above. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL M LUKE whose telephone number is (571)270-1569. The examiner can normally be reached Monday-Friday, 9am-5pm, EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Kraig can be reached at (571) 272-8660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DANIEL LUKE/Primary Examiner, Art Unit 2896
Read full office action

Prosecution Timeline

Jul 25, 2023
Application Filed
Oct 21, 2025
Non-Final Rejection mailed — §103
Jan 21, 2026
Response Filed
Mar 02, 2026
Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12642079
INTERCONNECT FEATURE CONTACTED WITHIN A RECESS
4y 2m to grant Granted May 26, 2026
Patent 12635503
GRAPHENE COATED INTERCONNECTS WITH AIRGAP STRUCTURES
3y 4m to grant Granted May 19, 2026
Patent 12622248
Interconnects with Sidewall Barrier Layer Divot Fill
3y 4m to grant Granted May 05, 2026
Patent 12622244
SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE
2y 8m to grant Granted May 05, 2026
Patent 12615783
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
3y 2m to grant Granted Apr 28, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
71%
Grant Probability
90%
With Interview (+19.7%)
2y 9m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 688 resolved cases by this examiner. Grant probability derived from career allowance rate.

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