DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Invention I, Species A in the reply filed on 12/23/2025 is acknowledged. The traversal is on the ground(s) that there will be no “serious search and/or examination burden on the examiner if restriction was not required”. Examiner disagrees. As previously presented in the Requirement for Restriction/Election mailed on 10/28/2005, in sections 4-5, for many reasons there is a serious search and/or examination burden if restriction were not required.
Thus, the requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 6, 10-14, 17, 20, 24, 34 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kwon et al. (US 2012/0299197 A1 hereinafter referred to as “Kwon”).
With respect to claim 1, Kwon discloses, in Figs.1-16, a semiconductor package, comprising: a submount (10); and a semiconductor die (20) on the submount (10), wherein the submount (10) defines a base plane, wherein the submount comprises at least one stud protrusion (14/24, 12/22) extending from the base plane (10) in a direction toward the semiconductor die (20) (see Par.[0044] wherein the package substrate 10 may have a top surface 10a and a bottom surface 10b opposite to the top surface 10a; a semiconductor chip 20 may be mounted on the top surface 10a of the package substrate 10 opposite to the bottom surface 10b; the semiconductor chip 20 may include a second central portion C2 and a second peripheral portion P2; see Figs.1-2, Par.[0046] wherein connection members 24/14 in P1/P2 regions are around connection members 12/22 in C1/C2 regions).
With respect to claim 3, Kwon discloses, in Figs.1-16, the semiconductor package, wherein the at least one stud protrusion (22, 24) has a planar surface/(planar surface of terminals16), the semiconductor die (20) being on the planar surface (16) of the at least one stud protrusion (22, 24) (see Par.[0044] wherein the package substrate 10 may include bismaleimide triazine resin, alumina type ceramic or glass type ceramic; upper terminals 16 and lower terminals 19 may be disposed on the top surface 10a and the bottom surface 10b of the package substrate 10, respectively).
With respect to claim 6, Kwon discloses, in Figs.1-16, the semiconductor package, wherein the planar surface of the at least one stud protrusion comprises a circular cross-section or a square cross-section (see Par.[0044] wherein the central portion of connection members may have a square shape, a circular shape or a cross shape in a plan view).
With respect to claim 10, Kwon discloses, in Figs.1-16, the semiconductor package, wherein the submount comprises a plurality of stud protrusions, the semiconductor package further comprising: at least one stud protrusion (22) of the plurality of stud protrusions in a center portion of the submount; and at least one stud protrusion of the plurality of stud protrusions (24) in a peripheral portion of the submount.
With respect to claim 11, Kwon discloses, in Figs.1-16, the semiconductor package, wherein the at least one stud protrusion comprises at least one punch-defined stud protrusion.
With respect to claim 12, Kwon discloses, in Figs.1-16, the semiconductor package, wherein the at least one stud protrusion is integral with the submount.
With respect to claim 13, Kwon discloses, in Figs.1-16, the semiconductor package, wherein the at least one stud protrusion has a height in a range of about 1 micron to about 20 microns (see Par.[0050] wherein the fusion conductive layer 9 of conductive member 22, 24 may have a thickness of about 10 .mu.m to about 30 .mu.m).
With respect to claim 14, Kwon discloses, in Figs.1-16, the semiconductor package, wherein the semiconductor package has a bond line thickness (BLT) that is substantially equal to a height of the at least one stud protrusion.
With respect to claim 17, Kwon discloses, in Figs.1-16, the semiconductor package, wherein the at least one stud protrusion comprises an annular stud protrusion.
With respect to claim 20, Kwon discloses, in Figs.1-16, the semiconductor package, further comprising a die-attach material (26) between at least a portion of the semiconductor die (20) and the submount, the die-attach material (26) at least partially filling a space between adjacent stud protrusions on the submount.
With respect to claim 24, Kwon discloses, in Figs.1-16, the semiconductor package, further comprising an electroless deposited material between at least a portion of the semiconductor die and the submount, the electroless deposited material at least partially filling a space between adjacent stud protrusions on the submount.
Moreover, regarding the limitation “an electroless deposited material”, it is submitted that such limitation does not further define the structure as instantly claimed, nor serve to distinguish over Kwon. Therefore, the said claimed limitation is a “product by process” limitation. Applicant attention is thereby directed to the fact that a "product by process" claim is directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al, 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or not. Note that applicant has the burden of proof in such cases, as the above case law make clear.
With respect to claim 34, Kwon discloses, in Figs.1-16, the semiconductor package, wherein the semiconductor die comprises a wide bandgap semiconductor device (see Par.[0021] wherein the semiconductor chip may be a silicon substrate, a GaAg substrate, a SiC substrate, or the like).
Claims 1, 3, 6, 10-12, 14, 17, 20, 28-30, 32, 35 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kasem et al. (US 2006/0110856 A1 hereinafter referred to as “Kasem”).
With respect to claim 1, Kasem discloses, in Figs.1A-14B, a semiconductor package, comprising: a submount (12); and a semiconductor die (14) on the submount (12), wherein the submount (12) defines a base plane, wherein the submount (12) comprises at least one stud protrusion (123, 121, 154) extending from the base plane in a direction toward the semiconductor die (see Par.[0046], [0049] wherein this first reflow causes the solder to flow into the valleys between and around the mesas 121 and 123, and die 14 settles downward towards source contact 126 and gate contact 128 laterally expansive solder layer between lower lead frame 12 and die 14 tends to impose a greater stress on the solder layer and the die; therefore, it is desirable to structure the die 14 as shown in FIG. 9, with segregated source and drain pads, each of which is surrounded by a passivation layer. FIG. 9 is a view of the front side of die 14).
With respect to claim 3, Kasem discloses, in Figs.1A-14B, the semiconductor package, wherein the at least one stud protrusion (154) has a planar surface, the semiconductor die (14) being on the planar surface of the at least one stud protrusion.
With respect to claim 6, Kasem discloses, in Figs.1A-14B, the semiconductor package, wherein the planar surface of the at least one stud protrusion (154) comprises a circular cross-section or a square cross-section.
With respect to claim 10, Kasem discloses, in Figs.1A-14B, the semiconductor package, wherein the submount comprises a plurality of stud protrusions, the semiconductor package further comprising: at least one stud protrusion of the plurality of stud protrusions in a center portion of the submount; and at least one stud protrusion of the plurality of stud protrusions in a peripheral portion of the submount.
With respect to claim 11, Kasem discloses, in Figs.1A-14B, the semiconductor package, wherein the at least one stud protrusion comprises at least one punch-defined stud protrusion.
With respect to claim 12, Kasem discloses, in Figs.1A-14B, the semiconductor package, wherein the at least one stud protrusion is integral with the submount.
With respect to claim 14, Kasem discloses, in Figs.1A-14B, the semiconductor package, wherein the semiconductor package has a bond line thickness (BLT) that is substantially equal to a height of the at least one stud protrusion.
With respect to claim 17, Kasem discloses, in Figs.1A-14B, the semiconductor package, wherein the at least one stud protrusion comprises an annular stud protrusion.
With respect to claim 20, Kasem discloses, in Figs.1A-14B, the semiconductor package, further comprising a die-attach material (18) between at least a portion of the semiconductor die (14) and the submount (12), the die- attach material at least partially filling a space between adjacent stud protrusions on the submount.
With respect to claim 28, Kasem discloses, in Figs.1A-14B, the semiconductor package, further comprising a conductive catalytic layer (16) (see Par.[0038] wherein the lower solder layer 18 is generally thicker than the upper solder layer 16. Therefore, lower solder layer 18 is more rugged and is better able to withstand differential lateral expansion between die 14 and the elements of lower lead frame 12).
With respect to claim 29, Kasem discloses, in Figs.1A-14B, the semiconductor package, wherein the conductive catalytic layer (16) is on the semiconductor die.
With respect to claim 30, Kasem discloses, in Figs.1A-14B, the semiconductor package, wherein the conductive catalytic layer (16) is on the submount (12).
With respect to claim 32, Kasem discloses, in Figs.1A-14B, the semiconductor package, wherein the submount comprises a lead frame.
With respect to claim 35, Kasem discloses, in Figs.1A-14B, the semiconductor package of claim, wherein the wide bandgap semiconductor device comprises a silicon carbide-based MOSFET, a silicon carbide-based Schottky diode, or a Group III nitride-based high electron mobility transistor (see Par.[0035] wherein the drain terminal on the top surface of die 14 is electrically and thermally connected to upper lead frame 10 by an upper solder layer 16, which as shown extends into groove 105 on the bottom surface of upper lead frame 10).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Kwon.
With respect to claim 4, Kwon discloses, the semiconductor package, wherein a surface area of the planar surface is less than of a surface area of the base plane defined by the submount.
Even though Kwon does not disclose a surface area of the planar surface is less than about 10% of a surface area of the base plane defined by the submount, the said range is predictable by simple engineering optimization motivated by a design choice, such as overall size of device. In cases like the present, where patentability is said to be based upon particular chosen dimensions or upon another variable recited within the claims, applicant must show that the chosen dimensions are critical. As such, the claimed dimensions appear to be an obvious matter of engineering design choice and thus, while being a difference, does not serve in any way to patentably distinguish the claimed invention from the applied prior art. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990); In re Kuhle, 526 F2d. 553,555,188 USPQ 7, 9 (CCPA 1975).
Citation of Pertinent Prior Art
The prior art made of record (e.g.; see PTO-892) and not relied upon is considered pertinent to applicant's disclosure.
Examiner’s Telephone/Fax Contacts
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOULOUCOULAYE INOUSSA whose telephone number is (571)272-0596. The examiner can normally be reached Monday-Friday (10-18).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JEFF W NATALINI can be reached at 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Mouloucoulaye Inoussa/ Primary Examiner, Art Unit 2818