Prosecution Insights
Last updated: April 19, 2026
Application No. 18/358,634

Integrated Circuits Having Protruding Interconnect Conductors

Non-Final OA §DP
Filed
Jul 25, 2023
Examiner
GEYER, SCOTT B
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Co., Ltd.
OA Round
1 (Non-Final)
94%
Grant Probability
Favorable
1-2
OA Rounds
2y 1m
To Grant
98%
With Interview

Examiner Intelligence

Grants 94% — above average
94%
Career Allow Rate
664 granted / 706 resolved
+26.1% vs TC avg
Minimal +4% lift
Without
With
+4.4%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 1m
Avg Prosecution
15 currently pending
Career history
721
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
21.1%
-18.9% vs TC avg
§102
42.4%
+2.4% vs TC avg
§112
24.2%
-15.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 706 resolved cases

Office Action

§DP
DETAILED ACTION Information Disclosure Statement The references cited within the IDS document (dated September 5, 2023) have been considered. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer. Claims 9 and 11 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 9 and 10 of U.S. Patent No. 11,728,397. Although the claims at issue are not identical, they are not patentably distinct from each other because all of the limitations of claims 9 and 11 are recited within claims 9 and 10 of the ‘397 patent. Specifically, as to claim 9 of the instant application, see claim 9 of the ‘397 patent; as to claim 11 of the instant application, see claims 9 and 10 of the ‘397 patent. Allowable Subject Matter Claims 1-8 and 16-20 are allowable. The following is an examiner’s statement of reasons for allowability. The prior art of record does not teach or suggest the disclosed invention regarding – A device comprising a first dielectric layer disposed on the gate structure, the first dielectric layer having a top surface extending to a first height above the substrate, the top surface of the first dielectric layer facing away from the substrate; a first contact feature extending through the first dielectric layer to electrically couple to the source/drain feature, the first contact feature extending to a second height above the substrate, the second height being greater than the first height; a first contact liner interfacing with the first contact feature and extending from the source/drain feature to the first height above the substrate; and a first etch stop layer interfacing with the top surface of the first dielectric layer, the first contact feature and the first contact liner, as recited within independent claim 1. Claims 2-8 depend from claim 1. A device comprising: a first dielectric layer disposed on the source/drain feature, the first dielectric layer extending to a first height above the substrate; a first etch stop layer disposed directly on the first dielectric layer; and a first contact extending through the first dielectric layer to the source/drain feature, wherein the first contact includes: a conductive fill extending to a second height above the substrate that is greater than the first height, wherein the conductive fill includes opposing sidewall surfaces and the first etch stop layer interfaces with at least one of the opposing sidewall surfaces of the conductive fill; and a first liner layer disposed on the conductive fill, the first liner layer extending to the first height above the substrate, as recited within claim 16. Claims 17-20 depend from claim 16. Claims 10, 12, and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. (Claims 14 and 15 are also objected to as being dependent upon an objected claim.) As to claim 10, the prior art of record does not teach or suggest the disclosed invention regarding a fin structure disposed on the substrate, wherein the source/drain feature is at least partially embedded within the fin structure. As to claim 12, the prior art of record does not teach or suggest the disclosed invention regarding the first liner layer and the second liner layer extend to a first height above the substrate, and wherein the conductive material layer extends to a second height above the substrate that is greater than the first height. As to claim 13, the prior art of record does not teach or suggest the disclosed invention regarding the sidewall of the first contact feature includes a first portion defined by the second liner layer and a second portion defined by the conductive material layer. Cited Prior Art The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: see the attached form PTO-892 for pertinent cited art. Contact Information Any inquiry concerning this communication or earlier communications from the examiner should be directed to Scott B. Geyer (telephone: 571-272-1958). The examiner can normally be reached on Monday to Friday, 10AM - 4PM (ET). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at: http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim (telephone: 571-272-8458). The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (in U.S.A. or Canada) or 571-272-1000. /SCOTT B GEYER/ Primary Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Jul 25, 2023
Application Filed
Feb 23, 2026
Non-Final Rejection — §DP (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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Patent 12593730
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2y 5m to grant Granted Mar 31, 2026
Patent 12593720
SEMICONDUCTOR DEVICE COMPRISING ELECTRODE TERMINALS COATED WITH AN INSULATING FILM HAVING A THICKNESS OF LESS THAN 100 MICRONS, METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE, AND POWER CONVERSION APPARATUS COMPRISING THE SEMICONDUCTOR DEVICE
2y 5m to grant Granted Mar 31, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
94%
Grant Probability
98%
With Interview (+4.4%)
2y 1m
Median Time to Grant
Low
PTA Risk
Based on 706 resolved cases by this examiner. Grant probability derived from career allow rate.

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