DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-17, 21-23 in the reply filed on 10/06/25 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-10, 21-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee(USPGPUB DOCUMENT: 2021/0090973, hereinafter Lee) in view of Lien (USPGPUB DOCUMENT: 2012/0234683, hereinafter Lien).
Re claim 1 Lee discloses a method of forming a semiconductor structure, comprising: forming a seed layer(S1) on a substrate[0011]; forming a photoresist layer(PR1/PR2) on the seed layer(S1), the photoresist layer(PR1/PR2) defining a first opening(OP1) and a second opening(OP2), the first opening(OP1) being wider than the second opening(OP2);performing an electroplating process[0012], thereby growing a bottom portion of a first metal line(100a) in the first opening(OP1) and a bottom portion of a second metal line(100b) in the second opening(OP2);continuing the electroplating process[0012], thereby growing a top portion of the first metal line(100a) and a top portion of the second metal line(100b); removing the photoresist layer(PR1/PR2) to expose a portion of the seed layer(S1); and removing the exposed portion of the seed layer(S1) (see Fig 1C).
Lee does not disclose performing an electroplating process[0012] with a first plating current; continuing the electroplating process[0012] with a second plating current that is larger than the first plating current,
Lien disclose performing an electroplating process with a first plating current[0010]; continuing the electroplating process with a second plating current that is larger than the first plating current[0026],
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Lien to the teachings of Lee in order to readily control growth of the electroplated film for bottom-up filling, and the superior electrical conductivity characteristics of the electroplated film [0002, Lien].
Re claim 2 Lee and Lien disclose the method of claim 1, wherein a width of the first metal line(100a) is larger than a width of the second metal line(100b), and a height of the first metal line(100a) is larger than a height of the second metal line(100b) for less than about 0.4 um.
Re claim 3 Lee and Lien disclose the method of claim 1, wherein the bottom portion of the first and second metal line(100b)s has a grain size[0002 of Lien] smaller than the top portion of the first and second metal line(100b)s.
Re claim 4 Lee and Lien disclose the method of claim 1, wherein the bottom portion of the first and second metal line(100b)s has a surface roughness larger than the top portion of the first and second metal line(100b)s.
Re claim 5 Lee and Lien disclose the method of claim 1, wherein the bottom portion of the first and second metal line(100b)s has an impurity concentration larger than the top portion of the first and second metal line(100b)s.
Re claim 6 Lee and Lien disclose the method of claim 1, wherein the first plating current[0010 of Lien] is less than about 0.6 amps per square decimeter (ASD), and the second plating current[0010 of Lien] is larger than about 0.6 ASD.
Re claim 7 Lee and Lien disclose the method of claim 1, wherein a ratio of the second plating current[0010 of Lien] and the first plating current[0010 of Lien] ranges from about 2 : 1 to about 5 : 1.
Re claim 8 Lee and Lien disclose the method of claim 1, wherein the semiconductor structure is immersed in a plating solution[0012] during the electroplating process[0012], and the plating solution[0012] has a concentration of copper[0012] ions less than a concentration of sulfuric acid and a concentration of hydrochloric acid.
Re claim 9 Lee and Lien disclose the method of claim 8, wherein a ratio of the concentration of copper[0012] ions and the concentration of sulfuric acid ranges from about 1 : 2 to about 1 : 4.
Re claim 10 Lee and Lien disclose the method of claim 8, wherein a ratio of the concentration of copper[0012] ions and the concentration of hydrochloric acid ranges from about 1 : 2 to about 1: 3.8.
Re claim 21 Lee discloses a method, comprising: forming a substrate[0011];forming a seed layer(S1); forming a patterned layer on the seed layer(S1), the patterned layer including a first opening(OP1) and a second opening(OP2), the first opening(OP1) being wider than the second opening(OP2);performing an electroplating process[0012], thereby growing a bottom portion of a first metal line(100a) in the first opening(OP1) and a bottom portion of a second metal line(100b) in the second opening(OP2); thereby growing a top portion of the first metal line(100a) and a top portion of the second metal line(100b); removing the patterned layer to expose a portion of the seed layer(S1); and etching the exposed portion of the seed layer(S1) (see Fig 1C).
Lee does not disclose forming an interconnect structure over a substrate[0011]; forming a seed layer(S1) on the interconnect structure; performing an electroplating process[0012] with a first plating current, continuing the electroplating process[0012] with a second plating current that is different from the first plating current, wherein the top portion of the first metal line(100a) and the bottom portion of the first metal line(100a) have different grain sizes, wherein the top portion of the second metal line(100b) and the bottom portion of the second metal line(100b) have different grain sizes
Lien disclose forming an interconnect structure(720) over a substrate(700); performing an electroplating process with a first plating current[0010], continuing the electroplating process[0012] with a second plating current that is different from the first plating current[0026],
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Lien to the teachings of Lee in order to readily control growth of the electroplated film for bottom-up filling, and the superior electrical conductivity characteristics of the electroplated film [0002, Lien]. In doing so, forming a seed layer(S1 of Lee) on the interconnect structure(720 of Lien); wherein the top portion of the first metal line(100a of Lee) and the bottom portion of the first metal line(100a of Lee) have different grain sizes[0002 of Lien], wherein the top portion of the second metal line(100b) and the bottom portion of the second metal line(100b) have different grain sizes
Re claim 22 Lee and Lien disclose the method of claim 21, wherein a width of the first metal line(100a) is larger than a width of the second metal line(100b), and a height of the first metal line(100a) is larger than a height of the second metal line(100b) for less than about 0.4 um.
Re claim 23 Lee and Lien disclose the method of claim 21, wherein the first plating current[0010 of Lien] is less than the second plating current, and a duration of the first plating current[0010 of Lien] is longer than a duration of the second plating current.
Claim(s) 11-16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee(USPGPUB DOCUMENT: 2021/0090973, hereinafter Lee) in view of Lee (USPGPUB DOCUMENT: 2021/0082830, hereinafter Lee-830).
Re claim 11 Lee discloses an electroplating method for electroplating, comprising: immersing a semiconductor structure into a plating solution[0012], and performing an electrochemical reaction on the plating solution[0012] to form a redistribution layer(140) on the semiconductor structure.
Lee does not disclose wherein the plating solution[0012] includes copper ions, sulfuric acid, and hydrochloric acid, wherein the plating solution[0012] further includes an accelerator, a suppressor, and a leveler, and wherein a concentration of the leveler is less than the accelerator and the suppressor;, wherein a height difference between metal lines of the redistribution layer(140) is less than about 0.4 um.
Lee-830 disclose wherein the plating solution[0045] includes copper ions, sulfuric acid, and hydrochloric acid, wherein the plating solution further includes an accelerator, a suppressor, and a leveler[0051], and wherein a concentration of the leveler is less than the accelerator and the suppressor; wherein a height difference between metal lines of the redistribution layer(140) is less than about 0.4 um[0048].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Lien to the teachings of Lee in order to increase the reliability of the electrical performance within an internal component [0001, Lee-830].
Re claim 12 Lee and Lee-830 disclose the electroplating method of claim 11, wherein the performing of the electrochemical reaction includes applying a first plating current through the plating solution[0012] to form a lower portion of the metal lines, and applying a second plating current through the plating solution[0012] to form an upper portion of the metal lines, and wherein the second plating current[0050 of Lee-830] is different from the first plating current.
Re claim 13 Lee and Lee-830 disclose the electroplating method of claim 12, wherein the second plating current[0050 of Lee-830] is stronger than the first plating current.
Re claim 14 Lee and Lee-830 disclose the electroplating method of claim 12, wherein a grain[0113 of Lee-830] size of the upper portion of the metal lines is larger than the lower portion of the metal lines.
Re claim 15 Lee and Lee-830 disclose the electroplating method of claim 12, wherein a ratio[0047 of Lee-830] of a height of the lower portion of the metal lines and a height of the metal lines[0051 of Lee-830] ranges from about 10% to about 20%.
Re claim 16 Lee and Lee-830 disclose the electroplating method of claim 11, wherein the concentration[0051 of Lee-830] of the leveler is less than each of the accelerator and the suppressor for about 30% to about 50%.
Conclusion
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/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812