DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-18 in the reply filed on 12/4/25 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-9, 11-14, and 17 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by SHIH et al. (US 2022/0230946, hereinafter, Shih.)
In regard to claims 1 and 11, in fig. 1, Shih discloses a package structure 1a (also considered including a first tiered/second tiered structures as claimed) (para [0018]), comprising:
a first semiconductor die 171, an electric component (para [0027]);
a first encapsulant 120 (para [0019]) laterally encapsulating the first semiconductor die;
a first bonding structure 160 (para [0019]) disposed on the first semiconductor die and the
first encapsulant;
a second bonding structure 180 (para [0018]) disposed on the first bonding structure;
a second semiconductor die 172/173 (para [0018]) disposed on the second bonding structure; and
a second encapsulant 192 (para [0018]) laterally encapsulating the second semiconductor die,
wherein the first encapsulant is spaced apart from the second encapsulant by at least one of the first bonding structure and the second bonding structure.
Regarding claim 2, wherein the second bonding structure is laterally encapsulated by the second encapsulant, fig. 1.
Regarding claims 3 and 13, wherein the second encapsulant is in contact with sidewalls of the second bonding structure, sidewalls of the second semiconductor die, and the first bonding structure, fig. 1.
Regarding claim 4, wherein the first encapsulant is spaced apart from the second encapsulant by the first bonding structure.
Regarding claim 5, wherein the first bonding structure has a substantial uniform thickness, fig. 1.
Regarding claim 6, wherein the first bonding structure comprises first portions having a first thickness and second portions having a second thickness, the first portions are covered by the first semiconductor die, the second portions are uncovered by the first semiconductor die, and the second thickness is greater than the first thickness, fig. 1.
Regarding claim 7, wherein the second portions are covered by the first encapsulant, fig. 1.
Regarding claim 8, Shih further comprising:
a redistribution structure, at dielectric layer 110, wherein the redistribution structure and the second semiconductor die are disposed on opposite sides of the first semiconductor, fig. 1.
Regarding claim 9, Shih further comprising:
through vias 140 penetrating through the first encapsulant, wherein the redistribution structure is electrically connected to the second semiconductor die through the through vias, fig. 1.
Regarding claim 12, wherein a first lateral dimension of the first bonding structure is greater than a second lateral dimension of the second bonding structure, fig. 1.
Regarding claim 14, wherein the first bonding structure has a substantial uniform thickness, fig. 1.
Regarding claim 17, Shih further comprising:
a redistribution structure, wherein the redistribution structure and the second semiconductor die are disposed on opposite sides of the first semiconductor; and
through vias penetrating through the first encapsulant, wherein the redistribution structure is electrically connected to the second semiconductor die through the through vias (see also the discussion of claim 9 above and fig. 1.)
Claim(s) 11 (also read on claim 1) and 15-16 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by CHOI (US 2021/0272930.)
In regard to claim 11 (and also discloses limitations of claim 1), in fig. 14, Choi discloses a package structure 1700 (para [0020]), comprising:
a first tiered structure (top part of the package), comprising:
a first semiconductor die 400 (para [0029]) laterally encapsulated by a first encapsulant 490 (para [0090]);
a first bonding structure in the layer 445 including pads 440 (para [0047]);
a second tiered structure (bottom part of the package structure) stacked on and electrically connected to the first tiered structure, and the second tiered structure comprising:
a second semiconductor die 200 (para [0029] and figs. 1-2 and 13) laterally encapsulated by a second encapsulant 290 (para [0042]);
a second bonding structure 310 (para [0031]), wherein the first semiconductor die is electrically connected to the second semiconductor die through the first bonding structure and the second bonding structure, the first bonding structure and the second bonding structure are between the first semiconductor die and the second semiconductor die, and the first encapsulant is spaced apart from the second encapsulant by the first bonding structure.
Regarding claim 15, in fig. 14, Choi further discloses, wherein the first bonding structure comprises recessed at 300S2 to exposed the lower layer, and uncovered by the first semiconductor die.
Regarding claim 16, wherein the recessed portions are in contact with the first encapsulant, fig. 14.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 10 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shih as applied to claims 1 and 11 above, and further in view of SHEN (US 2022/0302010.)
In regard to claims 10 and 18, Shih discloses all of the claimed limitations as mentioned above, except 1 further comprising:
a support substrate disposed on the second semiconductor die and the second encapsulant.
Shen, in fig. 2, discloses an analogous package (para [0011) including a first die 102, second dies D1 and D2 on the first dies on a connecting element. Shen also further discloses addition substrates on the package, for example, heatsink 218 and carrier 200 (paras [0043] and [0034].) The addition substate provide structure support and heat dissipation, substrate 218, for example. This si known to one of ordinary skill in the art.
Therefore, it would have been obvious to one of ordinary skill in the art at the time of the application was filed to form addition substrate as taught in order to provide heat dissipation.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHAN W HA whose telephone number is (571)272-1707. The examiner can normally be reached M-T: 8:00AM-6:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WAEL FAHMY can be reached at (571)-272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NATHAN W HA/Primary Examiner, Art Unit 2814