DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Amendments/Arguments
Amendments made to claims 1-2 and 11, as filed on December 19, 2025, are acknowledged.
The amendment made to claim 1 has overcome the previous double patenting rejections to claims 1 and its dependent claims 3-5 as set forth in the Office Action mailed on September 22, 2025.
The amendment made to the specification and claim 11 are responsive. The previous objections to the specification and claim 11, as set forth in the Office Action mailed on September 22, 2025 have been withdrawn.
Applicant's arguments, see Remarks filed on December 19, 2025, with respect to amended claim 1 have been fully considered and are persuasive. The previous rejections to the claim and its dependents under 35 USC 103(a), as set forth in the Office Action mailed on September 22, 2025, have been withdrawn.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement.
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
Claims 8-9, 12-13, 15 and 17-20 are rejected on the ground of nonstatutory obviousness-type double patenting as being obvious over U.S. Patent No. 11,756,838 (hereinafter ‘838).
Regarding claim 8, ‘838 claims a method comprising: providing a first gate stack and a second gate stack over a substrate, wherein the first and second gate stacks each includes a gate electrode layer, a first layer disposed over the gate electrode layer and a second layer disposed over the first layer, wherein the second gate stack is different size than the first gate stack (claims 1 and 3; the second layer claimed in claim 3 of ‘838 reads on the first layer recited in the instant claim; the first layer claimed in claim 3 of ‘838 reads on the second layer recited in the instant claim); forming a first dielectric layer directly on the second layer of the first and second gate stacks (the first material layer reads on a first dielectric layer, claim 1); forming a second dielectric layer directly on the first dielectric layer (the dielectric layer reads on a second dielectric layer, claim 1); removing a first portion of the second dielectric layer to expose the first dielectric layer over the first gate stack while a second portion of the second dielectric layer covers the first dielectric layer disposed over the second gate stack (claim 1); and removing the second portion of the second dielectric layer and the first dielectric layer over the first and second gate stacks to expose the second layer in the first and second gate stacks (claim 1), wherein the first and second gate stacks extend to the same height above the substrate after the removing of the second portion of the second dielectric layer and the first dielectric layer over the first and second gate stacks (claim 8).
Regarding claim 9, ‘838 claims removing the exposed second layer from the first and second gate stacks to expose the gate electrode layer in the first and second gate stacks (claim 3).
Regarding claim 12, ‘838 claims wherein the removing of the first portion of the second dielectric layer includes performing a first removal process using a first removal material, and wherein the removing of the second portion of the second dielectric layer and the first dielectric layer includes performing a second removal process using a second removal material, and wherein the second removal process is different than the first removal process and the second removal material is different than the first removal material (claims 1 and 7).
Regarding claim 13, ‘838 claims wherein the first removal process includes a chemical mechanical planarization process and the second removal process includes an etching process (claim 7).
Regarding claim 15, ‘838 claims wherein the first gate stack has a first width and the second gate stack has a second width that is different than the first width after the providing of first gate stack and the second gate stack over the substrate (claim 15).
Regarding claim 17, ‘838 claims a method comprising: providing a first gate stack and a second gate stack over a substrate, wherein the first and second gate stacks each includes a gate electrode layer, a first layer disposed over the gate electrode layer and a second layer disposed over the first layer, wherein the second gate stack is different size than the first gate stack (claims 1 and 3; the second layer claimed in claim 3 of ‘838 reads on the first layer recited in the instant claim; the first layer claimed in claim 3 of ‘838 reads on the second layer recited in the instant claim); forming a first dielectric layer directly on the first and second gate stacks (the first material layer reads on a first dielectric layer, claim 1); removing the first dielectric layer over the first gate stack and the second gate stack to expose the second layer in the first and second gate stacks (claim 1); removing the exposed second layer from the first and second gate stacks to expose the first layer in the first and second gate stacks, wherein the first dielectric layer disposed on the first and second gate stacks extends to a greater height above the substrate than the first layer after the removing of the exposed second layer from first and second gate stacks to expose the first layer in the first and second gate stacks (claim 5); and removing the exposed first layer from the first and second gate stacks to expose the gate electrode layer in the first and second gate stacks (claims 1 and 4).
Regarding claim 18, ‘838 claims wherein the removing of the first dielectric layer over the first gate stack and the second gate stack to expose the second layer in the first and second gate stacks includes performing a first etching process using a first etchant, and wherein the removing of the exposed second layer from the first and second gate stacks to expose the first layer in the first and second gate stacks includes performing a second etching process using a second etchant that has a different material composition than the first etchant (claim 1).
Regarding claim 19, ‘838 claims forming a second dielectric layer directly on the first dielectric layer prior to removing the first dielectric layer over the first gate stack and the second gate stack to expose the second layer in the first and second gate stacks (the dielectric layer reads on a second dielectric layer, claim 1).
Regarding claim 20, ‘838 claims after removing the exposed first layer from the first and second gate stacks, performing a gate replacement process on the first and second gate stacks by replacing the gate electrode layer in the first and second gate stacks with at least another gate electrode layer (claim 2).
Allowable Subject Matter
Claims 1-7 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 1, the amendment made to the instant claim has overcome the previous prior art rejection to the claim as set forth in the Office Action mailed on September 22, 2025, see Applicant's arguments filed on December 19, 2025 for more details. Further search fails to find prior art, taken either alone or in combination, that discloses or renders obvious a method comprising: depositing an etch stop layer over top surfaces of the first gate stack, the second gate stack and the substrate as well as sidewalls of the first gate stack and the second gate stack; forming a dielectric layer over the etch stop layer; performing a first removal process to remove a first portion of the dielectric layer over the first and second gate stacks, wherein a second portion of the of the dielectric layer is disposed directly over the first gate stack while no portions of the dielectric layer are disposed directly over the second gate stack after the performing of the first removal process, wherein the first removal process includes applying a first removal material to remove the first portion of the dielectric layer from over the first and second gate stacks; performing a second removal process to expose the first layer in the first and second gate stacks such that top surfaces of the first layer and the dielectric layer are lower than topmost surface of the etch stop layer, in the context of the instant claim. The closest cited prior art of Lin discloses that top surfaces of the first layer and the dielectric layer are higher than topmost surface of the etch stop layer after the second removal process (Fig. 7).
Regarding claims 2-7, they are dependent on claim 1.
Claims 8-20 would be allowable if the nonstatutory obviousness-type double patenting rejections set forth in this Office Action are overcome.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 8, the cited prior art of record, taken either alone or in combination, fails to disclose or render obvious a method comprising: removing the second portion of the second dielectric layer and the first dielectric layer over the first and second gate stacks to expose the second layer in the first and second gate stacks, wherein the first and second gate stacks extend to the same height above the substrate after the removing of the second portion of the second dielectric layer and the first dielectric layer over the first and second gate stacks, in the context of the instant claim. The closest cited prior art of Lin discloses removing the second portion of the second dielectric layer and the first dielectric layer over the first and second gate stacks to expose the second layer in the first and second gate stacks, wherein the first and second gate stacks extend to different heights above the substrate after the removing of the second portion of the second dielectric layer and the first dielectric layer over the first and second gate stacks (Figs. 3-5).
Regarding claims 9-16, they are dependent on claim 8.
Regarding claim 17, the cited prior art of record, taken either alone or in combination, fails to disclose or render obvious a method comprising: removing the exposed second layer from the first and second gate stacks to expose the first layer in the first and second gate stacks, wherein the first dielectric layer disposed on the first and second gate stacks extends to a greater height above the substrate than the first layer after the removing of the exposed second layer from first and second gate stacks to expose the first layer in the first and second gate stacks, in the context of the instant claim. The closest cited prior art of Lin discloses removing the exposed second layer from the first and second gate stacks to expose the first layer in the first and second gate stacks, wherein the first dielectric layer disposed on the first and second gate stacks extends to a lower height above the substrate than the first layer after the removing of the exposed second layer from first and second gate stacks to expose the first layer in the first and second gate stacks (Figs. 5-7).
Regarding claims 18-20, they are dependent on claim 17.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JIONG-PING LU whose telephone number is (571) 270-1135. The examiner can normally be reached on M-F: 9:00am – 5:00pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua L Allen, can be reached at telephone number (571)270-3176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from Patent Center. Status information for published applications may be obtained from Patent Center. Status information for unpublished applications is available through Patent Center for authorized users only. Should you have questions about access to Patent Center, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) Form at https://www.uspto.gov/patents/uspto-automated- interview-request-air-form.
/JIONG-PING LU/
Primary Examiner, Art Unit 1713