Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
The following is in response to the communication filed 2/3/2026.
Claims 1-16 and 21-24 are currently pending.
Claims 1, 10, and 11 have been amended.
Claims 17-20 have been canceled.
Claims 1-16 and 21-24 have been examined.
Priority
The applicant' s claim for benefit of Provisional Patent Application Serial No. 63/491,778, filed on March 23, 2023 has been received and acknowledged.
Election/Restriction
Applicant’s election without traverse of claims 1-16 Invention I in the reply filed on 2/3/2026 is acknowledged. Claim 17-20 of Invention II are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention II, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 2/3/2026.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 10/3/2023 and 1/21/2025, are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: MULTI-GATED SEMICONDUCTOR DEVICE MANUFACTURED ON A BONDED MULTI-STACK ASSEMBLED WAFER
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2, 9-11, 14, and 21-24 are rejected under 35 U.S.C. 103 as being unpatentable over Cho et al. KR20240142209A (hereinafter Cho – US 20240321886 A1 will be used for translation) Gardner et al US 20220238652 A1 (hereinafter Gardner).
Regarding claim 1:
Cho discloses a method of manufacturing a stacked integrated circuit (Fig. 20-39E).
patterning the composite stack to form a fin-shaped structure; (Fig. 21A - 21B, [0130] the stack – which includes nanosheets NSD1-4 and NSU1-3, lower sacrificial layers SLD, and upper sacrificial layers SLU- shown in Fig. 21A is etched to form fin-shaped structures.)
form a dummy gate stack over a channel region (area that includes nanosheets NSD1-4 and NSU1-3) of the fin-shaped structure; (Fig. 23A, The dummy gate stack is the part of the fin structure that includes a second hard mask pattern HMK2 and conductive patterns DPCP are etched in the second horizontal direction.)
etching a source/drain region of the fin-shaped structure to form a source/drain trench; (Fig. 26, the stack structures including upper stack NSSU and lower stack NSSD are anisotropically etched to form the trenches.)
forming a bottom source/drain feature in the source/drain trench to contact sidewalls of the first plurality of channel layers; (Fig. 27A, the lower source/drain region SDD is formed in the trench and contacts the side walls of the plurality of lower nanosheet stack structures NSSD.)
forming a top source/drain feature over the bottom source/drain feature to contact sidewalls of the second plurality of channel layers; (Fig. 28A, the upper source/drain region SDU is formed in the trench and contacts the side walls of the plurality of upper nanosheet stack structures NSSU.)
selectively removing the first plurality of sacrificial layers (lower sacrificial layers SLD) and the second plurality of sacrificial layers (upper sacrificial layers SLU) in the channel region of the fin-shaped structure to form bottom channel members (ND1-4 of lower nanosheet stack NDD) and top channel members (NU1-3 of upper nanosheet stack) over the bottom channel members; (Fig. 30A, [0141], the gate removed space GRS is formed by removing the conductive patter DPCP, lower sacrificial layers SLD and upper sacrificial layers SLU.)
forming a first gate structure to wrap around each of the bottom channel members; and (Fig. 31A, lower gate electrode PCD is formed.)
forming a second gate structure to wrap around each of the top channel members. (Fig. 31A, upper gate electrode PCU is formed.)
Cho does not appear to disclose:
forming a first stack over a first substrate, the first stack comprising a first plurality of channel layers interleaved by a first plurality of sacrificial layers;
forming a first bonding layer over the first stack;
forming a second stack over a second substrate, the second stack comprising a second plurality of channel layers interleaved by a second plurality of sacrificial layers;
forming a second bonding layer over the second stack;
bonding the second bonding layer to the first bonding layer such that the second stack is disposed over the first stack to form a composite stack;
after the bonding, removing the second substrate over the composite stack;
Gardner, which teaches manufacture of microfabricated transistor device (Gardner, Abstract) discloses:
forming a first stack (Fig. 9A, first wafer 910) over a first substrate (bulk silicon), the first stack comprising a first plurality of channel layers (silicon 3106) interleaved by a first plurality of sacrificial layers; (SiGe 3108)
forming a first bonding layer over the first stack;(vertical isolation 3112)
forming a second stack over a second substrate, ([0058], second wafer 920 – in figure shown as 910 top stack) the second stack comprising a second plurality of channel layers interleaved by a second plurality of sacrificial layers; ([0058], the second wafer has a similar substack as first wafer 910)
forming a second bonding layer over the second stack; (vertical isolation 3224)
bonding the second bonding layer to the first bonding layer such that the second stack is disposed over the first stack to form a composite stack; ([0058], vertical isolation 3224 and 3112 are bonded.)
after the bonding, removing the second substrate over the composite stack; ([0058], the bulk silicon on second wafer 920 is removed from one side of the combined wafer so only one side has bulk silicon 3302.)
patterning the composite stack to form a fin-shaped structure; (Fig. 9C, [0058] the combined wafer is etched as a directed etch to form channel structures.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Cho to have form a first stack over a first substrate, the first stack comprising a first plurality of channel layers interleaved by a first plurality of sacrificial layers, an a first bonding layer over the first stack, form a second stack over a second substrate, the second stack comprising a second plurality of channel layers interleaved by a second plurality of sacrificial layers, form a second bonding layer over the second stack and then bond the second bonding layer to the first bonding layer such that the second stack is disposed over the first stack to form a composite stack, and after the bonding, removing the second substrate over the composite stack, and then patterning the composite stack to form a fin-shaped structure as taught by Gardner for purposes of having rotational symmetry so that alignment precision of multiple stacks is not an issue for later processing. (Gardner, [0057])
Regarding claim 2, Cho as modified by Gardner teach the elements of claim 1 as recited above.
Gardner discloses that the bonding layers (3112, and 3224) are a vertical isolation. See Fig. 9A. Gardner further discloses that the vertical isolation is a dielectric such as silicon oxide. (Gardner, [0045].)
Regarding claim 9, Cho as modified by Gardner teach the elements of claim 1 as recited above.
wherein, after the bonding, an observable interface exists between the first bonding layer (Fig. 9B, vertical isolation 3112) and the second bonding layer. (Fig. 9B, vertical isolation 3224) (There would by necessity be an observable interface caused by bonding the vertical isolation 3112 and vertical isolation 3224.)
Regarding claim 10:
Cho et al. discloses a method of manufacturing a stacked integrated circuit (Fig. 20-39E).
patterning the composite stack to form a fin-shaped structure; (Fig. 21A - 21B, [0130] the stack– which includes nanosheets NSD1-4 and NSU1-3, lower sacrificial layers SLD, and upper sacrificial layers SLU- shown in Fig. 21A is etched to form fin-shaped structures.)
form a dummy gate stack over a channel region (area that includes nanosheets NSD1-4 and NSU1-3) of the fin-shaped structure; (Fig. 23A, The dummy gate stack is the part of the fin structure that includes a second hard mask pattern HMK2 and conductive patterns DPCP are etched in the second horizontal direction.)
forming a bottom source/drain feature in the source/drain trench to contact sidewalls of the first plurality of channel layers; (Fig. 27A, the lower source/drain region SDD is formed in the trench and contacts the side walls of the plurality of lower nanosheet stack structures NSSD.)
forming a top source/drain feature over the bottom source/drain feature to contact sidewalls of the second plurality of channel layers; (Fig. 28A, the upper source/drain region SDU is formed in the trench and contacts the side walls of the plurality of upper nanosheet stack structures NSSU.)
selectively removing the first plurality of sacrificial layers (lower sacrificial layers SLD) and the second plurality of sacrificial layers (upper sacrificial layers SLU) in the channel region of the fin-shaped structure to form bottom channel members (ND1-4 of lower nanosheet stack NDD) and top channel members (NU1-3 of upper nanosheet stack) over the bottom channel members; (Fig. 30A, [0141], the gate removed space GRS is formed by removing the conductive patter DPCP, lower sacrificial layers SLD and upper sacrificial layers SLU.)
forming a first gate structure to wrap around the bottom channel member; and (Fig. 31A, lower gate electrode PCD is formed.)
forming a second gate structure to wrap around the top channel member. (Fig. 31A, upper gate electrode PCU is formed.)
Cho does not appear to disclose:
A method, comprising:
forming a first stack over a first substrate, the first stack comprising a first plurality of silicon layers interleaved by a first plurality of silicon germanium layers;
forming a first bonding layer over the first stack;
forming a second stack over a second substrate, the second stack comprising a second plurality of silicon layers interleaved by a second plurality of silicon germanium layers;
forming a second bonding layer over the second stack; and
bonding the second bonding layer to the first bonding layer such that the second stack is disposed over the first stack to form a composite stack,
after the bonding, removing the second substrate;
patterning the composite stack to form a fin-shaped structure;
….
wherein a germanium content in each of the first plurality of silicon germanium layer and each of the second plurality of silicon germanium layers is the same.
Gardner, which teaches manufacture of microfabricated transistor device (Gardner, Abstract) discloses:
forming a first stack (Fig. 9A, first wafer 910) over a first substrate (bulk silicon), the first stack comprising a first plurality of silicon layers (silicon 3106) interleaved by a first plurality of silicon germanium layers;(SiGe 3108)
forming a first bonding layer over the first stack;(vertical isolation 3112)
forming a second stack over a second substrate, ([0058], second wafer 920 – in figure shown as 910 top stack) the second stack comprising a second plurality of silicon layers interleaved by a second plurality of silicon germanium layers; ([0058], the second wafer has a similar substack as first wafer 910)
forming a second bonding layer over the second stack; (vertical isolation 3224)
bonding the second bonding layer to the first bonding layer such that the second stack is disposed over the first stack to form a composite stack; ([0058], vertical isolation 3224 and 3112 are bonded
after the bonding, removing the second substrate; ([0058], the bulk silicon on second wafer 920 is removed from one side of the combined wafer so only one side has bulk silicon 3302.)
patterning the composite stack to form a fin-shaped structure; (Fig. 9C, [0058] the combined wafer is etched as a directed etch to form channel structures.)
….
wherein a germanium content in each of the first plurality of silicon germanium layer and each of the second plurality of silicon germanium layers is the same. ([0058], the second wafer has a similar substack as first wafer 910 and therefore the germanium content of the first plurality of SiGe layers would be same as the content of the SiGe layers in the second plurality.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Cho to have form a first stack over a first substrate, the first stack comprising a first plurality of silicon layers interleaved by a first plurality of silicon germanium layers, an a first bonding layer over the first stack, form a second stack over a second substrate, t the second stack comprising a second plurality of silicon layers interleaved by a second plurality of silicon germanium layers, form a second bonding layer over the second stack and then bond the second bonding layer to the first bonding layer such that the second stack is disposed over the first stack to form a composite stack, and then after the bonding, removing the second substrate and then patterning the composite stack to form a fin-shaped structure, wherein a germanium content in each of the first plurality of silicon germanium layer and each of the second plurality of silicon germanium layers is the same
as taught by Gardner for purposes of having rotational symmetry so that alignment precision of multiple stacks is not an issue for later processing. (Gardner, [0057])
Regarding claim 11, Cho as modified by Gardner discloses all the elements of claim 10. Cho further discloses:
before the forming of the bottom source/drain feature, anisotropically etching the source/drain region of the fin-shaped structure to form expose sidewalls of the first plurality of silicon layers, the second first plurality of silicon germanium layers, the first bonding layer, the second bonding layer, the second plurality of silicon layers, and the second plurality of silicon germanium layers. (Fig. 26, the stack structures including upper stack NSSU and lower stack NSSD are anisotropically etched to form the trenches.)
Regarding claim 14, Cho as modified by Gardner teach the elements of claim 10 as recited above.
Gardner discloses that the bonding layers (3112, and 3224) are a vertical isolation. See Fig. 9A. Gardner further discloses that the vertical isolation is a dielectric such as silicon oxide. (Gardner, [0045].)
Regarding claim 21:
Cho et al. discloses a method of manufacturing a stacked integrated circuit (Fig. 20-39E).
patterning the composite stack (Fig. 21A-21B, the stack includes nanosheets NSD1-4 and NSU1-3, lower sacrificial layers SLD, and upper sacrificial layers SLU) to form a fin-shaped structure, (Fig. 21A - 21B, [0130] the stack shown in Fig. 21A is etched to form fin-shaped structures.) the fin-shaped structure comprising a base portion patterned from the first substrate; (Fig. 21B, base substrate layer BSUB is a base portion of the first substrate that is patterned.)
forming an isolation feature over the first substrate to surround the base portion; (Fig. 22D, [0131] isolation film STI completely sills the spaces between the patterned portions of the base substrate layer BSUB.)
form a dummy gate stack over a channel region (area that includes nanosheets NSD1-4 and NSU1-3) of the fin-shaped structure; (Fig. 23A, The dummy gate stack is the part of the fin structure that includes a second hard mask pattern HMK2 and conductive patterns DPCP are etched in the second horizontal direction.)
depositing a gate spacer over sidewalls of the dummy gate stack; (Fig. 25A, second material layer CDL2 is deposited over the second hard mask pattern HMK2 and conductive patterns DPCP.)
etching a source/drain region of the fin-shaped structure to form a source/drain trench; (Fig. 26, the stack structures including upper stack NSSU and lower stack NSSD are anisotropically etched to form the trenches.)
forming a bottom source/drain feature over the source/drain trench to contact sidewalls of the first channel layers; (Fig. 27A, the lower source/drain region SDD is formed in the trench and contacts the side walls of the plurality of lower nanosheet stack structures NSSD.)
forming a top source/drain feature over the bottom source/drain feature to contact sidewalls of the second channel layers; (Fig. 28A, the upper source/drain region SDU is formed in the trench and contacts the side walls of the plurality of upper nanosheet stack structures NSSU.)
releasing at least one of the first channels layers (ND1-4 of lower nanosheet stack NDD) as a bottom channel member; (Fig. 30A, [0141], the gate removed space is formed by removing the conductive patter DPCP and lower sacrificial layers SLD.)
releasing at least one of the second channel layers ((NU1-3 of upper nanosheet stack) over as a top channel member; (Fig. 30A, [0141], the gate removed space is formed by removing the conductive patter DPCP and upper sacrificial layers SLU.)
forming a first gate structure to wrap around the bottom channel member; and (Fig. 31A, lower gate electrode PCD is formed.)
forming a second gate structure to wrap around the top channel member, (Fig. 31A, upper gate electrode PCU is formed.)
Cho does appear to disclose:
forming a first stack over a first substrate, the first stack comprising first channel layers interleaved by first sacrificial layers;
forming a first bonding layer over the first stack;
forming a second stack over a second substrate, the second stack comprising second channel layers interleaved second sacrificial layers;
forming a second bonding layer over the second stack; and
bonding the second bonding layer to the first bonding layer such that the second stack is disposed over the first stack to form a composite stack,
after the bonding, removing the second substrate;
patterning the composite stack to form a fin-shaped structure, the fin-shaped structure comprising a base portion patterned from the first substrate;
… wherein the first bonding layer and the second bonding layer comprise silicon oxide, silicon carbonitride, silicon nitride, silicon oxynitride, or silicon oxycarbonitride.
Gardner, which teaches manufacture of microfabricated transistor device (Gardner, Abstract) discloses:
forming a first stack (Fig. 9A, first wafer 910) over a first substrate (bulk silicon), the first stack comprising a first plurality of channel layers (silicon 3106) interleaved by a first plurality of sacrificial layers; (SiGe 3108)
forming a first bonding layer over the first stack;(vertical isolation 3112)
forming a second stack over a second substrate, ([0058], second wafer 920 – in figure shown as 910 top stack) the second stack comprising a second plurality of channel layers interleaved by a second plurality of sacrificial layers; ([0058], the second wafer has a similar substack as first wafer 910)
forming a second bonding layer over the second stack; (vertical isolation 3224)
bonding the second bonding layer to the first bonding layer such that the second stack is disposed over the first stack to form a composite stack; ([0058], vertical isolation 3224 and 3112 are bonded.)
after the bonding, removing the second substrate; ([0058], the bulk silicon on second wafer 920 is removed from one side of the combined wafer so only one side has bulk silicon 3302.)
patterning the composite stack to form a fin-shaped structure; (Fig. 9C, [0058] the combined wafer is etched as a directed etch to form channel structures.)
…wherein the first bonding layer and the second bonding layer comprise silicon oxide, silicon carbonitride, silicon nitride, silicon oxynitride, or silicon oxycarbonitride. ([0045], vertical isolation 3112 and vertical isolation 3224 is a dielectric which includes silicon oxide.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Cho to have form a first stack over a first substrate, the first stack comprising a first plurality of channel layers interleaved by a first plurality of sacrificial layers, an a first bonding layer over the first stack, form a second stack over a second substrate, the second stack comprising a second plurality of channel layers interleaved by a second plurality of sacrificial layers, form a second bonding layer over the second stack and then bond the second bonding layer to the first bonding layer such that the second stack is disposed over the first stack to form a composite stack, and after the bonding, removing the second substrate over the composite stack, and then patterning the composite stack to form a fin-shaped as taught by Gardner for purposes of having rotational symmetry so that alignment precision of multiple stacks is not an issue for later processing. (Gardner, [0057])
Regarding claim 22, Cho as modified by Gardner discloses all the elements of claim 21 as recited above.
Cho further discloses:
before the forming of the bottom source/drain feature, depositing a leakage block layer over the source/drain trench. (Fig. 27A, [0136], fourth material layer CDL 4 is formed to cover a portion of the STI. The fourth material layer CDL4 may be nitride and therefore act as a leakage block layer.)
Regarding claim 23, Cho as modified by Gardner discloses all the elements of claim 22 as recited above.
Cho further discloses:
wherein the leakage block layer comprises an undoped semiconductor material or a dielectric material. ([0136], fourth material layer is a nitride which is known dielectric material.)
Regarding claim 24, Cho as modified by Gardner discloses all the elements of claim 21 as recited above.
Cho further discloses:
before the forming of the top source/drain feature, depositing a bottom contact etch stop layer (CESL) (Fig. 28A-28D, [0138] fifth material layer CDL5 form second insulating layer L02) and a bottom interlayer dielectric (ILD) layer (Fig. 28A-28D, [00138], a fourth insulating layer L04 fills the space defined by the second insulating layer L02.) over the bottom source/drain feature, (Fig. 28A-28D, the first material layer CDL5 and the fourth insulating layer L04 are above the lower source/drain region.)
wherein the bottom CESL interfaces sidewalls of the first bonding layer and the second bonding layer. (Fig. 28A, the fifth material layer CDL5 interface the sidewalls.)
Claims 3-5, 15, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Cho as modified by Gardner as applied to claim1 and 10 above, and further in view of Luo et al. US 20200075539 A1 (hereinafter Luo).
Regarding claim 3, Cho as modified by Gardner teach the elements of claim 1 as recited above.
Neither Cho or Gardner appear to disclose:
treating surfaces of the first bonding layer and the second bonding layer with a plasma of nitrogen (N2),oxygen (02), or argon (Ar);
bringing the first bonding layer and the second bonding layer in contact with one another; and
after the bringing, performing an anneal to bond the first bonding layer and the second bonding layer.
Luo, which teaches a first wafer being bonded to a second wafer (Luo, [0006]) therefore solving the problem of wafer to wafer bonding, discloses:
treating surfaces of the first bonding layer (Fig. 5, first oxide layer 450) and the second bonding layer (Fig. 6, second oxide layer 250) with a plasma of nitrogen (N2),oxygen (02), or argon (Ar); (Fig. 5 and 6, [0065], [0088] pre-bonding treatment performed on the surface of the first oxide layer 450 and second oxide layer 250 with a plasma activation process 110 using N2.)
bringing the first bonding layer and the second bonding layer in contact with one another; and (Fig.7, [0071], face-to-face bonding after plasma activation process attaches the first oxide layer 450 and second oxide layer 250.)
after the bringing, performing an anneal to bond the first bonding layer and the second bonding layer. (Fig. 8, [0078], annealing treatment after the step of Fig. 7.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Cho as modified by Gardner to include treating surfaces of the first bonding layer and the second bonding layer with a plasma of nitrogen (N2),oxygen (02), or argon (Ar), bringing the first bonding layer and the second bonding layer in contact with one another, and after the bringing, performing an anneal to bond the first bonding layer and the second bonding layer as taught by Luo for purposes of bonding by using the interface chemistry, in which covalent bonds are formed at contact surfaces. (Luo, [0060].)
Regarding claim 4, Cho as modified by Gardner and Luo teach the elements of claim 3 as recited above.
Luo further discloses:
wherein the bonding further comprises:
before the bringing, cleaning the surfaces of the first bonding layer (Fig. 5, first oxide layer 450) and the second bonding layer (Fig. 6, second oxide layer 250) with ammonia, hydrogen peroxide, hydrochloric acid, hydrogen peroxide, or water. ([0088], cleaning the first oxide layer 450 and second bonding layer 250 with deionized water.)
Regarding claim 5, Cho as modified by Gardner teach the elements of claim 1 as recited above.
Gardner discloses that manufacturing the semiconductor device includes film-forming deposition process. However, Neither Cho or Gardner appear to specifically disclose:
wherein the forming of the first bonding layer comprises depositing the first bonding layer using chemical vapor deposition (CVD) or atomic layer deposition (ALD).
Luo, which teaches a first wafer being bonded to a second wafer (Luo, [0006]) therefore solving the problem of wafer to wafer bonding, discloses:
wherein the forming of the first bonding layer (Fig. 1, first oxide layer 450)comprises depositing the first bonding layer using chemical vapor deposition (CVD) or atomic layer deposition (ALD). ([0027], first oxide layer 450 is formed by atomic layer deposition ALD.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Cho as modified Gardner to have forming of the first bonding layer comprises depositing the first bonding layer using chemical vapor deposition (CVD) or atomic layer deposition (ALD) as taught by Luo for purposes of increase the uniformity in thickness of the oxide layer. (Luo, [0027].)
Regarding claim 15, Cho as modified by Gardner teach the elements of claim 10 as recited above.
Neither Cho or Gardner appear to disclose:
treating surfaces of the first bonding layer and the second bonding layer with a plasma of nitrogen (N2),oxygen (02), or argon (Ar);
bringing the first bonding layer and the second bonding layer in contact with one another; and
after the bringing, performing an anneal to bond the first bonding layer and the second bonding layer.
Luo, which teaches a first wafer being bonded to a second wafer (Luo, [0006]) therefore solving the problem of wafer to wafer bonding, discloses:
treating surfaces of the first bonding layer (Fig. 5, first oxide layer 450) and the second bonding layer (Fig. 6, second oxide layer 250) with a plasma of nitrogen (N2),oxygen (02), or argon (Ar); (Fig. 5 and 6, [0065], [0088] pre-bonding treatment performed on the surface of the first oxide layer 450 and second oxide layer 250 with a plasma activation process 110 using N2.)
bringing the first bonding layer and the second bonding layer in contact with one another; and (Fig.7, [0071], face-to-face bonding after plasma activation process attaches the first oxide layer 450 and second oxide layer 250.)
after the bringing, performing an anneal to bond the first bonding layer and the second bonding layer. (Fig. 8, [0078], annealing treatment after the step of Fig. 7.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Cho as modified by Gardner to include treating surfaces of the first bonding layer and the second bonding layer with a plasma of nitrogen (N2),oxygen (02), or argon (Ar), bringing the first bonding layer and the second bonding layer in contact with one another, and after the bringing, performing an anneal to bond the first bonding layer and the second bonding layer as taught by Luo for purposes of bonding by using the interface chemistry, in which covalent bonds are formed at contact surfaces. (Luo, [0060].)
Regarding claim 16, Cho as modified by Gardner and Luo teach the elements of claim 15 as recited above.
Luo further discloses:
wherein the bonding further comprises:
before the bringing, cleaning the surfaces of the first bonding layer (Fig. 5, first oxide layer 450) and the second bonding layer (Fig. 6, second oxide layer 250) with ammonia, hydrogen peroxide, hydrochloric acid, hydrogen peroxide, or water. ([0088], cleaning the first oxide layer 450 and second bonding layer 250 with deionized water.)
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Cho, Gardner, and Luo as applied to claim 5 above, and further in view of “Low temperature atomic layer deposition of SiO2 thin films using di-isopropylaminosilane and ozone” by Lee et al. (hereinafter Lee).
Regarding claim 6, Cho as modified by Gardner and Luo teach the elements of claim 15 as recited above.
Neither Cho, Gardner, or Luo appear to disclose:
wherein the depositing comprises a temperature below 600°C.
Lee, depositing silicon dioxide for electronic applications (Lee, Introduction, page 2095), discloses:
wherein the depositing comprises a temperature below 600°C. (Lee shows deposition temperatures between 100 to 250 oC.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Cho as modified by Gardner and Luo to have the depositing comprises a temperature below 600°C as taught by Lee for purposes of precise thickness control of silicon dioxide film. (Lee, Introduction, page 2095)
Claims 7 is rejected under 35 U.S.C. 103 as being unpatentable over Cho as modified by Gardner as applied to claim 1 above, and further in view of Yamazaki et al. US 20180025918 A1 (hereinafter Yamazaki).
Regarding claim 7, Cho as modified by Gardner teach the elements of claim 1 as recited above.
Gardner discloses that the dielectric is deposited by a film forming deposition method. (Gardner, [0003]) and after the wafer can be annealed to bond the two wafers. (Gardner, [0054].)
However, Gardner does specifically disclose:
depositing the first bonding layer using sputtering.
Yamazaki, which teaches creating an insulating layer containing excess oxygen (Yamazaki, [0134]), discloses:
depositing the first bonding layer using sputtering. ([0139], an insulating layer can be created by a sputtering method.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Cho as modified by Gardner to have deposit the first bonding layer using sputtering as taught by Yamazaki for purposes of covering unevenness. (Yamazaki,[0137].)
Claims 8 is rejected under 35 U.S.C. 103 as being unpatentable over Cho as modified by Gardner as applied to claim 1 above, and further in view of Hingerl et al. US 20190393037 A1 (hereinafter Hingerl).
Regarding claim 8, Cho as modified by Gardner teach the elements of claim 1 as recited above.
Neither Cho or Gardner appear to disclose:
wherein the first bonding layer and the second bonding layer comprise a thickness between about 1 nm and about 100 nm.
Hingerl, which teaches a method of bonding a first substrate with a second substrate, discloses:
wherein the first bonding layer and the second bonding layer comprise a thickness between about 1 nm and about 100 nm. (Kurt, [0015], bonding thickness is kept to several 10 nm.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Cho as modified by Gardner to have the first bonding layer and the second bonding layer comprise a thickness between about 1 nm and about 100 nm. as taught by Hingerl for purposes of creating a transition-free substrate stack. (Hingerl, [0059].)
Claims 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Cho and Gardner as applied to claim 11 above, and further in view of Rachmady et al. US 20200294969 A1 (hereinafter Rachmady).
Regarding claim 12, Cho as modified by Gardner teaches all the elements of claim 11 as above.
Neither Cho or Gardner appear to disclose:
after the anisotropically etching, selectively recessing the sidewalls of the first plurality of silicon germanium layers and the sidewalls of the second plurality of silicon germanium layers to form inner spacer recesses; and
forming inner spacer features in the inner spacer recesses to interleave the first plurality of silicon layers and the second plurality of silicon layers in the channel region,
wherein the selectively recessing does not substantially recess the sidewalls of the first bonding layer and the second bonding layer.
Rachmady, which teaches stacked transistors (Rachmady, Abstract), disclose:
after the anisotropically etching, (Fig. 6B, shows and anisotropic etch of the stacked channels) selectively recessing the sidewalls of the first plurality of silicon germanium layers (Fig. 7B, [0031], sacrificial material 104 in device stratum 130-1 ), and the sidewalls of the second plurality of silicon germanium layers to form inner spacer recesses; and(Fig. 7B, [0031], sacrificial material 104 in device stratum 130-1 ),
forming inner spacer features (Fig. 7B, spacers 116) in the inner spacer recesses to interleave the first plurality of silicon layers and the second plurality of silicon layers in the channel region, ([0027], Spacers 116 may be made of silicon nitride and are on the side surfaces of the sacrificial material 104.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Cho as modified by Gardner to have, after the anisotropically etching, selectively recessing the sidewalls of the first plurality of silicon germanium layers and the sidewalls of the second plurality of silicon germanium layers to form inner spacer recesses; and forming inner spacer features in the inner spacer recesses to interleave the first plurality of silicon layers and the second plurality of silicon layers in the channel region as taught by Rachmady for purposes of electrical isolation for the semiconductor device when the later gate stack will be formed in place of the sacrificial material.
The device of Cho as modified by Gardner and Rachmady would by necessity show that that “the selectively recessing does not substantially recess the sidewalls of the first bonding layer and the second bonding layer,” one of ordinary skill in the art at the time of filing would be able to use standard etching and masking techniques to form the fins and inner spacers. (Rachmady, [0032] and [[0036].)
Regarding claim 13, Cho as modified by Gardner and Rachmady disclose all the elements of claim 12.
Gardner further discloses the composition of the first and second bonding layers is silicon dioxide. (Gardner, [0045].)
Rachmady further the composition of the inner spacer features is silicon nitride. (Rachmady, [0027].)
Prior Art Made of Record
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Xu et al. US 20190319021 A1 – Figs 5A-5E a method of manufacturing a stacked FET and Figs. 6A-6F a second method of manufacturing a stacked FET.
Wang et al. US 20170025306 A1 – Fig. 1 method for producing a layered semiconductor structure with cleaning and bonding steps.
Chang et al. US 20220359768 A1 – Fig. 6B forming inner spacers 164 next to sacrificial layers 122.
Conclusion
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/HEIM KIRIN GREWAL/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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