DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 16-35 in the reply filed on 11/19/25 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 16-35 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cheng(USPGPUB DOCUMENT: 20210249461, hereinafter Cheng) in view of Chen (USPGPUB DOCUMENT: 20210035907, hereinafter Chen).
Re claim 16 Cheng discloses in Figs 14-23, rotated 180 degrees, a method, comprising: forming a semiconductor device(202) over a device region(region of 202) of a substrate(102); forming a back-end-of-line (BEOL) structure comprising a plurality of metallization layers[0024] over the semiconductor device(202), wherein each of the metallization layers[0024] comprises: a dielectric layer(128)[0024]; interconnect features(130/132) in the dielectric layer(128)[0024] and over the device region(region of 202) of the substrate(102), wherein the interconnect features(130/132) are electrically connected with the semiconductor device(202); and metal patterns(112)[0029] over a non-device region(other region than region of 202) of the substrate(102), wherein the metal patterns(112)[0029] are electrically isolated from the semiconductor device(202);
Cheng does not disclose metal patterns(112)[0029] in the dielectric layer(128)[0024]; forming an opening in a portion of the BEOL structure[0018] over the non-device region(other region than region of 202) of the substrate(102) and extending through at least two of the metallization layers[0024]; and filling the opening with a metal.
Chen discloses metal patterns(30) in the dielectric layer(150/160/170)[0018 of Chen]; forming an opening(280 of Chen) in a portion of the BEOL structure[0038 of Chen] over the non-device region(R2 of Chen) of the substrate(100 of Chen); and filling the opening with a metal(184)[0033 of Chen].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Chen to the teachings of Cheng in order to improve performance, such as increased speed and decreased power consumption [0001, Chen]. In doing so, forming an opening(280 of Chen) in a portion of the BEOL structure[0038 of Chen] over the non-device region(R2 of Chen) of the substrate(100 of Chen) and extending through at least two of the metallization layers[0024]
Re claim 17 Cheng and Chen disclose the method of claim 16, wherein forming the opening(280 of Chen) in the portion of the BEOL structure[0018] comprises performing an etching process[0022 of Chen] from a top surface of the BEOL structure[0018].
Re claim 18 Cheng and Chen disclose the method of claim 16, wherein forming the opening(280 of Chen) in the portion of the BEOL structure[0018] comprises performing an etching process[0022 of Chen] from a backside of the substrate(102) until the opening(280 of Chen) extends into the portion of the BEOL structure[0018].
Re claim 19 Cheng and Chen disclose the method of claim 16, wherein the metal patterns(112)[0029] are overlay marks(112)[0029], wherein a first one of the metallization layers[0024] is formed by using the overlay marks(112)[0029] in a second one of the metallization layers[0024] below the first one of the metallization layers[0024], such that the interconnect features(130/132) of the first one of the metallization layers[0024] are aligned with the interconnect features(130/132) of the second one of the metallization layers[0024].
Re claim 20 Cheng and Chen disclose the method of claim 16, wherein the metal patterns(112)[0029] are test critical dimension patterns, and the method further comprising measuring a critical dimension of the metal patterns(112)[0029] during forming the BEOL structure[0018].
Re claim 21 Cheng discloses in Figs 14-23, rotated 180 degrees, a method, comprising: forming a semiconductor device(202) over a device region(region of 202) of a substrate(102), while leaving a non- device region(other region than region of 202) of the substrate(102) free of semiconductor device(202); forming a back-end-of-line (BEOL) structure comprising a plurality of metallization layers[0024] over the substrate(102) and at a level above the semiconductor device(202), wherein each of the metallization layers[0024] comprises:a dielectric layer(128)[0024];interconnect features(130/132) in the dielectric layer(128)[0024] and over the device region(region of 202) of the substrate(102), wherein the interconnect features(130/132) are electrically connected with the semiconductor device(202); and overlay marks(112)[0029] over the non-device region(other region than region of 202) of the substrate(102);
Cheng does not disclose overlay marks(112)[0029] in the dielectric layer(128)[0024]; and forming a via structure in the dielectric layer(128)[0024] and over the non-device region(other region than region of 202) of the substrate(102), wherein in a top view at least one of the overlay marks(112)[0029] is cut by the via structure.
Chen discloses overlay marks(30) in the dielectric layer(150/160/170)[0018 of Chen]; and forming a via structure(184)[0033 of Chen] in the dielectric layer and over the non-device region(R2 of Chen) of the substrate(100 of Chen)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Chen to the teachings of Cheng in order to improve performance, such as increased speed and decreased power consumption [0001, Chen]. In doing so, wherein in a top view at least one of the overlay marks(112)[0029] is cut by the via structure(184)[0033 of Chen].
Re claim 22 Cheng and Chen disclose the method of claim 21, wherein the interconnect features(130/132) are electrically isolated from the overlay marks(112)[0029].
Re claim 23 Cheng and Chen disclose the method of claim 21, wherein the via structure(184)[0033 of Chen] is thicker than each of the metallization layers[0024].
Re claim 24 Cheng and Chen disclose the method of claim 21, wherein a top surface of the via structure(184)[0033 of Chen] is substantially level with a top surface of the dielectric layer(128)[0024] of a topmost one of the metallization layers[0024].
Re claim 25 Cheng and Chen disclose the method of claim 21, further comprising forming a bump(296/196) over the via structure(184)[0033 of Chen].
Re claim 26 Cheng and Chen disclose the method of claim 21, wherein the via structure(184)[0033 of Chen] is formed from a backside of the substrate(102).
Re claim 27 Cheng and Chen disclose the method of claim 21, further comprising forming another metallization layer(208/108) covering the via structure(184)[0033 of Chen].
Re claim 28 Cheng and Chen disclose the method of claim 21, wherein a plurality of overlay marks(112)[0029] are cut by the via structure(184)[0033 of Chen].
Re claim 29 Cheng discloses in Figs 14-23, rotated 180 degrees, a method, comprising: forming a semiconductor device(202) over a substrate(102); forming a back-end-of-line (BEOL) structure comprising a plurality of metallization layers[0024] over the substrate(102) and at a level above the semiconductor device(202), wherein each of the metallization layers[0024] comprises: a dielectric layer(128)[0024]; and metal patterns(112)[0029]
Cheng does not disclose metal patterns(112)[0029] in the dielectric layer(128)[0024]; and forming an opening extending through at least two of the metallization layers[0024], wherein the opening exposes the metal patterns(112)[0029] of the at least two of the metallization layers[0024]; and forming a via structure in the opening.
Chen discloses metal patterns(30) in the dielectric layer(150/160/170)[0018 of Chen]; and forming an opening(280 of Chen), and forming a via structure(184)[0033 of Chen] in the opening.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to apply the teachings of Chen to the teachings of Cheng in order to improve performance, such as increased speed and decreased power consumption [0001, Chen]. In doing so, forming an opening(280 of Chen) extending through at least two of the metallization layers[0024], wherein the opening(280 of Chen) exposes the metal patterns(112)[0029] of the at least two of the metallization layers[0024];
Re claim 30 Cheng and Chen disclose the method of claim 29, wherein the metal patterns(112)[0029] form a plurality of overlay marks(112)[0029].
Re claim 31 Cheng and Chen disclose the method of claim 30, wherein in a top view the via structure(184)[0033 of Chen] overlaps at least two of the overlay marks(112)[0029].
Re claim 32 Cheng and Chen disclose the method of claim 29, wherein the opening(280 of Chen) does not overlap the semiconductor device(202).
Re claim 33 Cheng and Chen disclose the method of claim 29, wherein the via structure(184)[0033 of Chen] is electrically isolated from the semiconductor device(202).
Re claim 34 Cheng and Chen disclose the method of claim 29, wherein the opening(280 of Chen) is formed from a backside of the substrate(102).
Re claim 35 Cheng and Chen disclose the method of claim 29, wherein opening(280 of Chen) is formed over a non-device region(other region than region of 202) of the substrate(102) that is free of semiconductor device(202).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PATRICIA D VALENZUELA whose telephone number is (571)272-9242. The examiner can normally be reached Monday-Friday 10am-6pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/PATRICIA D VALENZUELA/Primary Examiner, Art Unit 2812
Prosecution Insights