DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/23/2026 has been entered.
Response to Arguments
Applicant's arguments filed 09/18/2025 have been fully considered but they are not persuasive. Applicant argued that the prior art RYU does not disclose “the electrically conducting via structure and the second electrically conducting line structure are continuous portions of the electrically conductive material and are free of an interface therebetween, and wherein the via width is greater than the second line width”. Examiner respectfully disagreed: 1. as it can be seen on Fig. 14 the via width W1 is greater than the second line width W4 (para [0210]). 2. Also according to Case law Howard v. Detroit Stove Works, 150 U.S. 164 (1893) it has been held that forming in one piece an article which has formerly been formed in two pieces and put together involves only routine skill in the art. Please note that in the instant application, (para [0088], [0102], [0104], [0115] and [0125]), applicant has not disclosed any criticality for the claimed limitations.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 9 – 10, 13 – 15, 21, 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over RYU et al. (US 20220418106 A1, “RYU”).
Regarding claim 1, RYU discloses (Fig. 14) an interposer, comprising: a first electrically conducting line structure (122c); and a monolithic structure comprising an electrically conductive material, the monolithic structure including: an electrically conducting via structure (131c) having a via width (W1) that is electrically connected to the first electrically conducting line structure (122c); and a second electrically conducting line structure (132c) having a second line width (W4), wherein the electrically conducting via structure and the second electrically conducting line structure are continuous portions of the electrically conductive material and are free of an interface therebetween, and wherein the via width is greater than the second line width (W1 < W4).
RYU discloses the claimed invention except for (wherein the electrically conducting via structure and the second electrically conducting line structure are continuous portions of the electrically conductive material and are free of an interface therebetween). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide wherein the electrically conducting via structure and the second electrically conducting line structure are continuous portions of the electrically conductive material and are free of an interface therebetween, since it has been held that forming in one piece an article which has formerly been formed in two pieces and put together involves only routine skill in the art. Howard v. Detroit Stove Works, 150 U.S. 164 (1893). Please note that in the instant application, (para [0088], [0102], [0104], [0115] and [0125]), applicant has not disclosed any criticality for the claimed limitations.
Additionally, having a via and a pad as an integral one piece is known in the art as it is provided by LEE (US 20150016082 A1) see Fig. 15
Regarding claim 9, RYU discloses the interposer of claim 1, wherein a portion of the first electrically conducting line structure (122c) is embedded within the electrically conducting via structure (131c) such that the first electrically conducting line structure and the electrically conducting via structure share a common connection volume (Fig. 14).
Regarding claim 10, RYU discloses the interposer of claim 1, wherein: the second electrically conducting line structure (132c) comprises a second line thickness and is formed in contact with a surface of the electrically conducting via structure (131c); the surface of the electrically conducting via structure is perpendicular to a thickness direction such that a first combined spatial extent of the second electrically conducting line structure and the electrically conducting via structure along the thickness direction is greater than the via thickness (see annotated figure below); and wherein a second combined spatial extent of the second electrically conducting line structure and the electrically conducting via structure along the thickness direction is given by a sum of the via thickness and the second line thickness.
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Regarding claim 13, RYU discloses (Fig. 14) an interposer, comprising: a first dielectric layer (111); a second dielectric layer (112) formed over the first dielectric layer (111); and a monolithic structure comprising an electrically conductive material, the monolithic structure including: a first electrically conducting line structure (122c) formed over the first dielectric layer and within the second dielectric layer; an electrically conducting via structure (131c) having a via width (W1) formed within the second dielectric layer (112); and a second electrically conducting line structure (132c) having a second line width (W4), wherein the electrically conducting via structure and the second electrically conducting line structure are continuous portions of the electrically conductive material and are free of an interface therebetween, and wherein the via width is greater than the second line width (W1 < W4).
RYU discloses the claimed invention except for (wherein the electrically conducting via structure and the second electrically conducting line structure are continuous portions of the electrically conductive material and are free of an interface therebetween). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide wherein the electrically conducting via structure and the second electrically conducting line structure are continuous portions of the electrically conductive material and are free of an interface therebetween, since it has been held that forming in one piece an article which has formerly been formed in two pieces and put together involves only routine skill in the art. Howard v. Detroit Stove Works, 150 U.S. 164 (1893). Please note that in the instant application, (para [0088], [0102], [0104], [0115] and [0125]), applicant has not disclosed any criticality for the claimed limitations.
Additionally, having a via and a pad as an integral one piece is known in the art as it is provided by LEE (US 20150016082 A1) see Fig. 15
Regarding claim 14, RYU discloses the interposer of claim 13, wherein the electrically conducting via structure (131c) is formed within the second dielectric layer (112) and formed over the first electrically conducting line structure (122c) such that the electrically conducting via structure is electrically connected to, and partially surrounds, a portion of the first electrically conducting line structure (see Fig. 14), and wherein a first line thickness of the first electrically conducting line structure is less than a via thickness of the electrically conducting via structure such that a combined spatial extent of the first electrically conducting line structure and the electrically conducting via structure along a thickness direction is equal to the via thickness (See annotated figure below).
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Regarding claim 15, RYU discloses the interposer of claim 13, further comprising: a third dielectric layer (114) formed over the second dielectric layer (112), wherein the second electrically conducting line structure (132c) is formed over the second dielectric layer (112) and within the third dielectric layer (114) such that the second electrically conducting line structure is electrically connected to the electrically conducting via structure (See Fig. 14).
Regarding claim 21, RYU discloses (Fig. 14) an interposer, comprising: a first electrically conducting line structure (122c) is formed over a first dielectric layer (111); a second dielectric layer (112) is formed over the first dielectric layer (111); and a monolithic structure comprising an electrically conductive material, the monolithic structure including: an electrically conducting via structure (131c) is formed within the second dielectric layer (112) over a portion of the first electrically conducting line structure (122c) so as to form an electrical connection with the first electrically conducting line structure; and a second electrically conducting line structure (132c) , (W4), wherein the electrically conducting via structure and the second electrically conducting line structure are continuous portions of the electrically conductive material and are free of an interface therebetween.
RYU discloses the claimed invention except for (wherein the electrically conducting via structure and the second electrically conducting line structure are continuous portions of the electrically conductive material and are free of an interface therebetween). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to provide wherein the electrically conducting via structure and the second electrically conducting line structure are continuous portions of the electrically conductive material and are free of an interface therebetween, since it has been held that forming in one piece an article which has formerly been formed in two pieces and put together involves only routine skill in the art. Howard v. Detroit Stove Works, 150 U.S. 164 (1893). Please note that in the instant application, (para [0088], [0102], [0104], [0115] and [0125]), applicant has not disclosed any criticality for the claimed limitations.
Additionally, having a via and a pad as an integral one piece is known in the art as it is provided by LEE (US 20150016082 A1) see Fig. 15
Regarding claim 23, RYU discloses the interposer of claim 21, wherein: the second electrically conducting line structure (132c) comprises a second line thickness and is formed in contact with a surface of the electrically conducting via structure (131c); the surface of the electrically conducting via structure is perpendicular to a thickness direction such that a first combined spatial extent of the second electrically conducting line structure and the electrically conducting via structure along the thickness direction is greater than the via thickness; and wherein a second combined spatial extent of the second electrically conducting line structure and the electrically conducting via structure along the thickness direction is given by a sum of the via thickness and the second line thickness (See annotated figure below).
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Claim(s) 2 – 6, 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over RYU et al. (US 20220418106 A1, “RYU”) in view of HO et al. (US 20170231093 A1, “HO”).
Regarding claim 2, RYU discloses the interposer of claim 1, wherein a portion of the first electrically conducting line structure is provided within the electrically conducting via structure such that the first electrically conducting line structure is at least partially overlapping with the electrically conducting via structure (See Fig. 14) in an overlapping region such that the overlapping region is substantially rectangular in plan view, and wherein the first electrically conducting line structure and the electrically conducting via structure share a common surface (Fig. 14).
RYU is silent on an overlapping region such that the overlapping region is substantially rectangular in plan view
However, HO discloses (Fig. 3) an overlapping region such that the overlapping region is substantially rectangular in plan view (Fig. 3)
RYU and HO are both considered to be analogous to the claimed invention because they are in the same field of circuit board. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified RYU to incorporate the teachings of HO and provide an overlapping region such that the overlapping region is substantially rectangular in plan view (Fig. 3). Doing so would enable a reduced-dimension structure.
Regarding claim 3, RYU in view of HO discloses the interposer of claim 2, wherein RYU further discloses a first line thickness of the first electrically conducting line structure is less than a via thickness of the electrically conducting via structure such that the first electrically conducting line structure is at least partially overlapping with the electrically conducting via structure along a thickness direction (see annotated figure below).
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Regarding claim 4, RYU in view of HO discloses the interposer of claim 3, wherein a combined spatial extent of the first electrically conducting line structure and the electrically conducting via structure along the thickness direction equals the via thickness (see annotated figure above).
Regarding claim 5, RYU in view of HO discloses the interposer of claim 2, wherein RYU further discloses a first line width (W4) of the first electrically conducting line structure is less than a via width (W1 or W2) of the electrically conducting via structure such that the first electrically conducting line structure is at least partially overlapping with the electrically conducting via structure along a width direction (para [0210]).
Regarding claim 6, RYU in view of HO discloses the interposer of claim 5, wherein RYU further discloses a combined spatial extent of the first electrically conducting line structure and the electrically conducting via structure along the width direction is equal to the via width (along the width direction: W1 + W4 = W1 and W2 + W4 = W2, see Fig. 14).
Regarding claim 22, RYU discloses the interposer of claim 21, wherein a portion of the first electrically conducting line (122c) structure is provided within the electrically conducting via structure (131c) such that the first electrically conducting line structure is at least partially overlapping with the electrically conducting via structure in an overlapping region such that the overlapping region is substantially rectangular in plan view, and wherein the first electrically conducting line structure and the electrically conducting via structure share a common surface (See Fig. 14).
RYU is silent on an overlapping region such that the overlapping region is substantially rectangular in plan view
However, HO discloses (Fig. 3) an overlapping region such that the overlapping region is substantially rectangular in plan view (Fig. 3)
RYU and HO are both considered to be analogous to the claimed invention because they are in the same field of circuit board. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified RYU to incorporate the teachings of HO and provide an overlapping region such that the overlapping region is substantially rectangular in plan view (Fig. 3). Doing so would enable a reduced-dimension structure.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over RYU et al. (US 20220418106 A1, “RYU”)
Regarding claim 7, RYU discloses the interposer of claim 1, wherein: the first electrically conducting line structure (122c) is formed over a first dielectric layer extending linearly along a length direction (111); a second dielectric layer (112) is formed over the first dielectric layer (111); and the electrically conducting via structure (131c) is formed within the second dielectric layer (112) over a portion of the first electrically conducting line structure (122c) so as to form an electrical connection with the first electrically conducting line structure (see Fig. 14)
RYU does not disclose and such that the first electrically conducting line structure extends laterally beyond an edge of the electrically conducting via structure along the length direction in this embodiment.
However, RYU discloses in the sixth embodiment (Fig. 15) such that the first electrically conducting line structure (122e) extends laterally beyond an edge of the electrically conducting via structure (121) along the length direction (See Fig. 15)
Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the fifth embodiment of RYU to incorporate the teachings of the sixth embodiment and provide such that the first electrically conducting line structure (122e) extends laterally beyond an edge of the electrically conducting via structure (121) along the length direction (See Fig. 15). Doing so can increase a separation distance between the plurality of via portions, and the circuit density can be increased (para [0247]).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over RYU et al. (US 20220418106 A1, “RYU”) in view of Cho et al. (US 20080225501 A1, “Cho”).
Regarding claim 8, RYU discloses the interposer of claim 1, further comprising an electrically conductive seed layer formed between the first electrically conducting line structure (122c) and the electrically conducting via structure (131c) and a plurality of third electrically conducting line structures (135), wherein the plurality of third electrically conducting line structures and the second electrically conducting line structure are coplanar (See Fig. 14), and wherein the plurality of third electrically conducting line structures are disposed on the electrically conductive seed layer.
RYU fails to disclose an electrically conductive seed layer formed between the first electrically conducting line structure and the electrically conducting via structure, and wherein the plurality of third electrically conducting line structures are disposed on the electrically conductive seed layer.
However, Cho discloses (Fig. 12 & 13) an electrically conductive seed layer (23) formed between the first electrically conducting line structure (14) and the electrically conducting via structure (22), and wherein the plurality of third electrically conducting line structures (24) are disposed on the electrically conductive seed layer (23).
RYU and Cho are both considered to be analogous to the claimed invention because they are in the same field of circuit board. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified RYU to incorporate the teachings of Cho and provide an electrically conductive seed layer (23) formed between the first electrically conducting line structure (14) and the electrically conducting via structure (22), and wherein the plurality of third electrically conducting line structures (24) are disposed on the electrically conductive seed layer (23). Doing so would ensure better conductivity and adhesion and enable electroplating (para [0042]).
Claim(s) 11, 16, 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over RYU et al. (US 20220418106 A1, “RYU”) in view of Muramatsu et al. (US 20120119377 A1, “Muramatsu”) and further in view of TSAI et al. (US 20180005846 A1, “TSAI”)
Regarding claim 11, RYU discloses the interposer of claim 1, further comprising: a via land (122 Fig. 11) structure electrically connected to the first electrically conducting line structure,
RYU does not disclose wherein the via land structure comprises an elongated structure comprising a land width that is smaller than a land length.
However, Muramatsu discloses (Fig. 6) wherein the via land structure (33) comprises an elongated structure comprising a land width that is smaller than a land length (see annotated figure below) and wherein the via land is separated from the electrically conducting via structure by an electrically conductive seed layer.
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RYU and Muramatsu are both considered to be analogous to the claimed invention because they are in the same field of circuit board. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified RYU to incorporate the teachings of Muramatsu and provide wherein the via land structure (33) comprises an elongated structure comprising a land width that is smaller than a land length (see annotated figure above). Doing so would optimize the interconnect density, electrical performance and manufacturability.
RYU in view of Muramatsu is silent on wherein the via land is separated from the electrically conducting via structure by an electrically conductive seed layer.
However, TSAI discloses (Fig. 2) wherein the via land (42) is separated from the electrically conducting via structure (46) by an electrically conductive seed layer (54).
RYU in view of Muramatsu and TSAI are both considered to be analogous to the claimed invention because they are in the same field of circuit board. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified RYU in view of Muramatsu to incorporate the teachings of TSAI and provide wherein the via land (42) is separated from the electrically conducting via structure (46) by an electrically conductive seed layer (54). Doing so would promote adhesion of conductive material and improves plating uniformity (para [0057] and [0087]).
Regarding claim 16, RYU discloses the interposer of claim 13, further comprising: a via land (122 Fig. 11) structure electrically connected to the first electrically conducting line structure,
RYU does not disclose wherein the via land structure comprises an elongated structure comprising a land width that is smaller than a land length, and wherein the via land is separated from the electrically conducting via structure by an electrically conductive seed layer.
However, Muramatsu discloses (Fig. 6) wherein the via land structure (33) comprises an elongated structure comprising a land width that is smaller than a land length (see annotated figure below).
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RYU and Muramatsu are both considered to be analogous to the claimed invention because they are in the same field of circuit board. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified RYU to incorporate the teachings of Muramatsu and provide wherein the via land structure (33) comprises an elongated structure comprising a land width that is smaller than a land length (see annotated figure above). Doing so would optimize the interconnect density, electrical performance and manufacturability.
RYU and Muramatsu are both considered to be analogous to the claimed invention because they are in the same field of circuit board. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified RYU to incorporate the teachings of Muramatsu and provide wherein the via land structure (33) comprises an elongated structure comprising a land width that is smaller than a land length (see annotated figure above). Doing so would optimize the interconnect density, electrical performance and manufacturability.
RYU in view of Muramatsu is silent on wherein the via land is separated from the electrically conducting via structure by an electrically conductive seed layer.
However, TSAI discloses (Fig. 2) wherein the via land (42) is separated from the electrically conducting via structure (46) by an electrically conductive seed layer (54).
RYU in view of Muramatsu and TSAI are both considered to be analogous to the claimed invention because they are in the same field of circuit board. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified RYU in view of Muramatsu to incorporate the teachings of TSAI and provide wherein the via land (42) is separated from the electrically conducting via structure (46) by an electrically conductive seed layer (54). Doing so would promote adhesion of conductive material and improves plating uniformity (para [0057] and [0087]).
Regarding claim 24, RYU discloses the interposer of claim 21, further comprising: a via land (122 Fig. 11) structure electrically connected to the first electrically conducting line structure,
RYU does not disclose wherein the via land structure comprises an elongated structure comprising a land width that is smaller than a land length, and wherein the via land is separated from the electrically conducting via structure by an electrically conductive seed layer.
However, Muramatsu discloses (Fig. 6) wherein the via land structure (33) comprises an elongated structure comprising a land width that is smaller than a land length (see annotated figure below).
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RYU and Muramatsu are both considered to be analogous to the claimed invention because they are in the same field of circuit board. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified RYU to incorporate the teachings of Muramatsu and provide wherein the via land structure (33) comprises an elongated structure comprising a land width that is smaller than a land length (see annotated figure above). Doing so would optimize the interconnect density, electrical performance and manufacturability.
RYU and Muramatsu are both considered to be analogous to the claimed invention because they are in the same field of circuit board. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified RYU to incorporate the teachings of Muramatsu and provide wherein the via land structure (33) comprises an elongated structure comprising a land width that is smaller than a land length (see annotated figure above). Doing so would optimize the interconnect density, electrical performance and manufacturability.
RYU in view of Muramatsu is silent on wherein the via land is separated from the electrically conducting via structure by an electrically conductive seed layer.
However, TSAI discloses (Fig. 2) wherein the via land (42) is separated from the electrically conducting via structure (46) by an electrically conductive seed layer (54).
RYU in view of Muramatsu and TSAI are both considered to be analogous to the claimed invention because they are in the same field of circuit board. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified RYU in view of Muramatsu to incorporate the teachings of TSAI and provide wherein the via land (42) is separated from the electrically conducting via structure (46) by an electrically conductive seed layer (54). Doing so would promote adhesion of conductive material and improves plating uniformity (para [0057] and [0087]).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over RYU et al. (US 20220418106 A1, “RYU”) in view of Muramatsu et al. (US 20120119377 A1, “Muramatsu”) and TSAI et al. (US 20180005846 A1, “TSAI”) as applied to claim 11 above, and further in view of Chen et al. (US 20230369288 A1, “Chen”).
Regarding claim 12, RYU in view of Muramatsu and TSAI discloses the interposer of claim 11,
RYU in view of Muramatsu and TSAI fails to disclose wherein the via land structure further comprises an elongated oval structure.
However, Chen discloses (Fig. 13B) wherein the via land structure further comprises an elongated oval structure (para [0058]).
RYU in view of Muramatsu, TSAI and Chen are both considered to be analogous to the claimed invention because they are in the same field of circuit board. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified RYU in view of Muramatsu and TSAI to incorporate the teachings of Chen and provide wherein the via land structure further comprises an elongated oval structure (para [0058]). Doing so would improve reliability and reduce cracking risks
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SIDI MOHAMED MAIGA whose telephone number is (703)756-1870. The examiner can normally be reached Monday - Friday 8 am 5 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached on 571-272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SIDI M MAIGA/Examiner, Art Unit 2847
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