DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I and Species 1c in the reply filed on November 21, 2025 is acknowledged.
Claims 6-9, and 17-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group and Species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on November 21, 2025.
Response to Amendment
This Office Action is in response to Applicant's amendments filed November 21, 2025. Claims 1, 3, 12, and 13 have been amended. Claims 21-28 have been added. Claims 6-9, and 17-20 have been canceled. Currently, claims 1-5, 10-16, and 21-28 are pending.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: 55A in Fig. 6A and 142 in Figs. 20A-21B.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the passivation layer recited in claims 22 and 24 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 13, and 26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US 20210126113 A1) herein after “Lin”.
Regarding claim 1, Figs. 1 and 4A-11B of Lin disclose a method of forming a semiconductor device (Fig. 1, semiconductor device 100, ¶ [0021]), the method comprising:
forming a first fin (Fig. 4A, fins 105, ¶ [0021]), a second fin (105), and a third fin (105) that protrude above a substrate (Fig. 4A, substrate 201, ¶ [0024]) and extend parallel to each other, wherein the third fin (105) is between the first fin (105) and the second fin (105);
forming first channel regions (Fig. 7B, nanostructures 701, ¶ [0072]), second channel regions (701), and third channel regions (701) over the first fin (105), the second fin (105), and the third fin (105), respectively;
forming a gate structure (Fig. 8B, gate electrodes 107, gate dielectric 703, ¶ [0072]) over the first fin (105), the second fin (105), and the third fin (105) and around the first channel regions (701), the second channel regions (701), and the third channel regions (701);
forming an interlayer dielectric (ILD) layer (Fig. 6A, contact etch stop layer 601, ¶ [0068]) over the first fin (105), over the second fin (105), over the third fin (105), and around the gate structure (107, 703);
forming a first dielectric plug (Fig. 10B, cut-metal gate structures 109, ¶ [0021]) and a second dielectric plug (109) in the gate structure (107, 703) to separate the gate structure (107, 703) into a plurality of segments, wherein the first dielectric plug (109) is formed between the first fin (105) and the third fin (105), and the second dielectric plug (109) is formed between the third fin (105) and the second fin (105);
after forming the first dielectric plug (109) and the second dielectric plug (109), performing a first etching process (Figs. 11A-11B, “The photo resist is then used as an etching mask to etch the excess dielectric material, edge portions of the cut-metal gate structures 109, the gate cap 801, and the gate electrode 107, so that the third opening 1003 (e.g., trenches, recesses, channels or the like) is formed”, ¶ [0096]) to remove a first segment of the gate structure (107, 703) disposed between the first dielectric plug (109) and the second dielectric plug (109), thereby forming a recess (1003) in the ILD layer (601);
after performing the first etching process (Figs. 11A-11B), performing a second etching process (Figs. 12A-12B, “Once the nanostructures 701 and a portion of the fin 105 protruding above the isolation regions 209 are exposed, a further etching process may be used to remove the materials of the nanostructures 701”, ¶ [0098]) different from the first etching process (Figs. 11A-11B) to remove the third channel regions (701); and
after performing the second etching process (Figs. 12A-12B), filling the recess (1003) with a dielectric material (Fig. 13B, CPODE structure 111, ¶ [0099]).
Regarding claim 2, Figs. 1 and 4A-11B of Lin disclose the method of claim 1 as applied above, and Figs. 3A-7B further disclose wherein the gate structure (107, 703) is a replacement gate structure (107, 703), wherein forming the gate structure (107, 703) comprises:
forming a dummy gate structure (Fig. 3AA, dummy gate electrode 303, dummy gate dielectric 211, ¶ [0035]) over the first fin (105), the second fin (105), and the third fin (105) and around the first channel regions (701), the second channel regions (701), and the third channel regions (701);
forming the ILD layer (601) around the dummy gate structure (303, 211);
removing the dummy gate structure (303, 211) to form an opening (Fig. 7A, “the dummy gate electrode 303 may be removed”, “the dummy gate dielectric 211 may be removed”, ¶ [0073-0074]) in the ILD layer (601);
forming a gate dielectric material (703) in the opening (Fig. 7A) around the first channel regions (701), the second channel regions (701), and the third channel regions (701) (“formation of the gate dielectric 703 over the nanostructures 701”, ¶ [0080]; and
filling the opening (Fig. 7A) with a gate electrode material (107) (Fig. 8A, “the gate electrodes 107 are formed using multiple layers, each layer deposited sequentially adjacent to each other using a highly conformal deposition process”, ¶ [0081]).
Regarding claim 13, Figs. 1 and 3A-11B of Lin disclose a method of forming a semiconductor device, the method comprising:
forming a dummy gate structure (303, 211) over a first fin (105) and around first channel regions (701) that are disposed over the first fin (105);
forming an interlayer dielectric (ILD) layer (601) over the first fin (105) around the dummy gate structure (303, 211);
replacing the dummy gate structure (303, 211) with a gate structure (107, 703);
forming a first dielectric plug (109) and a second dielectric plug (109) in the gate structure (107, 703) on opposing sides of the first fin (105), wherein the first dielectric plug (109) and the second dielectric plug (109) cut the gate structure (107, 703) into a plurality of segments that are separated from each other;
removing a segment of the gate structure (107, 703) interposed between the first dielectric plug (109) and the second dielectric plug (109) to form a recess (1003) in the ILD layer (601), wherein the recess (1003) exposes the first channel regions (701);
removing the exposed first channel regions (701); and
after removing the exposed first channel regions (701), filling the recess (1003) with a dielectric material (111).
Regarding claim 26, Figs. 1 and 4A-11B of Lin disclose a method of forming a semiconductor device, the method comprising:
forming a gate structure (107, 703) over a fin (105) and around channel regions (701) that are disposed over the fin (105);
forming an interlayer dielectric (ILD) layer over the fin (105) around the gate structure (107, 703);
forming a first dielectric plug (109) and a second dielectric plug (109) in the gate structure (107, 703) on opposing sides of the fin (105), wherein the first dielectric plug (109) and the second dielectric plug (109) cut the gate structure (107, 703) into a plurality of segments that are separated from each other;
forming a recess (1003) in the ILD layer (601) by removing a segment of the gate structure (107, 703) interposed between the first dielectric plug (109) and the second dielectric plug (109), wherein the recess (1003) exposes the channel regions (701);
removing the exposed channel regions (701); and
after removing the exposed channel regions (701), filling the recess (1003) with a dielectric material (111).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-4, 14-16, and 27-28 are rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 20210126113 A1) in view of Wang et al. (US 20200006075 A1) herein after “Wang”.
Regarding claim 3, Figs. 1 and 4A-11B of Lin disclose the method of claim 1 as applied above, and Figs. 11A-11B of Lin further disclose wherein the first etching process (Figs. 11A-11B) comprises a wet etching process (“the etching process used to form the third opening 1003 may be an isotropic etching process (e.g., a wet etching process)”, ¶ [0096]). Lin discloses that the second etching process is “an etching process such as a wet etch, a dry etch, combinations, or the like may be used”, ¶ [0098], but fails to explicitly disclose the second etching process comprises a plasma dry etching process.
In the similar field of endeavor of semiconductor device manufacturing, Fig. 3A of Wang discloses the second etching process comprises a plasma dry etching process (“the second etching step is an anisotropic etching, such as… plasma etching”, ¶ [0045]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Lin to include the plasma dry etching as disclosed by Wang, to obtain different selectivity in the etching processes (see Wang, ¶ [0045]) and/or because the known technique of plasma dry etching was recognized as part of ordinary capabilities of one skilled in the art. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 4, Lin and Wang together disclose the method of claim 3 as applied above, and Figs. 11A-11B of Lin further disclose wherein the recess (1003) is formed to expose a first sidewall of the first dielectric plug (109), a second sidewall of the second dielectric plug (109), a third sidewall of a first gate spacer (309), and a fourth sidewall of a second gate spacer (309), wherein the first gate spacer (309) and the second gate spacer (309) extend along opposing sidewalls of the gate structure (107, 703).
Regarding claim 14, Figs. 1 and 3A-11B of Lin disclose the method of claim 13 as applied above, and Figs. 11A-11B of Lin further disclose wherein removing the segment of the gate structure (107, 703) comprises performing a wet etching process (“the etching process used to form the third opening 1003 may be an isotropic etching process (e.g., a wet etching process)”, ¶ [0096]), wherein removing the exposed first channel regions (701) comprises performing an etching process (“an etching process such as a wet etch, a dry etch, combinations, or the like may be used”, ¶ [0098]).
Lin fails to explicitly disclose that the etching process comprises a plasma dry etching process.
In the similar field of endeavor of semiconductor device manufacturing, Fig. 3A of Wang discloses a plasma dry etching process (“the second etching step is an anisotropic etching, such as… plasma etching”, ¶ [0045]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Lin to include the plasma dry etching as disclosed by Wang, to obtain different selectivity in the etching processes (see Wang, ¶ [0045]) and/or because the known technique of plasma dry etching was recognized as part of ordinary capabilities of one skilled in the art. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 15, Lin and Wang together disclose the method of claim 14 as applied above, and Figs. 3A-7B of Lin further disclose wherein the first fin (105) is disposed between a second fin (105) and a third fin (105), wherein forming the dummy gate structure (303, 211) comprises forming the dummy gate structure (303, 211) over the first fin (105), the second fin (105), and the third fin (105), wherein the dummy gate structure (303, 211) surrounds the first channel regions (701) over the first fin (105), surrounds second channel regions (701) over the second fin (105), and surrounds third channel regions (701) over the third fin (105).
Regarding claim 16, Lin and Wang together disclose the method of claim 14 as applied above, and Lin further discloses comprising, after forming the first dielectric plug (109) and the second dielectric plug (109) and before removing the segment of the gate structure (107, 703):
forming a patterned mask layer over the ILD layer (601) and over the gate structure (107, 703), wherein an opening in the patterned mask layer exposes the segment of the gate structure (107, 703), wherein the patterned mask layer is used as an etching mask in the wet etching process and the plasma dry etching process (“The photo resist is then used as an etching mask to etch the excess dielectric material, edge portions of the cut-metal gate structures 109, the gate cap 801, and the gate electrode 107”, ¶ [0096]).
Regarding claim 27, Figs. 1 and 4A-11B of Lin disclose the method of claim 26 as applied above, and Figs. 11A-11B of Lin further disclose wherein forming the recess (1003) comprises:
performing a wet etching process (“the etching process used to form the third opening 1003 may be an isotropic etching process (e.g., a wet etching process)”, ¶ [0096]) to remove an upper portion (“etch the excess dielectric material, edge portions of the cut-metal gate structures 109, the gate cap 801, and the gate electrode 107”, ¶ [0096]) of the segment of the gate structure (107, 703); and
performing a first process to remove a lower portion (“another etching process is performed to remove the materials of the gate dielectric 703 within the third opening 1003”, ¶ [0097]) of the segment of the gate structure (107, 703) (“an etching process such as a wet etch, a dry etch, combinations, or the like may be used”, ¶ [0098]).
Lin fails to explicitly disclose that the first process is a plasma process.
In the similar field of endeavor of semiconductor device manufacturing, Fig. 3A of Wang discloses the first process is a plasma process (“the second etching step is an anisotropic etching, such as… plasma etching”, ¶ [0045]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Lin to include the plasma process as disclosed by Wang, to obtain different selectivity in the etching processes (see Wang, ¶ [0045]) and/or because the known technique of plasma dry etching was recognized as part of ordinary capabilities of one skilled in the art. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 28, Lin and Wang together disclose the method of claim 27 as applied above, and Lin further discloses wherein removing the exposed channel regions (701) comprises performing a second process different from the first process (“a further etching process may be used to remove the materials of the nanostructures 701 and to form the recess within the fin 105”, ¶ [0098]).
Lin fails to explicitly disclose that the processes are different plasma processes.
In the similar field of endeavor of semiconductor device manufacturing, Figs. 3A and 15A-15B of Wang disclose that the processes are different plasma processes (“the etchant may be a plasma containing HBr”, “The slanted plasma etching 152 may use argon ions”, ¶ [0050-0051]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Lin to include the different plasma processes as disclosed by Wang, to obtain different selectivity in the etching processes (see Wang, ¶ [0045]) and/or because the known technique of plasma dry etching was recognized as part of ordinary capabilities of one skilled in the art. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claims 5, 10-12, 21, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 20210126113 A1) and Wang (US 20200006075 A1) in further view of Chuang et al. (US 20220037315 A1) herein after “Chuang”.
Regarding claim 5, Lin and Wang together disclose the method of claim 4 as applied above, and Figs. 12A-12B of Lin further discloses wherein the second etching process (Figs. 12A-12B) removes portions of the third fin (105) underlying the third channel regions (701), wherein after the second etching process (Figs. 12A-12B), the recess (1003) in the ILD (601) has a downward protrusion (D2).
Lin and Wang fail to disclose the downward protrusion extends through shallow trench isolation (STI) regions and into the substrate, wherein the STI regions surround the first fin, the second fin, and the third fin.
In the similar field of endeavor of semiconductor device fabrication, Figs. 8B and 9B of Chuang disclose that the downward protrusion (Fig. 9B, trench 906, ¶ [0044]) extends through shallow trench isolation (STI) regions (Fig. 8B, STI features 317, ¶ [0026]) and into the substrate (Fig. 3A, substrate 302, ¶ [0022]), wherein the STI regions (317) surround the first fin (Fig. 8B, substrate portion 302A, ¶ [0025]), the second fin (302A), and the third fin (302A).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the protrusion of Lin with the extension through the STI as disclosed by Chuang, to isolate adjacent active regions (see Chuang, ¶ [0021]).
Regarding claim 10, Lin and Wang together disclose the method of claim 3 as applied above, and Figs. 11A-11B of Lin further disclose wherein the first etching process (Figs. 11A-11B) removes an upper portion (“etch the excess dielectric material, edge portions of the cut-metal gate structures 109, the gate cap 801, and the gate electrode 107”, ¶ [0096]) of the first segment of the gate structure (107, 703) distal from the substrate (201), wherein after the first etching process (Figs. 11A-11B), a lower portion of the first segment of the gate structure (107, 703) remains over and around the third channel regions (701), wherein the lower portion of the first segment of the gate structure (“the gate electrodes 107 are etched using an anisotropic etching process, and may stop on the top surface of the gate dielectric 703”, ¶ [0091]).
Lin and Wang fails to disclose wherein the lower portion of the first segment of the gate structure fills spaces between the third channel regions.
In the similar field of endeavor of semiconductor device fabrication, Fig. 7B of Chuang discloses wherein the first etching process (Figs. 7A-7B, “an etching process is performed to remove portions of the material layer 331 (e.g., in a region exposed by the opening 604) to form an opening 704”, ¶ [0041]) removes an upper portion of the first segment of the gate structure (Figs. 3A-3B, metal layer 312, metal layer 329, material layer 331, ¶ [0037]) distal from the substrate (302), wherein after the first etching process (forming opening 704), a lower portion of the first segment of the gate structure (312, 329, 331) remains over and around the third channel regions (Fig. 3B, nanosheet channel layers 306, ¶ [0023]), wherein the lower portion of the first segment of the gate structure (312, 329, 331) fills spaces between the third channel regions (306).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Lin to include the gate etching as disclosed by Chuang, to improve device reliability (see Chuang, ¶ [0043]).
Regarding claim 11, Lin, Wang and Chuang together disclose the method of claim 10 as applied above, and Figs. 11A-12B of Lin further disclose comprising, after performing the first etching process (Figs. 11A-11B) and before performing the second etching process (Figs. 12A-12B), performing a third etching process to remove the lower portion of the first segment of the gate structure (“Once the gate dielectric 703 has been exposed, another etching process is performed to remove the materials of the gate dielectric 703 within the third opening 1003 and to expose the nanostructures 701”, ¶ [0097]).
Regarding claim 12, Lin, Wang and Chuang together disclose the method of claim 11 as applied above, and Lin further discloses that the third etching process is “any suitable etching process”, ¶ [0097], but Lin and Chuang fail to explicitly disclose wherein the third etching process is another plasma dry etching process different from the plasma dry etching process.
In the similar field of endeavor of semiconductor device manufacturing, Figs. 3A and 15A-15B of Wang disclose that the third etching process is another plasma dry etching process different from the plasma dry etching process (“the etchant may be a plasma containing HBr”, “The slanted plasma etching 152 may use argon ions”, ¶ [0050-0051]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Lin to include the different plasma processes as disclosed by Wang, to obtain different selectivity in the etching processes (see Wang, ¶ [0045]) and/or because the known technique of plasma dry etching was recognized as part of ordinary capabilities of one skilled in the art. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Regarding claim 21, Lin, Wang and Chuang together disclose the method of claim 11 as applied above, and Lin further discloses wherein after performing the first etching process (Figs. 11A-11B) and before performing the third etching process, a gate dielectric material (703) of the first segment of the gate structure (107, 703) remains along inner sidewalls of gate spacers (309) facing the gate structure (“the etching process may stop on the gate dielectric 703”, ¶ [0096]), wherein performing the third etching process removes the gate dielectric material (703) from the inner sidewalls of the gate spacers (“Once the gate dielectric 703 has been exposed, another etching process is performed to remove the materials of the gate dielectric 703 within the third opening 1003”, ¶ [0097]).
Regarding claim 23, Lin, Wang and Chuang together disclose the method of claim 12 as applied above, but Lin and Chuang fail to disclose wherein the another plasma dry etching process and the plasma dry etching process are performed using different gas sources.
In the similar field of endeavor of semiconductor device manufacturing, Wang discloses the another plasma dry etching process and the plasma dry etching process are performed using different gas sources (“the etchant may be a plasma containing HBr”, “The slanted plasma etching 152 may use argon ions”, ¶ [0050-0051]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Lin to include the different plasma sources as disclosed by Wang, to obtain different selectivity in the etching processes (see Wang, ¶ [0045]) and/or because the known technique of plasma dry etching was recognized as part of ordinary capabilities of one skilled in the art. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 20210126113 A1), Wang (US 20200006075 A1) and Chuang (US 20220037315 A1) in further view of Jang et al. (US 20200135472 A1) herein after “Jang”.
Regarding claim 22, Lin, Wang and Chuang together disclose the method of claim 10 as applied above, but Lin and Chuang fail to disclose wherein performing the second etching process comprises performing multiple etching cycles, wherein each of the multiple etching cycles is performed by:
forming a passivation layer along sidewalls and a bottom of the recess;
performing an anisotropic etching process to remove the passivation layer from the bottom of the recess; and
after performing the anisotropic etching process, performing the plasma dry etching process.
In the similar field of endeavor of semiconductor device manufacturing, Fig. 3A of Wang discloses wherein performing the second etching process comprises performing the plasma dry etching process (“the second etching step is an anisotropic etching, such as… plasma etching”, ¶ [0045]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Lin to include the plasma dry etching as disclosed by Wang, to obtain different selectivity in the etching processes (see Wang, ¶ [0045]) and/or because the known technique of plasma dry etching was recognized as part of ordinary capabilities of one skilled in the art. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Wang fails to disclose wherein performing the second etching process comprises performing multiple etching cycles, wherein each of the multiple etching cycles is performed by:
forming a passivation layer along sidewalls and a bottom of the recess;
performing an anisotropic etching process to remove the passivation layer from the bottom of the recess; and
after performing the anisotropic etching process, performing the plasma dry etching process.
In the similar field of endeavor of semiconductor manufacturing, Figs. 13-18 if Jang disclose wherein performing the second etching process comprises performing multiple etching cycles (Figs. 14-16, “the etching of gate electrode 56 includes a plurality of deposition-etching cycles, each including a dielectric-deposition process, a dielectric breaking process, an etching process to extend trench 74 down”, ¶ [0039]), wherein each of the multiple etching cycles is performed by:
forming a passivation layer along sidewalls and a bottom of the recess (Fig. 14, “a deposition process is performed, which results in the deposition of dielectric layer 76”, ¶ [0036]);
performing an anisotropic etching process to remove the passivation layer from the bottom of the recess (Fig. 15, “a dielectric breaking process is performed, so that the bottom portion of dielectric layer 76 at the bottom of trench 74 is removed in an anisotropic etching”, ¶ [0037]); and
after performing the anisotropic etching process, performing another etching process (Fig. 16, “another etching process is performed to extend trench 74 deeper into gate electrode 56”, ¶ [0038]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Lin to include the multiple etching cycles as disclosed by Jang, to obtain the desired device characteristics (see Jang, ¶ [0043]).
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 20210126113 A1) and Wang (US 20200006075 A1) in further view of Jang (US 20200135472 A1).
Regarding claim 24, Lin and Wang together disclose the method of claim 14 as applied above, and Figs. 1 and 3A-11B of Lin further disclose removing the exposed first channel regions.
Lin fails to disclose performing a plurality of etching cycles, wherein each of the plurality of etching cycles is performed by:
forming a passivation layer along sidewalls and a bottom of the recess;
removing the passivation layer from the bottom of the recess by performing an anisotropic etching process; and
after performing the anisotropic etching process, performing the plasma dry etching process.
In the similar field of endeavor of semiconductor device manufacturing, Fig. 3A of Wang discloses wherein performing the plasma dry etching process (“the second etching step is an anisotropic etching, such as… plasma etching”, ¶ [0045]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Lin to include the plasma dry etching as disclosed by Wang, to obtain different selectivity in the etching processes (see Wang, ¶ [0045]) and/or because the known technique of plasma dry etching was recognized as part of ordinary capabilities of one skilled in the art. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Wang fails to disclose performing a plurality of etching cycles, wherein each of the plurality of etching cycles is performed by:
forming a passivation layer along sidewalls and a bottom of the recess;
removing the passivation layer from the bottom of the recess by performing an anisotropic etching process; and
after performing the anisotropic etching process, performing another etching process.
In the similar field of endeavor of semiconductor manufacturing, Figs. 13-18 if Jang disclose performing a plurality of etching cycles (Figs. 14-16, “the etching of gate electrode 56 includes a plurality of deposition-etching cycles, each including a dielectric-deposition process, a dielectric breaking process, an etching process to extend trench 74 down”, ¶ [0039]), wherein each of the plurality of etching cycles is performed by:
forming a passivation layer along sidewalls and a bottom of the recess (Fig. 14, “a deposition process is performed, which results in the deposition of dielectric layer 76”, ¶ [0036]);
removing the passivation layer from the bottom of the recess by performing an anisotropic etching process (Fig. 15, “a dielectric breaking process is performed, so that the bottom portion of dielectric layer 76 at the bottom of trench 74 is removed in an anisotropic etching”, ¶ [0037]); and
after performing the anisotropic etching process, performing another etching process (Fig. 16, “another etching process is performed to extend trench 74 deeper into gate electrode 56”, ¶ [0038]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Lin to include the multiple etching cycles as disclosed by Jang, to obtain the desired device characteristics (see Jang, ¶ [0043]).
Regarding claim 25, Lin, Wang and Jang together disclose the method of claim 24 as applied above, and Figs. 11A-11B of Lin further disclose wherein the wet etching process (Figs. 11A-11B) removes an upper portion (“etch the excess dielectric material, edge portions of the cut-metal gate structures 109, the gate cap 801, and the gate electrode 107”, ¶ [0096]) of the segment of the gate structure (107, 703), wherein removing the segment of the gate structure further comprises, after performing the wet etching process, performing another etching process to remove a lower portion of the segment of the gate structure (Fig. 12A-12B, “another etching process is performed to remove the materials of the gate dielectric 703 within the third opening 1003 and to expose the nanostructures 701”, ¶ [0097]).
Lin fails to disclose the other etching process is a plasma dry etching process.
In the similar field of endeavor of semiconductor device manufacturing, Fig. 3A of Wang discloses the other etching process comprises a plasma dry etching process (“the second etching step is an anisotropic etching, such as… plasma etching”, ¶ [0045]).
It would have been obvious to one of ordinary skill in the art before the time of the effective filling date of the invention to modify the method of Lin to include the plasma dry etching as disclosed by Wang, to obtain different selectivity in the etching processes (see Wang, ¶ [0045]) and/or because the known technique of plasma dry etching was recognized as part of ordinary capabilities of one skilled in the art. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Conclusion
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/C.A.N./ Examiner, Art Unit 2893
/YARA B GREEN/ Supervisor Patent Examiner, Art Unit 2893