DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
The Amendment filed on 1/20/2026, responding to the Office action mailed on 10/17/25, has been entered into the record. The present Office action is made with all the suggested amendments being fully considered. Accordingly, claims 1-20 are pending in this application.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zang (CN 108695230 A)
Re Claim 1 Zang teaches a fabrication method (FIG. 2), comprising:
forming, on a substrate (14, page 5 par 1), an epitaxial stack (page 6 par 3) comprising at least one sacrificial epitaxial layer (18) and at least one channel epitaxial layer (16);
forming a plurality of fins in the epitaxial stack (20, page 6 par 4);
performing, prior to shallow trench isolation (36, FIG. 4, page 7 par 4) (STI) formation, tuning operations (Page 7 par 3, more of 18 etched than 16 to create room for 34, FIG. 3) to control a lateral width of the sacrificial epitaxial layer (18) in the fins (20) to not exceed a width of the channel epitaxial layer (16, page 8 par 2) in the fins after expansion of the sacrificial epitaxial layer during subsequent STI formation (36, FIG. 4).
forming a sacrificial gate stack on channel regions of the fins (24, page 7 par 1);
forming gate sidewall spacers on sidewalls (30, page 8 par 2) of the sacrificial gate stack (24);
forming inner spacers (34, page 7 par 3) around the sacrificial epitaxial layer (18) and the channel epitaxial layer (16) in the fins (20);
forming source/drain features (40, page 7 last par);
removing the sacrificial gate stack (24) and sacrificial epitaxial layer (18) in the fins (20); and
forming a metal gate (42, page 8 par 3) to replace the sacrificial gate stack (24) and sacrificial epitaxial layer (18), wherein the metal gate (42) is shielded from the source/drain features (400 by the gate sidewall spacers (30) and the inner spacers (34, FIG. 5).
Re Claim 2 Zang teaches the fabrication method of claim 1, wherein performing tuning operations comprises etching sidewalls (page 7 par 3) of the sacrificial epitaxial layer (18, FIG. 3).
Re Claim 10 Zang teaches a method (FIG. 2) of forming a semiconductor device, comprising:
forming, on a substrate (14, page 5 par 1), an epitaxial stack (page 6 par 3) comprising a plurality of sacrificial epitaxial layers (18) and a plurality of channel epitaxial layers (16);
forming a plurality of fins (20,page 6 par 4) in the epitaxial stack (16/18);
etching sidewalls (Page 6 par 3) of the sacrificial epitaxial layers (18), prior to shallow trench isolation (STI) formation (FIG. 3), to control a lateral width of the sacrificial epitaxial layers (18) in the fins to not exceed a width of the channel epitaxial layers (16) in the fins after expansion of the sacrificial epitaxial layers (18) during subsequent STI formation (36, page 7 par 4, FIG. 4);
forming a sacrificial gate stack (24, page 7 par 1) on channel regions of the fins (20);
forming gate sidewall spacers (30, page 7 par 1) on sidewalls of the sacrificial gate stack (24);
forming inner spacers (34, page 7 par 3) around the sacrificial epitaxial layers (18) and the channel epitaxial layers (16) in the fins (20);
forming source/drain features (40, page 7 last par);
removing the sacrificial gate stack (24) and sacrificial epitaxial layers in the fins (18); and
forming a metal gate (42, page 8 par 3) to replace the sacrificial gate stack (24) and sacrificial epitaxial layers (18), wherein the metal gate (42) is shielded from the source/drain features (40) by the gate sidewall spacers (30) and the inner spacers (34, FIG. 5).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Zang (CN 108695230 A) in view of Zheng (CN 103515289 A).
Re Claim 3 Zang teaches the fabrication method of claim 1, further comprising forming isolation features (36, page 7 last par) between the plurality of fins (20), wherein the width of the sacrificial epitaxial layer (18) does not expand beyond the width of the channel epitaxial layer (16).
Zang does not teach performing tuning operations comprises adjusting temperatures used during heat treatment to form the isolation features.
Zheng [0014] states, “Optionally, in the forming method of the shallow trench isolation structure, said heat treatment process comprises two stages: steam annealing and dry annealing. the technological parameter of the steam annealing is H2 flow rate is 2 to 7 litre/minute, the 02 flow is 5 to 10 litre/min, the time is 5 to 50 min, the temperature range is 500 to 800 degrees centigrade. process parameters of the dry annealing is N2 flow rate is 7 to 20 litre/minute, and time is 30 to 180 min, the temperature range is 1000 to 1200 degrees centigrade.”
The ordinary artisan would have been motivated to modify Zheng in combination with Zang in the above manner for the motivation of adjusting temperatures while forming the isolation trenches to allow the trenches to optimally integrate into the chip with the other layers in the device. [0005] states, “The purpose of the invention is to shallow trench isolation structure provides a method for forming shallow trench isolation structure, which avoids the formed in forming the fragile surface, improve the isolation performance of forming shallow trench isolation structure, thereby improving the performance of the semiconductor device is formed.”
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Zheng into the structure of Zang.
Re Claim 16 Zang teaches a method (FIG. 2) of forming a semiconductor device, comprising:
forming, on a substrate (14, page 5 par 1), an epitaxial stack (page 6 par 3) comprising a plurality of sacrificial epitaxial layers (18) and a plurality of channel epitaxial layers (16);
forming a plurality of fins (20) in the epitaxial stack (page 6 par 4);
forming isolation features (36, page 5) between the plurality of fins (20), forming the isolation features (36) to control a lateral width of the sacrificial epitaxial layers (18) from expanding beyond a width of the channel epitaxial layers (16) after formation of the isolation features (FIG. 4);
forming a sacrificial gate stack (24, page 7 par 1) on channel regions of the fins (20);
forming gate sidewall spacers (30, page 7 par 1) on sidewalls of the sacrificial gate stack (24);
forming inner spacers (34, page 7 par 3) around the sacrificial epitaxial layers (18) and the channel epitaxial layers (16) in the fins (20);
forming source/drain features (40, page 7 last par);
removing the sacrificial gate stack (24) and sacrificial epitaxial layers (18) in the fins (20); and
forming a metal gate (42, page 8 par 3) to replace the sacrificial gate stack (24) and sacrificial epitaxial layers (18), wherein the metal gate (42) is shielded from the source/drain features (40) by the gate sidewall spacers (30) and the inner spacers (34, FIG. 5).
Zang does not teach adjusting heat- treatment temperatures.
Zheng [0014] states, “Optionally, in the forming method of the shallow trench isolation structure, said heat treatment process comprises two stages: steam annealing and dry annealing. the technological parameter of the steam annealing is H2 flow rate is 2 to 7 litre/minute, the 02 flow is 5 to 10 litre/min, the time is 5 to 50 min, the temperature range is 500 to 800 degrees centigrade. process parameters of the dry annealing is N2 flow rate is 7 to 20 litre/minute, and time is 30 to 180 min, the temperature range is 1000 to 1200 degrees centigrade.”
The ordinary artisan would have been motivated to modify Zheng in combination with Zang in the above manner for the motivation of adjusting temperatures while forming the isolation trenches to allow the trenches to optimally integrate into the chip with the other layers in the device. [0005] states, “The purpose of the invention is to shallow trench isolation structure provides a method for forming shallow trench isolation structure, which avoids the formed in forming the fragile surface, improve the isolation performance of forming shallow trench isolation structure, thereby improving the performance of the semiconductor device is formed.”
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Zheng into the structure of Zang.
Claims 4 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Zang (CN 108695230 A) in view of Xu (WO 2023035270 A1).
Re Claim 4 Zang teaches the fabrication method of claim 1, but does not teach forming the gate spacer and forming the inner spacer comprise forming a sacrificial gate stack on channel regions of the fins with a sacrificial gate residue that does not extend beyond 3 nanometers (nm) horizontally in an x- direction or a y-direction.
Xu teaches forming a sacrificial gate stack (page 5, 2023, “dummy gate”) on channel regions (2022) of the fins comprises forming a sacrificial gate stack (2023) on channel regions (2022) of the fins with a sacrificial gate residue (2024) that does not extend beyond 3 nanometers (nm) horizontally in an x-direction or a y-direction (use left/right as x direction, page 11 par 7 states, “…the thickness of the single crystal silicon layer 2024 is 2-3 nm.” The layer will not extend beyond 3nm in the x direction since it is 2-3nm thick).
The ordinary artisan would have been motivated to modify Xu in combination with Zang in the above manner for the motivation of adding a sacrificial gate and residue layer over the channels to help optimize the performance of the source and drain regions. Page 2 par 4 sates, “The invention provides an epitaxial preparation method for the source and drain of the ring gate structure and the ring gate structure to solve the problem of stress relaxation in the source/drain region.”
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Xu into the structure of Zang.
Re Claim 12 Zang teaches the method of claim 10, but does not teach forming a sacrificial gate stack on channel regions of the fins comprises forming a sacrificial gate stack on channel regions of the fins with a sacrificial gate residue that does not extend beyond 3 nanometers (nm) horizontally in an x-direction or a y-direction.
Xu teaches forming a sacrificial gate stack (page 5, 2023, “dummy gate”) on channel regions (2022) of the fins comprises forming a sacrificial gate stack (2023) on channel regions (2022) of the fins with a sacrificial gate residue (2024) that does not extend beyond 3 nanometers (nm) horizontally in an x-direction or a y-direction (use left/right as x direction, page 11 par 7 states, “…the thickness of the single crystal silicon layer 2024 is 2-3 nm.” The layer will not extend beyond 3nm in the x direction since it is 2-3nm thick).
The ordinary artisan would have been motivated to modify Xu in combination with Zang in the above manner for the motivation of adding a sacrificial gate and residue layer over the channels to help optimize the performance of the source and drain regions. Page 2 par 4 sates, “The invention provides an epitaxial preparation method for the source and drain of the ring gate structure and the ring gate structure to solve the problem of stress relaxation in the source/drain region.”
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Xu into the structure of Zang.
Claims 5-6 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Zang (CN 108695230 A) in view of Yang (US 11276604 B1).
Re Claim 5 Zang teaches the fabrication method of claim 1, but does not teach forming the gate spacer and forming the inner spacer comprise forming the gate spacer and the inner spacer with a gap between the gate spacer and the inner spacer.
Yang teaches forming the gate spacer (page 15 par 2, 1358, “third gate spacer”) and forming the inner spacer (page 14 par 3, 966, “etch stop layer”) comprise forming the gate spacer (1358) and the inner spacer (966) with a gap (page 16 par 3, 1864) between the gate spacer (1358) and the inner spacer (966, FIG. 18B).
The ordinary artisan would have been motivated to modify Yang in combination with Zang in the above manner for the motivation of forming a gap between the inner spacer and gate spacer to ensure the fins structures do not create a short circuit and that the device functions in an optimally.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Yang into the structure of Zang.
Re Claim 6 Zang in view of Yang teaches the fabrication method of claim 5, but does not explicitly teach the gap between the gate spacer and the inner spacer is approximately 0.3 nm to approximately 2 nm.
Yang teaches the gap (1864/1964) between the gate spacer (1358) and the inner spacer (966) ranges from 2nm to 4nm (page 17 par 1 states, “…sealing air gaps 1864 to form air spacers 1964. In some embodiments, air spacers 1964 can have a width along an X-axis ranging from about 2 nm to about 4 nm…”)
The ordinary artisan would have been motivated to modify Yang in combination with Zang in view of Yang in the above manner for the motivation of finding the ideal gap dimension. Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach ideal gap length.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Yang into the structure of Zang in view of Yang.
Re Claim 13 Zang teaches the method of claim 10, but does not teach forming the gate spacer and forming the inner spacer comprise forming the gate spacer and the inner spacer with a gap between the gate spacer and the inner spacer that is small enough to prevent a short circuit between the metal gate and a metal drain in the source/drain region.
Yang teaches forming the gate spacer (1358, col 14 par 3) and forming the inner spacer (966, “etch stop layer”, col 14 par 2) comprise forming the gate spacer (1358) and the inner spacer (966) with a gap (1964, col 14 last par) between the gate spacer (1358) and the inner spacer (966) that is small enough to prevent a short circuit (1964 is a gap and acts as an open circuit and therefore cannot be a short circuit) between the metal gate (1684, col 14 par1) and a metal drain (2098 col 15 par 0) in the source/drain region (2090, FIG. 20A).
The ordinary artisan would have been motivated to modify Yang in combination with Zang in the above manner for the motivation of forming a gap between the inner spacer and gate spacer to ensure the fins structures do not create a short circuit and that the device functions in an optimally.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Yang into the structure of Zang.
Re Claim 14 Zang in view of Yang teaches the method of claim 10, wherein forming the gate spacer (Yang, 1358, col 14 par 3) and forming the inner spacer (966, “etch stop layer”, col 14 par 2) comprise forming the gate spacer (1358) and the inner spacer (966) with a critical dimension stop layer (1964, col 14 last par) formed by the gate spacer (1358) and the inner spacer (966) that is large enough to prevent a short circuit (1964 is a gap and acts as an open circuit and therefore cannot be a short circuit) between the metal gate (1684, col 14 par1) and a metal drain (2098 col 15 par 0) in the source/drain region (2090, FIG. 20A).
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Zang (CN 108695230 A) in view of Huang (CN 114334961 A).
Re Claim 7 Zang teaches the fabrication method of claim 1, but does not teach forming the gate spacer and forming the inner spacer comprise forming the gate spacer and the inner spacer with a critical dimension stop layer formed by the gate spacer and the inner spacer.
Huang teaches forming the gate spacer (page 4, 222) and forming the inner spacer (226) comprise forming the gate spacer (222) and the inner spacer (226) with a critical dimension stop layer (232) formed by the gate spacer (222) and the inner spacer (226, FIG. 2J).
The ordinary artisan would have been motivated to modify Huang in combination with Chang in view of Zang in the above manner for the motivation of adding spacers around the source/drain regions to isolate the regions and help the device maintain optimal current levels. Page 14 par 3 states, “In addition, the spacer structure disclosed in the embodiment of the present invention can provide better isolation between the source/drain conductive layer, or between the gate conductive layer and the other metal regions.”
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Huang into the structure of Zang.
Re Claim 8 Zang in view of Huang teaches the fabrication method of claim 7, but does not explicitly teach the critical dimension stop layer provides a block wall of approximately 3 nm to approximately 10 nm.
Huang teaches the critical dimension stop layer (232) provides a block wall in the range of about .5nm to about 20nm. (page 12 par 1 states, “…the width of the air gap 232 is about 0.5nm to about 20nm.”)
The ordinary artisan would have been motivated to modify Huang in combination with Zang in view of Huang in the above manner for the motivation of finding ideal critical dimension stop layer length. Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach optimal critical dimension stop layer dimensions.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Huang into the structure of Zang in view of Huang.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Zang et al. (CN 108695230 A) in view of Lin (US 20210134982 A1).
Re Claim 11 Zang teaches the method of claim 10, but does not teach etching the sidewalls of the sacrificial epitaxial layers comprises performing a plasma etch with an etch gas of CH4, CHF3, HBr, Cl2, and/or H2;
a passivation gas for selectivity of N2 and/or O2;
a dilute gas of He, Ar, and/or N2;
at a power of approximately 10W to approximately 4000W;
at a pressure of approximately 1 mTorr to approximately 800 mTorr; and
with a gas Flow of approximately 20 sccm to approximately 3000 sccm.
Lin teaches etching the sidewalls of the sacrificial epitaxial layers comprises performing a plasma etch [0060] with an etch gas H2 [0059];
a passivation gas for selectivity of N2 [0059];
a dilute gas of He [0059];
at a power of approximately 10W to approximately 3000W [0060];
at a pressure of approximately 1 mTorr to approximately 800 mTorr [0060]; and
with a gas Flow of approximately 10 sccm to approximately 5000 sccm [0060].
The ordinary artisan would have been motivated to modify Lin in combination with Zang the above manner for the motivation of using ideal plasma etch settings. [0059] states, “The passivation gas is used to tune the etching selectivity of the second etching process, so as to advantageously reduce or avoid damage to, e.g., the gate spacers 87 and the first ILD 90 during the second etching process.” Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach ideal etch pressure, power, and gas flow rate.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Lin into the structure of Zang.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Zang et al. (CN 108695230 A) in view of Lee (US 9666687 B1) as applied to claim 16 above, and further in view of Xu (WO 2023035270 A1).
Re Claim 17 Zang in view of Lee teaches the method of claim 16, but does not teach forming a sacrificial gate stack on channel regions of the fins comprises forming a sacrificial gate stack on channel regions of the fins with a sacrificial gate residue that does not extend beyond 3 nanometers (nm) horizontally in an x-direction or a y-direction.
Xu teaches forming a sacrificial gate stack (page 5, 2023, “dummy gate”) on channel regions (2022) of the fins comprises forming a sacrificial gate stack (2023) on channel regions (2022) of the fins with a sacrificial gate residue (2024) that does not extend beyond 3 nanometers (nm) horizontally in an x-direction or a y-direction (use left/right as x direction, page 11 par 7 states, “…the thickness of the single crystal silicon layer 2024 is 2-3 nm.” The layer will not extend beyond 3nm in the x direction since it is 2-3nm thick).
The ordinary artisan would have been motivated to modify Xu in combination with Zang in view of Lee in the above manner for the motivation of adding a sacrificial gate and residue layer over the channels to help optimize the performance of the source and drain regions. Page 2 par 4 sates, “The invention provides an epitaxial preparation method for the source and drain of the ring gate structure and the ring gate structure to solve the problem of stress relaxation in the source/drain region.”
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Xu into the structure of Zang in view of Lee.
Claims 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Zang et al. (CN 108695230 A) in view of Lee (US 9666687 B1) as applied to claim 16 above, and further in view of Yang (US 11276604 B1).
Re Claim 18 Zang in view of Lee teaches the method of claim 16, but does not teach forming the gate spacer and forming the inner spacer comprise forming the gate spacer and the inner spacer with a gap between the gate spacer and the inner spacer.
Yang teaches forming the gate spacer (1358, col 14 par 3) and forming the inner spacer (966, “etch stop layer”, col 14 par 2) comprise forming the gate spacer (1358) and the inner spacer (966) with a gap (1964, col 14 last par) between the gate spacer (1358) and the inner spacer (966, FIG. 20A).
The ordinary artisan would have been motivated to modify Yang in combination with Zang in view of Lee in the above manner for the motivation of forming a gap between the inner spacer and gate spacer to ensure the fins structures do not create a short circuit and that the device functions in an optimally.
It would have been obvious to one ordinary skill in the art before the effective filing date of claimed the invention to incorporate the teaching as taught by Yang into the structure of Zang in view of Lee.
Re Claims 19 Zang in view of Lee and Yang teaches the method of claim 16, wherein forming the gate spacer (Yang, 1358, col 14 par 3) and forming the inner spacer (966, “etch stop layer”, col 14 par 2) comprise forming the gate spacer (1358) and the inner spacer (966) with a critical dimension stop layer (1964, col 14 last par) formed by the gate spacer (1358) and the inner spacer (966, FIG. 20A).
Allowable Subject Matter
Claims 9, 15, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claims 1-8, 10-14, and 16-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH MARK SIPLING whose telephone number is (571)272-3269. The examiner can normally be reached 10 AM - 6 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KENNETH MARK SIPLING/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 5/28/26
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