DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 9/30/25 has been entered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 21-27 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Li et al. (US PGPub 2010/0289098, hereinafter referred to as “Li”).
Li discloses the semiconductor method as claimed. See figures 1-10 and corresponding text, where Li teaches, in claim 21, a method of fabricating a semiconductor structure, comprising:
providing a substrate (102) having a first metal layer with a first metal line in a memory region (108) and a second metal line coplanar with the first metal line and disposed in a logic region (110); (figure 1; [0022])
providing a memory element having a bottom electrode (302), a magnetic tunneling junction (MTJ) layer (304) and a top electrode (502) over the first metal line (202, 204); (figures 2 and 3; [0023-0025])
depositing a first dielectric material (602) surrounding the memory element; (figure 6; [0030])
depositing a second dielectric material (604) over the first dielectric material in the memory region and extending to the logic region; (figure 6; [0030-0031])
forming a first trench (704) in the second dielectric material and the first dielectric material exposing a surface of the top electrode (502) and forming a second trench (702) in the second dielectric material of the logic region, wherein the second trench is a dual damascene trench (702) having a via region (704, 706) and a metal line region; (figure 7; [0032-0033])
filling the first trench and the second trench with conductive material; (figure 7; [0032-0033]) and planarizing the conductive material (figure 7; [0032-0033]);
wherein after the depositing the second dielectric material, an uppermost surface of the second dielectric material is lower in the logic region than an uppermost surface of the second dielectric material in the memory region (the examiner views that the thickness of the film will remain constant throughout such that the topography height, prior to planarization, would be greater in the memory region versus the logic region. For example, the second insulating layer 412 (Fig. 5) formed from planarizing the ILD layer (Fig. 4).
Li teaches, in claim 22, wherein the depositing the first dielectric material includes depositing the first dielectric material extending to the logic region. (figure 6; [0030-0031])
Li teaches, in claim 23, wherein the depositing the first dielectric material extending to the logic region includes depositing the first dielectric material directly on a top surface of the second metal line. (figure 6; [0030-0031])
Li teaches, in claim 24, wherein after the depositing the second dielectric material and prior to forming the first trench and the second trench, an uppermost surface of the second dielectric material is lower in the logic region than in an uppermost surface of the second dielectric material in the memory region. (figure 7; [0032-0033])
Li teaches, in claim 25, wherein after the planarizing, an uppermost surface of the second dielectric material in the logic region is substantially coplanar with an uppermost surface of the second dielectric material in the memory region. (figure 7; [0032-0033])
Li teaches, in claim 26, wherein the planarizing the conductive material removes a portion of the second dielectric material (figures 6 and 7; [0030-0033]).
Li teaches, in claim 27, wherein the depositing the first dielectric material includes depositing the first dielectric material on the surface of the top electrode and a top surface of the second metal line. (figure 6; [0030-0031])
REASONS FOR ALLOWANCE
Claims 28-40 are allowed over the prior art of record.
The following is an examiner’s statement of reasons for allowance: The closest prior art of record and to the examiner’s knowledge does not suggest or render obvious a semiconductor structure, particularly characterized by the top electrode having a bottom surface engaging the MTJ, a top surface, a first sidewall extending from the bottom surface to the top surface, and a second sidewall extending from the bottom surface to the top surface and opposing the first sidewall; and
a second portion of the (N+1)th metal layer over and engaging the top surface of the top electrode and an upper portion of the first sidewall and the second sidewall, N being a nonzero, positive integer;
a third dielectric layer interfacing sidewalls of a bottom portion of the first sidewall and the second sidewall of the top electrode;
the first dielectric layer interfacing sidewalls a middle portion of the first sidewall and the second sidewall of the top electrode, as detailed in claim 28. Claims 29-33 depends from claim 28.
The closest prior art of record and to the examiner’s knowledge does not suggest or render obvious a semiconductor structure, particularly characterized by such that the first dielectric layer has a first circular edge defining the circular configuration of the first dielectric layer and the third dielectric layer has a second circular edge defining the circular configuration of the second dielectric layer, the first dielectric layer being disposed within the second circular edge of the third dielectric layer, as detailed in claim 34. Claims 35-40 depends from claim 40.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant's arguments filed 9/30/25 have been fully considered but they are not persuasive. In the Remarks applicant raises the clear issue as to whether that wherein after the depositing the second dielectric material, and uppermost surface of the second dielectric material is lower in the logic region than an uppermost surface of the second dielectric material in the memory.
The examiner views that the thickness of the film will remain constant throughout such that the topography height, prior to planarization, would be greater in the memory region versus the logic region. For example, the second insulating layer 412 (Fig. 5) formed from planarizing the ILD layer (Fig. 4).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STANETTA D ISAAC whose telephone number is (571)272-1671. The examiner can normally be reached M-F 10-6.
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/STANETTA D ISAAC/Examiner, Art Unit 2898 February 21, 2026