DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 11/25/2026 has been entered.
Response to Amendment
Applicant’s amendment filed on 11/25/2025 is acknowledged. Claims 1, 11, and 16 have been amended. Claims 3, 15 have been canceled. Claims 21-22 have been added.
Response to Arguments
Applicant’s arguments with respect to claims 11-14, 16-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant's arguments filed on 11/25/2025 regarding claims 1-2, 4-10 have been fully considered but they are not persuasive. The amendment of claim 1 has not overcome the prior art of record. The phrase “bonding structure” can be used to refer to a collection, or an array of solder bumps, not just a single solder bump. In the case of reference Kim, the first bonding structure is the array of bumps 113 and the second bonding structure is the array of bumps 210. As can be seen in Fig. 4A of Kim, the array of bumps 210 surrounds the array of bumps 113, thus, the array of bumps 210 is wider than the array of bumps 113.
The rejection of claims 1-2, 4-10 are maintained.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2016/0056103 A1) in view of Jang et al. (US 2014/0339708 A1) and Karpur et al. (US 2011/0147912 A1).
Regarding claim 1, Kim teaches a package structure (5 in Figs. 1A-1B, and 4A), comprising:
a redistribution structure (lower substrate 110 in Fig. 4A);
a semiconductor chip (120) bonded to the redistribution structure through a first bonding structure (array of bumps 113);
an interposer substrate (200) bonded to the redistribution structure through a second bonding structure (array of bumps 210), wherein the second bonding structure is wider than the first bonding structure (as shown in Fig. 4A, the lateral dimensions of the array of bumps 210 is larger than those of the array of bumps 113), and a bottommost surface of the interposer substrate is spaced apart from a topmost surface of the redistribution structure (as shown in Fig. 4B).
But Kim does not teach that the package structure comprising: an adhesive layer directly on the semiconductor chip, wherein the redistribution structure is wider than the adhesive layer; and a protective layer laterally surrounding the semiconductor chip, wherein a portion of the protective layer is between the interposer substrate and the semiconductor chip.
Jang teaches a package structure (200 in Fig. 2 of Jang) comprising: an upper package (150); a lower package (100) including a semiconductor chip (20) on a redistribution structure (lower package substrate 10 which is a PCB so it includes all the wirings to route the electrical connections from the terminals 22 to the pads 16); and an adhesive layer (44) directly on the semiconductor chip.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the adhesive layer (44 of Jang) in Kim in order to facilitate more heat to escape from the semiconductor chip of Kim.
As incorporated, since the adhesive layer is smaller than the top area of the chip, the redistribution structure is wider than the adhesive layer.
But Kim in view of Jang does not teach that the package structure comprising: a protective layer laterally surrounding the semiconductor chip, wherein a portion of the protective layer is between the interposer substrate and the semiconductor chip.
Karpur teaches a method of forming package structure (Figs. 10A-10C of Karpur) comprising: attaching a semiconductor chip (11) to a lower redistribution layer (43); dispensing an underfill layer (44) to secure the chip; disposing a stiffener (44) surrounding the semiconductor chip; dispensing a curable protective layer (46) filling the space between the chip and the stiffener; curing the layers by the thermal process (as described in [0054]-[0055] of Karpur).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the protective layer (46) of Karpur on the semiconductor chip’s sidewalls and the interposer substrate, as disclosed by Karpur, in order to further stiffening the package.
As incorporated, the stiffener 45 of Karpur is analogous to interposer substrate 200 of Kim. Since the uncured protective layer is a liquid material, it could flow under the interposer substrate (as it flows under the curved corners of the stiffener). Hence, the protective layer 45 is between the interposer substrate and the semiconductor chip.
Regarding claim 2, Kim-Jang-Karpur teaches all limitations of the package structure as claimed in claim 1, and also teaches wherein the interposer substrate has interior sidewalls (H in Figs. 1A and 4A of Kim) laterally surrounding the semiconductor chip, and the semiconductor chip is as high as or higher than the interposer substrate (as shown in Figs. 1A and 4A of Kim).
Regarding claim 4, Kim-Jang-Karpur teaches all limitations of the package structure as claimed in claim 2, and also teaches wherein the interposer substrate is spaced apart from the semiconductor chip (as shown in Figs. 1A and 4A of Kim).
Regarding claim 5, Kim-Jang-Karpur teaches all limitations of the package structure as claimed in claim 4, and also teaches wherein the interposer substrate laterally and continuously surrounds the semiconductor chip (as shown in Figs. 1A and 4A of Kim).
Regarding claim 6, Kim-Jang-Karpur teaches all limitations of the package structure as claimed in claim 4, and also teaches wherein the protective layer is in direct contact with the interior sidewalls of the interposer substrate (as combined in claim 1 above).
Regarding claim 9, Kim-Jang-Karpur teaches all limitations of the package structure as claimed in claim 1, and further comprising: a second redistribution structure (310 in Fig. 4A of Kim) bonded to the interposer substrate, wherein the adhesive layer is between the semiconductor chip and the second redistribution structure (as combined in claim 1 above).
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Jang and Karpur, as applied to claim 1 above, and further in view of Jeong et al. (US 2016/0336296 A1).
Regarding claim 7, Kim-Jang-Karpur teaches all limitations of the package structure as claimed in claim 1, but does not teach the package structure further comprising a second semiconductor chip over the redistribution structure.
Jeong teaches a package (Figs. 20-21 of Jeong) wherein a first semiconductor chip (120) and a second semiconductor chip (122) are disposed in the same opening (100X) of a frame (110) on a redistribution layer (130-140-160).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed a second semiconductor chip in the same opening as the first semiconductor chip of Kim-Jang in order to increase performance of the package structure.
Regarding claim 8, Kim-Jang-Karpur teaches all limitations of the package structure as claimed in claim 7, and also teaches wherein the interposer substrate has interior sidewalls continuously surrounding the semiconductor chip and the second semiconductor chip (as shown in Fig. 1A of Kim and Fig. 21 of Jeong).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Jang and Karpur, and further in view of Lau et al. (US 2010/0213600 A1).
Regarding claim 10, Kim-Jang-Karpur teaches all limitations of the package structure as claimed in claim 1, but does not teach wherein the adhesive layer has an area as large as that of a top surface of the semiconductor chip.
Lau teaches a package structure (100 in Fig. 1 of Lau) comprising: a lower package substrate (108); a semiconductor chip (118A-B) on the lower package substrate; an upper substrate (102 and 114) on top of the first and second semiconductor chips; a thermal interface material (TIM) layer (116) on each of the first and second semiconductor chips, wherein the TIM layer has an area as large as that of a top surface of the semiconductor chip (see Fig. 1 of Lau).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the TIM layer having an area as large as that of a top surface of the semiconductor chip as disclosed by Lau in order to maximize the amount of heat transferred out of the semiconductor chip.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Jang and Karpur, and further in view of Yeom et al. (US 2013/0161836 A1).
Regarding claim 21, Kim-Jang-Karpur teaches all limitations of the package structure as claimed in claim 1, but does not teach wherein a top of the protective layer is substantially level with a top of the interposer substrate.
Yeom teaches a package structure (Fig. 1 of Yeom) comprising: a redistribution structure (10); a chip (30) bonded to the redistribution structure through a first solder bump (70); an interposer substrate (20) surrounding the chip; a protective layer (40) surrounding the chip, and wherein a top of the protective layer is substantially level with a top of the interposer substrate (as shown in Fig. 1 of Yeom).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the protective layer of Kim-Jang-Karpur with a top surface level with a top surface of the interposer substrate in order to provide more protection and better secure the chip together with the interposer.
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Wu (US 2014/0264811 A1) in view of Marimuthu et al. (US 2010/0133704 A1), and Jang.
Regarding claim 11, Wu teaches a package structure (package in Fig. 1A-1B, and 4A), comprising:
a redistribution structure (200, as shown in Figs. 1 & 6);
an interposer substrate (100) bonded to the redistribution structure through a first solder bump (216B);
a semiconductor chip (300) bonded to the redistribution structure through a second solder bump (216A), wherein the first solder bump is wider than the second solder bump (as shown in Fig. 1 & 6), and interior sidewalls (100’ and 44’ in Fig. 1) of the interposer substrate laterally surround the semiconductor chip;
and a protective layer (48) laterally surrounding the semiconductor chip, wherein the protective layer has a sidewall beside the interposer substrate (as shown in Fig. 6 of Wu), and the redistribution structure extends across the sidewall of the protective layer (as shown in Fig. 6 of Wu).
But Kim does not teach that the first solder bump and the second solder bump are tin-containing solder bumps; and that the package structure comprising: an adhesive layer directly on the semiconductor chip, wherein opposite edges of the adhesive layer is laterally between opposite edges of the redistribution structure.
Marimuthu teaches solder bumps are made of Sn-containing materials such as Sn (see [0043] of Marimuthu).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the solder bumps of Wu from Sn-containing materials since this is a common material for solder bumps, and also safe and highly conductive.
But Wu in view of Marimuthu does not teach that the package structure comprising: an adhesive layer directly on the semiconductor chip, wherein opposite edges of the adhesive layer is laterally between opposite edges of the redistribution structure.
Jang teaches a package structure (200 in Fig. 2 of Jang) comprising: an upper package (150); a lower package (100) including a semiconductor chip (20) on a redistribution structure (lower package substrate 10 which is a PCB so it includes all the wirings to route the electrical connections from the terminals 22 to the pads 16); and an adhesive layer (44) directly on the semiconductor chip.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the adhesive layer (44 of Jang) in Wu in order to facilitate more heat to escape from the semiconductor chip of Kim.
As incorporated, since the adhesive layer is smaller than the top area of the chip, the opposite edges of the adhesive layer is laterally between opposite edges of the redistribution structure.
Regarding claim 12, Wu-Marimuthu-Jang teaches all limitations of the package structure as claimed in claim 11, and further comprising: a second redistribution structure (310 in Fig. 4A of Kim) bonded to the interposer substrate, wherein the adhesive layer is between the second redistribution structure and the semiconductor chip (as shown in Fig. 4A of Kim).
Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Marimuthu, and Jang, as applied to claim 12 above, and further in view of Jeong.
Regarding claim 13, Wu-Marimuthu-Jang teaches all limitations of the package structure as claimed in claim 12, but does not teach the package structure further comprising: a second semiconductor chip between the redistribution structure and the second redistribution structure.
Jeong teaches a package (Figs. 20-21 of Jeong) wherein a first semiconductor chip (120) and a second semiconductor chip (122) are disposed in the same opening (100X) of a frame (110) on a redistribution layer (130-140-160).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed a second semiconductor chip in the same opening as the first semiconductor chip of Kim-Jang in order to increase performance of the package structure.
Regarding claim 14, Wu-Marimuthu-Jang-Jeong teaches all limitations of the package structure as claimed in claim 13, and also teaches wherein the interposer substrate has a hole (opening 128 in Fig. 1 of Wu), and sidewalls of the hole laterally surround the semiconductor chip and the second semiconductor chip (as shown in Fig. 1A of Kim).
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Marimuthu, and Jang, as applied to claim 11 above, and further in view of Yeom.
Regarding claim 22, Kim-Marimuthu-Jang teaches all limitations the package structure as claimed in claim 11, but does not teach wherein tops of the protective layer and the interposer substrate are substantially at the same height level.
Yeom teaches a package structure (Fig. 1 of Yeom) comprising: a redistribution structure (10); a chip (30) bonded to the redistribution structure through a first solder bump (70); an interposer substrate (20) surrounding the chip; a protective layer (40) surrounding the chip, and wherein a top of the protective layer is substantially level with a top of the interposer substrate (as shown in Fig. 1 of Yeom).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the protective layer of Wu-Marimuthu-Jang with a top surface level with a top surface of the interposer substrate in order to provide more protection and better secure the chip together with the interposer.
Claims 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Jang.
Regarding claim 16, Wu teaches a package structure (package in Fig. 6), comprising:
a redistribution structure (200, as shown in Fig. 1 & 6);
a semiconductor chip (320) bonded to the redistribution structure through a first solder bump (216A, as shown in Fig. 1 & 6);
a second redistribution structure (420) over the redistribution structure;
an interposer substrate (100) between the redistribution structure and the second redistribution structure, wherein the interposer is bonded to the redistribution structure through a second solder bump (216B, as shown in Fig. 1 & 6), and the second solder bump is larger than the first solder bump (as shown in Figs. 1 & 6); and
a protective layer (48 in Fig. 6 of Wu) laterally surrounding the semiconductor chip, wherein interposer substrate laterally surrounds the protective layer, the protective layer has a sidewall beside the semiconductor chip, and the second redistribution structure extends across the sidewall of the protective layer (as shown in Fig. 6 of Wu).
But Wu does not teach that the package structure comprising: an adhesive layer directly on the semiconductor chip; and wherein the adhesive layer is between the semiconductor chip and the second redistribution structure, and the second redistribution structure extends across opposite edges of the adhesive layer.
Jang teaches a package structure (200 in Fig. 2 of Jang) comprising: an upper package (150); a lower package (100) including a semiconductor chip (20) on a redistribution structure (lower package substrate 10 which is a PCB so it includes all the wirings to route the electrical connections from the terminals 22 to the pads 16); and an adhesive layer (44) directly on the semiconductor chip.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the adhesive layer (44 of Jang) in Kim in order to facilitate more heat to escape from the semiconductor chip of Kim.
As incorporated, since the adhesive layer is smaller than the top area of the chip, the redistribution structure is wider than the adhesive layer and the second redistribution structure extends across opposite edges of the adhesive layer.
Regarding claim 17, Wu in view of Jang teaches all limitations of the package structure as claimed in claim 16, and also teaches wherein the interposer substrate has interior sidewalls (100’ and 44’ as shown in Fig. 1 of Wu) laterally surrounding an area where the semiconductor chip is disposed.
Claims 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Jang, and further in view of Jeong.
Regarding claim 18, Wu in view of Jang teaches all limitations of the package structure as claimed in claim 17, but does not teach the package structure further comprising: a second semiconductor chip between the second redistribution structure and the redistribution structure, wherein the interior sidewalls of the interposer substrate laterally surround the area where the semiconductor chip and the second semiconductor chip are disposed.
Jeong teaches a package (Figs. 20-21 of Jeong) wherein a first semiconductor chip (120) and a second semiconductor chip (122) are disposed in the same opening (100X) of a frame (110) on a redistribution layer (130-140-160).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed a second semiconductor chip in the same opening as the first semiconductor chip of Wu-Jang in order to increase performance of the package structure.
Regarding claim 20, Wu in view of Jang teaches all limitations of the package structure as claimed in claim 16, but does not teach the package structure further comprising: a second semiconductor chip between the second redistribution structure and the redistribution structure.
Jeong teaches a package (Figs. 20-21 of Jeong) wherein a first semiconductor chip (120) and a second semiconductor chip (122) are disposed in the same opening (100X) of a frame (110) on a redistribution layer (130-140-160).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed a second semiconductor chip in the same opening as the first semiconductor chip of Wu-Jang in order to increase performance of the package structure.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Wu in view of Jang, and further in view of Lau.
Regarding claim 19, Wu in view of Jang teaches all limitations of the package structure as claimed in claim 16, but does not teach wherein the adhesive layer has an area as large as that of a top surface of the semiconductor chip.
Lau teaches a package structure (100 in Fig. 1 of Lau) comprising: a lower package substrate (108); a semiconductor chip (118A-B) on the lower package substrate; an upper substrate (102 and 114) on top of the first and second semiconductor chips; a thermal interface material (TIM) layer (116) on each of the first and second semiconductor chips, wherein the TIM layer has an area as large as that of a top surface of the semiconductor chip (see Fig. 1 of Lau).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the TIM layer (heat transfer member 44 of Jang) having an area as large as that of a top surface of the semiconductor chip in Wu-Jang’s package as disclosed by Lau in order to maximize the amount of heat transferred out of the semiconductor chip.
Conclusion
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/Tuan A Hoang/ Primary Examiner, Art Unit 2898