DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to because Fig. 8A is in conflict with the specification. Specifically, Fig. 8A has a box labeled 202; however, ¶ 0101 describing Fig. 8A does not mention or describe “202”. Furthermore, TSVs 172 should be above surface 102a, not above surface 102b (¶ 0100-0103, see also TSVs 172 in Fig. 8B). Please correct as appropriate.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10, 13-14, 21, and 24-25 are rejected under 35 U.S.C. 103 as being unpatentable over Ang et al. (“Ang”), US 2019/0096840, in view of Huang et al. (“Huang”), US 20180151537.
Regarding Claim 10, Ang discloses method for forming a package structure (10; ¶ 0008; Figs. 1C-1E), comprising:
forming a first die (300; Fig. 1C; ¶ 0010 “first dies 300”) over a carrier substrate (100; Figs 1C-1E; ¶ 0008 “first carrier 100”), wherein the first die comprises a first substrate (the upper portion of first die 300 closest to surface 300b; Figs. 1C-1E);
forming a buffer layer (500; Figs. 1C-1E; ¶ 0012 “encapsulation material 500”) on the first die (Figs. 1C-1E; ¶ 0012 “a second surface 500b of the encapsulation material 500 is located at a level height higher than both of the rear surfaces 300b of the first dies 300”), wherein the first die is surrounded by the buffer layer (Fig. 1C; ¶ 0012 “encapsulation material 500 completely encapsulates the first dies 300”);
performing a planarization process (Fig. 1D; ¶ 0013 “the thinning process includes a mechanical grinding process, a chemical mechanical polishing (CMP) process, or a combination thereof”) on the buffer layer (Fig. 1D; ¶ 0013 “a thinning process is performed to reduce the height…of the encapsulation material 500”) and the first substrate of the first die (Fig. 1D; ¶ 0013 “a thinning process is performed to reduce the height… of the first dies 300”) to form a thinned first substrate (Figs. 1C-1D; ¶ 0013 in this instance the height of the first substrate (that is the upper portion of first die 300 closest to surface 300b) is thinned from a height of H300 to a height of H300’);
forming a first bonding layer (620; Fig. 1E; ¶ 0015 “die attach film (DAF) 620”) on the thinned first substrate and the remaining buffer layer (Fig. 1E; ¶ 0015) to form a first package structure (Fig. 1E).
Ang does not disclose
wherein the first die comprises a first substrate and a first conductive plug formed in the first substrate; and
bonding the first package structure to a second package structure by bonding the first bonding layer to a second bonding layer.
Huang discloses
wherein the first die (300; Fig. 1E; ¶ 0043) comprises a first substrate (310; Fig. 1B; ¶ 0027) and a first conductive plug (330; Fig. 1E; ¶ 0025) formed in the first substrate (¶ 0025 “conductive features 330 are embedded in the substrate 310”); and
bonding (Fig. 1C; ¶ 0035, 0043) the first package structure (300; Figs. 1C, 1E) to a second package structure (100; Figs. 1C, 1E) by bonding the first bonding layer (440; Fig. 1C; ¶ 0036) to a second bonding layer (240; Fig. 1C; ¶ 0036).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Ang to have wherein the first die comprises a first substrate and a first conductive plug formed in the first substrate; and bonding the first package structure to a second package structure by bonding the first bonding layer to a second bonding layer, as taught by Huang, in order to “improve the density and functionality” of the package structure (Huang ¶ 0004).
Regarding Claim 13, Ang discloses further comprising:
forming nanostructures over the first substrate (¶ 0009 “first dies 300 may include…application-specific integrated circuit (“ASIC”) chips” it is known that ASICs have nanostructures and they would be formed over the substrate);
forming an interconnect structure over the nanostructures (¶ 0009 it is known that ASICs have an interconnect structure and it would be formed over the nanostructure); and
forming the first bonding layer over the interconnect structure (Fig. 1E; ¶ 0009 the bonding layer 620 is over the ASIC 300 that has the interconnect structure).
Regarding Claim 14, Ang discloses wherein the first substrate (the upper portion of first die 300 closest to surface 300b) is in direct contact with the buffer layer (Fig. 1C; ¶ 0010 “first dies 300…are bare dies”, ¶ 0012 “encapsulation material 500 completely encapsulates the first dies 300” and “a second surface 500b of the encapsulation material 500 is located at a level height higher than…surfaces 300b of the first dies 300”) before removing the portion of the buffer layer and the portion of the first substrate (Figs. 1C-1D; ¶ 0013 “a thinning process is performed to reduce the height…of the encapsulation material 500”).
Regarding Claim 21, Ang discloses method for forming a package structure (10; ¶ 0008; Figs. 1C-1E), comprising:
forming a first die (300; Fig. 1C; ¶ 0010 “first dies 300”) over a carrier substrate (100; Figs. 1C-1E; ¶ 0008 “first carrier 100”), wherein the first die comprises nanostructures (¶ 0009 “first dies 300 may include…application-specific integrated circuit (“ASIC”) chips” it is known that ASICs have nanostructures) formed over a first substrate (the upper portion of first die 300 closest to surface 300b; Figs. 1C-1E), an S/D structure formed adjacent to the nanostructures (¶ 0009 it is known that ASICs have a S/D structure and it would be formed adjacent/near to the nanostructures as they are both in the die) and a first conductive plug formed in the first substrate (¶ 0009 it is known that ASICs have a conductive plug (e.g. a conductive element) and part of it would be formed in the substrate);
forming a buffer layer (500; Figs. 1C-1E; ¶ 0012 “encapsulation material 500”) on the first die (Figs 1C-1E; ¶ 0012 “a second surface 500b of the encapsulation material 500 is located at a level height higher than both of the rear surfaces 300b of the first dies 300”), wherein the first die is surrounded by the buffer layer (Fig. 1C; ¶ 0012 “encapsulation material 500 completely encapsulates the first dies 300”);
performing a planarization process (Fig. 1D; ¶ 0013 “the thinning process includes a mechanical grinding process, a chemical mechanical polishing (CMP) process, or a combination thereof”) on a portion of the buffer layer (Fig. 1D; ¶ 0013 “a thinning process is performed to reduce the height…of the encapsulation material 500”) and a portion of the first substrate (Fig. 1D; ¶ 0013 “a thinning process is performed to reduce the height… of the first dies 300”) to form a thinned first substrate (Figs. 1C-1D; ¶ 0013 in this instance the height of the first substrate (that is the upper portion of first die 300 closest to surface 300b) is thinned from a height of H300 to a height of H300’);
forming a first bonding layer (620, Fig. 1E; ¶ 0015 “die attach film (DAF) 620”) on the thinned first substrate (Fig. 1E; ¶ 0015) to form a first package structure (Fig. 1E).
Ang does not disclose bonding the first package structure to a second package structure.
Huang discloses bonding (Fig. 1C; ¶ 0035, 0043) the first package structure (300; Figs. 1C, 1E) to a second package structure (100; Figs. 1C, 1E).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Ang to have bonding the first package structure to a second package structure, as taught by Huang, in order to “improve the density and functionality” of the package structure (Huang ¶ 0004).
Regarding Claim 24, Ang discloses wherein the first die further comprises:
an S/D contact structure formed over the S/D structure (¶ 0009 it is known that ASICs have a S/D contact structure formed over the S/D structure); and
a second conductive plug connected to the first conductive plug (¶ 0009 it is known that ASICs have a second conductive plug connected to the first conductive plug) and the S/D contact structure (¶ 0009 it is known that ASICs have a second conductive plug connected to the S/D contact structure).
Regarding Claim 25, Ang does not disclose wherein the first bonding layer comprises a first conductive layer embedded in a first insulating layer.
Huang discloses wherein the first bonding layer (Figs. 1D-1E; ¶ 0034) comprises a first conductive layer (420; Fig. 1D; ¶ 0030 “conductive bump 420”) embedded in a first insulating layer (520; Fig. 1D; ¶ 0041-0042).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Ang to have wherein the first bonding layer comprises a first conductive layer embedded in a first insulating layer, as taught by Huang, in order to “improve the density and functionality” of the package structure (Huang ¶ 0004).
Claims 11, 15, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Ang et al. (“Ang”), US 2019/0096840, and Huang et al. (“Huang”), US 20180151537, as applied to their respective Claims 10 and 21 supra, in view of Shao et al. “Shao”), US 2020/0091039.
Regarding Claim 11, Ang as modified by Huang does not disclose further comprising:
forming through substrate via (TSV) structures in the first substrate; and
exposing the TSV structures after removing the portion of the first substrate.
Shao discloses further comprising:
forming through substrate via (TSV) structures (120; Fig. 3A-3C; ¶ 0068 ”through-substrate-via (TSV) structures 120 are formed in the first substrate 102”) in the first substrate (102; Figs. 3A-3C; ¶ 0068 “through-substrate-via (TSV) structures 120 are formed in the first substrate 102”); and
exposing the TSV structures after removing the portion of the first substrate (Fig. 3C; ¶ 0079 “first substrate 102 is thinned from the second surface 102b until the TSV structure 120 is exposed”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Ang as modified to have further comprising: forming through substrate via (TSV) structures in the first substrate; and exposing the TSV structures after removing the portion of the first substrate, as taught by Shao, in order to have “various packages with different or similar functions that are integrated together” (Shao ¶ 0003) to have a compact package structure and allowing for a smaller overall device.
Regarding Claim 15, Ang as modified by Huang does not disclose wherein the first die is sawed from a wafer.
Shao discloses wherein the first die (202; Fig. 3C; ¶ 0070) is sawed from a wafer (¶ 0070 “202 is an integrated circuit (IC) die which is sawed from a wafer”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Ang as modified to have wherein the first die is sawed from a wafer, as taught by Shao, in order to have “various packages with different or similar functions that are integrated together” (Shao ¶ 0003) to have a compact package structure and allowing for a smaller overall device.
Regarding Claim 23, Ang as modified by Huang does not disclose further comprising:
after the planarization process, forming through substrate via (TSV) structures in the thinned first substrate, wherein one of the TSV structures is electrically connected to the first conductive plug.
Shao discloses further comprising:
after the planarization process (in this instance it would be obvious to form TSVs after the planarization process in order to save the cost of unneeded portions of the TSV structures), forming through substrate via (TSV) structures (120; Fig. 3A-3C; ¶ 0068 ”through-substrate-via (TSV) structures 120 are formed in the first substrate 102”) in the thinned first substrate (102; Fig. 3C; ¶ 0079 “substrate 102 of the first die 10 is thinned”), wherein one of the TSV structures is electrically connected to the first conductive plug (in this instance it would be obvious to electrically connect the first conductive plug to one of the TSV structures so as to provide electrical connections for the chip and allow all of the signals to run through it efficiently).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for Ang as modified to have further comprising: after the planarization process, forming through substrate via (TSV) structures in the thinned first substrate, wherein one of the TSV structures is electrically connected to the first conductive plug, as taught by Shao, in order to have “various packages with different or similar functions that are integrated together” (Shao ¶ 0003) to have a compact package structure and allowing for a smaller overall device.
Allowable Subject Matter
Claims 1-9 are allowed.
Regarding Claim 1, the prior art does not disclose after the planarization process, forming through substrate via (TSV) structures in the thinned first substrate, wherein one of the TSV structures is electrically connected to the first conductive plug and in the combination as claimed.
Claims 2-9 are allowable for depending on Claim 1.
Claim 12 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 12, the prior art does not teach or render obvious wherein one of the TSV structures is connected to the first conductive plug. Therefore, the combination of the features of Claims 10, 11, and 12 is considered allowable.
Claim 22 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding Claim 22, the prior art does not teach or render obvious wherein the second package structure comprises a second through substrate via (TSV) structures in the second substrate, and a width of the second substrate is greater than a width of the first substrate. Therefore, the combination of the features of Claims 21 and 22 is considered allowable.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chen et al., US 2018/0204791, discloses forming a first die over a carrier substrate, and forming a buffer layer on the first die. Chen et al., US 2021/0407920, discloses a package structure where a first die is sawed from a wafer. Chien et al., US 2021/050303, discloses forming a first die over a carrier substrate.
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/R.K./Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818