Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1)/(2) as being anticipated by MOTOHASHI (Pub. No.: US 2021/0221071).
Re claim 1, MOTOHASHI, FIG. 14 teaches an electronic package module, comprising:
a circuit substrate comprising:
a first circuit layer (31, ¶ [0060]);
a first insulation layer (32) covering the first circuit layer and having a first boundary surface;
a second circuit layer (41) located on the first boundary surface of the first insulation layer (32) and electrically connected to the first circuit layer (31); and
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a second insulation layer (52) located on the first boundary surface and partially covering the second circuit layer, wherein the second insulation layer bares a first region of the first boundary surface, and the first region is located on a perimeter of the first boundary surface to define a recessed region ([R], Fig. 14 [as shown above]) surrounding a side wall of the circuit substrate;
an electronic component (3) located on the circuit substrate and electrically connected to the circuit substrate; and
a molding compound (5, [0053]) encapsulating the circuit substrate and the electronic component, wherein the molding compound directly touches the first region of the first boundary surface and the second insulation layer (sidewalls of 42);
wherein the molding compound (5) directly covers the recessed region to encapsulate the entire side wall of the circuit substrate (sidewalls of 32 and 52), whereby the recessed region [R] is filled up with the molding compound.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-4, 6 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over MOTOHASHI in view of Chinese Patent No.: (CN110858575) (hereinafter `575).
Re claim 2, MOTOHASHI teaches all the limitation of claim 1.
MOTOHASHI fails to teach the limitation of claim 2.
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`575 teaches wherein the second insulation layer further comprising:
a plurality of trenches [T] and the plurality of trenches and the first region of the first boundary surface (occupied by far left and right of 140/124/[FR]) are not overlapping.
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of improving the radiating efficiency of the substrate as taught by `575, Background.
Moreover, after the combining of `575 and MOTOHASHI would teach wherein the molding compound (5 of MOTOHASHI) directly touches inner surfaces of the plurality of trenches ([T] of `575),
Re claim 3, in the combination, `575, FIG. 2A [as shown above] teaches the electronic package module of claim 2, wherein the inner surfaces of the plurality of trenches [T] comprise a part of the first boundary surface.
Re claim 4, in the combination, `575, FIG. 2A [as shown above] teaches the electronic package module of claim 2, wherein the electronic component (200) overlaps a second region [SR] of the first boundary surface surrounded by the first region [FR], and at least one of the plurality of trenches is located between the second region and the first region.
Re claim 6, in the combination, `575, FIG. 2A [as shown above] teaches the electronic package module of claim 2, wherein the electronic component (200) covers none of the plurality of trenches [T].
Re claim 9, in the combination, MOTOHASHI, Fig. 14 [as shown above] teaches the electronic package module of claim 1, wherein the molding compound (5) covers a side wall of the first insulation layer (32).
Claim(s) 1-4, 6 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over CHUI (Pub. No.: US 2026/0076250) in view of `575.
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Re claim 1, CHUI, FIG. 3A [as shown above] teaches an electronic package module, comprising:
a circuit substrate comprising:
a first circuit layer (26 or [FC] for claim 9, ¶ [0050]);
a first insulation layer (260 or [FI] for claim 9, FIG. 2D, [0051]) covering the first circuit layer and having a first boundary surface;
a second circuit layer ([SC] or [SCf9]) located on the first boundary surface of the first insulation layer [FI] and electrically connected to the first circuit layer (20); and
a second insulation layer (230, FIG. 2A, [0035]) located on the first boundary surface and partially covering the second circuit layer, wherein the second insulation layer bares a first region of the first boundary surface, and the first region is located on a perimeter of the first boundary surface;
an electronic component (21, [0037]) located on the circuit substrate and electrically connected to the circuit substrate; and
a molding compound (25, [0047]) encapsulating the circuit substrate and the electronic component, wherein the molding compound directly touches the first region of the first boundary surface and the second insulation layer [SI].
CHUI fails to teach the first region is located on a perimeter of the first boundary surface to define a recessed region surrounding a side wall of the circuit substrate; and wherein the molding compound directly covers the recessed region to encapsulate the entire side wall of the circuit substrate, whereby the recessed region is filled up with the molding compound.
`575 teaches the first region is located on a perimeter of the first boundary surface to define a recessed region [T] surrounding a side wall of the circuit substrate (110/122/124/140).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of improving the radiating efficiency of the substrate as taught by `575, Background.
Moreover, after the combining of `575 and CHUI would teach wherein the molding compound (25 of CHUI) directly touches inner surfaces of the plurality of trenches ([T] of `575), and whereby the recessed region [T] is filled up with the molding compound (25).
Re claim 2, in the combination, CHUI, FIG. 3A [as shown above] teaches the electronic package module of claim 1, wherein the second insulation layer further comprising:
a plurality of trenches [T], wherein the molding compound (25) directly touches inner surfaces of the plurality of trenches, and the plurality of trenches and the first region of the first boundary surface (occupied by 234) are not overlapping.
Re claim 3, in the combination, CHUI, FIG. 3A [as shown above] teaches the electronic package module of claim 2, wherein the inner surfaces of the plurality of trenches [T] comprise a part of the first boundary surface.
Re claim 4, in the combination, CHUI, FIG. 3A [as shown above] teaches the electronic package module of claim 2, wherein the electronic component (21) overlaps a second region of the first boundary surface surrounded by the first region (occupied by 234), and at least one of the plurality of trenches is located between the second region and the first region.
Re claim 6, in the combination, CHUI, FIG. 3A [as shown above] teaches the electronic package module of claim 2, wherein the electronic component covers none of the plurality of trenches [NofT].
Re claim 9, in the combination, CHUI, FIG. 3A [as shown above] teaches the electronic package module of claim 1, wherein the molding compound (25) covers a side wall of the first insulation layer [FI].
Response to Arguments
Applicant's arguments with respect to claims 1-4, 6 and 9 on the remarks filed on 07/20/2026 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONY TRAN whose telephone number is (571)270-1749. The examiner can normally be reached Monday-Friday, 8AM-5PM, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TONY TRAN/Primary Examiner, Art Unit 2893
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