Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I. Specie II, which corresponds to Claims 1-4, 6, 9 in the reply filed on 04/24/2026 is acknowledged. The traversal is on the ground(s) that it should be no undue burden on the Examiner to consider all claims in the single application. This is not found persuasive because the fact that claims 5, 7-8 and 10-15 are withdrawn per Applicants whose showed that the serious burden is undue.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ng (Pub. No.: US 2021/0296295).
Re claim 1, Ng, FIG. 2F teaches an electronic package module, comprising:
a circuit substrate comprising:
a first circuit layer (20, ¶ [0037]);
a first insulation layer (200, FIG. 2D, [0037]) covering the first circuit layer and having a first boundary surface;
a second circuit layer (260/27/270) located on the first boundary surface of the first insulation layer (200) and electrically connected to the first circuit layer (20); and
a second insulation layer (260) located on the first boundary surface and partially covering the second circuit layer, wherein the second insulation layer bares a first region of the first boundary surface, and the first region is located on a perimeter of the first boundary surface;
an electronic component (26) located on the circuit substrate and electrically connected to the circuit substrate; and
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a molding compound (28, [0042]) encapsulating the circuit substrate and the electronic component, wherein the molding compound directly touches the first region of the first boundary surface [FofFBS] and the second insulation layer (sidewalls of 260).
Claim(s) 1-4, 6 and 9 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by CHUI (Pub. No.: US 2026/0076250).
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Re claim 1, CHUI, FIG. 3A [as shown above] teaches an electronic package module, comprising:
a circuit substrate comprising:
a first circuit layer (26 or [FC] for claim 9, ¶ [0050]);
a first insulation layer (260 or [FI] for claim 9, FIG. 2D, [0051]) covering the first circuit layer and having a first boundary surface;
a second circuit layer ([SC] or [SCf9]) located on the first boundary surface of the first insulation layer [FI] and electrically connected to the first circuit layer (20); and
a second insulation layer (230, FIG. 2A, [0035]) located on the first boundary surface and partially covering the second circuit layer, wherein the second insulation layer bares a first region of the first boundary surface, and the first region is located on a perimeter of the first boundary surface;
an electronic component (21, [0037]) located on the circuit substrate and electrically connected to the circuit substrate; and
a molding compound (25, [0047]) encapsulating the circuit substrate and the electronic component, wherein the molding compound directly touches the first region of the first boundary surface and the second insulation layer [SI].
Re claim 2, CHUI, FIG. 3A [as shown above] teaches the electronic package module of claim 1, wherein the second insulation layer further comprising:
a plurality of trenches [T], wherein the molding compound (25) directly touches inner surfaces of the plurality of trenches, and the plurality of trenches and the first region of the first boundary surface (occupied by 234) are not overlapping.
Re claim 3, CHUI, FIG. 3A [as shown above] teaches the electronic package module of claim 2, wherein the inner surfaces of the plurality of trenches [T] comprise a part of the first boundary surface.
Re claim 4, CHUI, FIG. 3A [as shown above] teaches the electronic package module of claim 2, wherein the electronic component (21) overlaps a second region of the first boundary surface surrounded by the first region (occupied by 234), and at least one of the plurality of trenches is located between the second region and the first region.
Re claim 6, CHUI, FIG. 3A [as shown above] teaches the electronic package module of claim 2, wherein the electronic component covers none of the plurality of trenches [NofT].
Re claim 9, CHUI, FIG. 3A [as shown above] teaches the electronic package module of claim 1, wherein the molding compound (25) covers a side wall of the first insulation layer [FI].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONY TRAN whose telephone number is (571)270-1749. The examiner can normally be reached Monday-Friday, 8AM-5PM, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TONY TRAN/Primary Examiner, Art Unit 2893
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