DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) filed on July 28, 2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS is considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 18 and 19 are rejected under 35 U.S.C. 102(a)(1) or 102(a)(2) as being anticipated by Hung US 2014/0252634.
Regarding claim 18, Hung teaches a chip package structure (e.g., Fig. 6-12 and the description thereof), comprising:
a wiring substrate (e.g., 102, Fig. 12) having a surface (e.g., surface of 102 on which 110 (not labeled) is disposed, Fig. 12; Fig. 1);
a chip structure (e.g., 110 (not labeled), Fig. 12; Fig. 1) over the surface of the wiring substrate;
a first anchor structure (e.g., 130, Fig. 12) bonded to the surface of the wiring substrate, wherein the first anchor structure has an opening (e.g., opening created by 130, Fig. 12), the chip structure is in the opening (e.g., Fig. 12), and the first anchor structure is electrically isolated from the chip structure (e.g., Fig. 12);
an antiwarpage structure (e.g., 120, Fig. 12, [25], [31]) over the surface of the wiring substrate, wherein the antiwarpage structure surrounds the chip structure and is between the chip structure and the first anchor structure (e.g., Fig. 11, Fig. 12); and
a first conductive adhesive layer (e.g., thermally conductive layer(s) 124, 114 (not labeled) and/or 128, Fig. 12, [51]) between the first anchor structure and the antiwarpage structure.
Regarding claim 19, Hung teaches the chip package structure as claimed in claim 18, further comprising: an adhesive layer (e.g., 134, Fig. 12) over the surface of the wiring substrate, wherein the antiwarpage structure is bonded to the adhesive layer, and the first conductive adhesive layer is in direct contact with the adhesive layer (e.g., Fig. 12).
Claims 18 is rejected under 35 U.S.C. 102(a)(1) or 102(a)(2) as being anticipated by Saedi et al. US 2014/0061893.
Regarding claim 18, Saedi teaches a chip package structure (e.g., Fig. 13-14 and the description thereof), comprising:
a wiring substrate (e.g., 308, Fig. 13) having a surface (e.g., surface of 308 on which 304 is disposed, Fig. 13);
a chip structure (e.g., 304, Fig. 13) over the surface of the wiring substrate;
a first anchor structure (e.g., 302, Fig. 13) bonded to the surface of the wiring substrate, wherein the first anchor structure has an opening (e.g., opening created by 302, Fig. 13), the chip structure is in the opening (e.g., Fig. 13), and the first anchor structure is electrically isolated from the chip structure (e.g., Fig. 13);
an antiwarpage structure (e.g., 1302, Fig. 13, [68], [66]) over the surface of the wiring substrate, wherein the antiwarpage structure surrounds the chip structure and is between the chip structure and the first anchor structure (e.g., Fig. 14, Fig. 13); and
a first conductive adhesive layer (e.g., thermally conductive layer(s) 1304, Fig. 13, [68]) between the first anchor structure and the antiwarpage structure (e.g., Fig. 13).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 4, 5, 7 and 9 are rejected are rejected under 35 U.S.C. 103 as being unpatentable over Saedi et al. US 2014/0061893.
Regarding claim 1, Saedi (one interpretation) teaches a chip package structure (e.g., Fig. 13-14 and the description thereof), comprising:
a wiring substrate (e.g., 308, Fig. 13) having a first conductive pad (e.g., [31]);
a chip structure (e.g., 304, Fig. 13) over the wiring substrate;
an antiwarpage structure (e.g., 1302, Fig. 13, [68], [66]) over the wiring substrate, wherein the antiwarpage structure surrounds the chip structure (e.g., Fig. 14); and
a first anchor structure (e.g., 302, Fig. 13) adjacent to a first lower portion of the antiwarpage structure (e.g., first lower portion of 1302 near the lower 1304, Fig. 13), wherein the first lower portion is between the first anchor structure and the chip structure (e.g., Fig. 13), and the first anchor structure is electrically insulated from the chip structure (e.g., Fig. 13).
Saedi does not explicitly teach a first anchor structure on the first conductive pad of the wiring substrate and the first conductive pad is electrically insulated from the chip structure.
Saedi, however, recognizes that the wiring substrate 308 includes one or more electrically conductive layers such as contact pads at the surface 310 of 308 (e.g., [31]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Saedi to include a first anchor structure on the first conductive pad of the wiring substrate and the first conductive pad is electrically insulated from the chip structure for the purpose of enhancing heat spreading efficiency and reducing the electrical interference in the wiring substrate for example.
Regarding claim 3, Saedi teaches the chip package structure as claimed in claim 1, wherein the first anchor structure is closer to the first lower portion of the antiwarpage structure than the chip structure (e.g., Fig. 13).
Regarding claim 4, Saedi teaches the chip package structure as claimed in claim 1, wherein the first anchor structure comprises a pillar structure or a strip structure (e.g., Fig. 13, Fig. 14).
Regarding claim 5, Saedi teaches the chip package structure as claimed in claim 1, wherein the first anchor structure comprises a ring structure, and the first anchor structure continuously surrounds the chip structure in a top view of the first anchor structure and the chip structure (e.g., Fig. 14).
Regarding claim 1, Saedi (alternative interpretation) teaches a chip package structure (e.g., Fig. 13-14 and the description thereof), comprising:
a wiring substrate (e.g., 308, Fig. 13) having a first conductive pad (e.g., [31]);
a chip structure (e.g., 304, Fig. 13) over the wiring substrate;
an antiwarpage structure (e.g., 1302, Fig. 13, [68], [66]) over the wiring substrate, wherein the antiwarpage structure surrounds the chip structure (e.g., Fig. 14); and
a first anchor structure (e.g., first anchor structure; see the annotated Fig. 13 below) adjacent to a first lower portion of the antiwarpage structure (e.g., first lower portion; see the annotated Fig. 13 below), wherein the first lower portion is between the first anchor structure and the chip structure (e.g., Fig. 13), and the first anchor structure is electrically insulated from the chip structure (e.g., Fig. 13).
Saedi does not explicitly teach a first anchor structure on the first conductive pad of the wiring substrate and the first conductive pad is electrically insulated from the chip structure.
Saedi, however, recognizes that the wiring substrate 308 includes one or more electrically conductive layers such as contact pads at the surface 310 of 308 (e.g., [31]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Saedi to include a first anchor structure on the first conductive pad of the wiring substrate and the first conductive pad is electrically insulated from the chip structure for the purpose of enhancing heat spreading efficiency and reducing the electrical interference in the wiring substrate for example.
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Annotated Fig. 13 of Saedi
Regarding claim 7, Saedi teaches the chip package structure as claimed in claim 1, further comprising: a second anchor structure (e.g., second anchor structure; see the annotated Fig. 13 above) over the wiring substrate and adjacent to a second lower portion of the antiwarpage structure (e.g., second lower portion; see the annotated Fig. 13 above), wherein the chip structure is between the first lower portion and the second lower portion of the antiwarpage structure; see the annotated Fig. 13 above), the second lower portion is between the second anchor structure and the chip structure (e.g., see the annotated Fig. 13 above), and the second anchor structure is electrically isolated from the chip structure (e.g., see the annotated Fig. 13 above).
Regarding claim 9, Saedi teaches the chip package structure as claimed in claim 7 as discussed above.
Saedi does not explicitly teach wherein the second anchor structure is on a second conductive pad of the wiring substrate, and the second conductive pad is electrically isolated from the chip structure.
Saedi, however, recognizes that the wiring substrate 308 includes one or more electrically conductive layers such as contact pads at the surface 310 of 308 (e.g., [31]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Saedi to include wherein the second anchor structure is on a second conductive pad of the wiring substrate, and the second conductive pad is electrically isolated from the chip structure for the purpose of enhancing heat spreading efficiency and reducing the electrical interference in the wiring substrate for example.
Claims 10-12 and 17 are rejected are rejected under 35 U.S.C. 103 as being unpatentable over Hung US 2014/0252634 in view of Saedi et al. US 2014/0061893.
Regarding claim 10, Hung teaches a chip package structure (e.g., Fig. 1-5 and the description thereof), comprising:
a wiring substrate (e.g., 102, Fig. 5) having a surface (e.g., surface of 102 on which 110 (not labeled) is disposed, Fig. 5; Fig. 1);
a chip structure (e.g., 110 (not labeled) and 128, Fig. 5; Fig. 1) over the surface of the wiring substrate, wherein the chip structure comprises a chip (e.g., 110 (not labeled), Fig. 5; Fig. 1);
a structure (e.g., 130, Fig. 5; [48]) over the surface of the wiring substrate, wherein the structure surrounds the chip structure (e.g., Fig. 5); and
a first anchor structure (e.g., 120, Fig. 5) bonded to the surface of the wiring substrate and adjacent to a first lower portion (e.g., first lower portion of 130 near 132, Fig. 5) of the structure, wherein the first anchor structure is between the chip structure and the first lower portion (e.g., Fig. 5), a top surface of the first anchor structure is lower than a bottom surface of the chip (e.g., Fig. 5), and the first anchor structure is electrically isolated from the chip structure (e.g., Fig. 5).
Hung does not explicitly teach an antiwarpage structure.
Hung, however, recognizes that the structure 130 functions as a heatsink (e.g., [48]).
It has been well known in the art that a heatsink/heat spreader lid may function as an antiwarpage structure as suggested by Saedi (e.g., [36]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the structure 130 of Hung may function as an antiwarpage structure as suggested by Saedi for the purpose of reducing warpage, thereby enhancing the performance of the package structure for example (e.g., Saedi, [75]).
Regarding claim 11, Hung in view of Saedi teaches the chip package structure as claimed in claim 10, wherein the first lower portion is closer to the first anchor structure than the chip structure (e.g., Hung, Fig. 5).
Regarding claim 12, Hung in view of Saedi teaches the chip package structure as claimed in claim 10 as discussed above.
Hung in view of Saedi does not explicitly teach wherein a first upper portion of the first anchor structure is narrower than a second lower portion of the first anchor structure.
Hung in view of Saedi, however, recognizes that the first anchor structure 120 has various shapes and combinations thereof (e.g., Hung, [36], [40]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Hung in view of Saedi to include wherein a first upper portion of the first anchor structure is narrower than a second lower portion of the first anchor structure because a shape of the anchor structure is a matter of obvious design choice and thus the claimed arrangement could be achieved by the general skill of a worker in the art through ordinary means of routine work for a desired purpose for example.
Regarding claim 17, Hung in view of Saedi teaches the chip package structure as claimed in claim 10, further comprising: a conductive layer (e.g., thermally conductive layer(s) 124, 114 (not labeled) and/or 128; Fig. 5, [51]) connected between the first anchor structure and the antiwarpage structure.
Allowable Subject Matter
Claims 2, 6, and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 13-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Bo Bin Jang whose telephone number is (571) 270-0271. The examiner can normally be reached on M-F from 9:00 AM to 6:00 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BO B JANG/Primary Examiner, Art Unit 2818 February 6, 2026
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