DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Applicant’s election without traverse of Group 1, directed to claims 1-15 and 21-25 in the reply filed on January 23, 2026 is acknowledged. Claims 16-20 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected group. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claim s 7 , 11-12, 114-15 , 21- 23 and 25 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Regarding claim 7 , the claim recites, “ wherein the first transistor has a first capacitance equivalent thickness, and the second transistor has a second capacitance equivalent thickness that is thinner than the first capacitance equivalent thickness ”, which does not have support in the disclosure. Paragraph [0109] of the instant application recites, “ wherein the first transistor has a first capacitance equivalent thickness, and the second transistor has a second capacitance equivalent thickness that is thinner than the first capacitance equivalent thickness ….”. Paragraph [0110] recites, “ In the anneal process 1100, due to the incorporation of nitrogen, the interfacial layer 134 in the device region 50N substantially does not regrow, or only slightly regrows, in accordance with some embodiments. ” Paragraph [0114] recites, “ The capacitance equivalent thickness of the p-type transistor P1 is thicker than the capacitance equivalent thickness of the n-type transistor N1, ….” The nitrogen-doped interfacial layer does not substantially allow regrowth of oxide during annealing as a result its capacitance equivalent thickness is less than that of a non-nitrogen doped interfacial layer. Regarding claim 10 , the claim recites absorbing dopant on the surface of the first high-k dielectric layer however, the disclosure lacks explicit support for such a broad assertion. While additional dopants are mentioned in the disclosure, the detailed discussion is primarily limited to nitrogen as the dopant. Consequently, the claim’s scope regarding dopant absorption on the high-k surface maybe considered overly general. Claims 11-12 and 14-15 depend upon claim 10 and do not rectify the problem therefore, they are also rejected. Regarding claim 21 , the claim recites formation of a nitrogen-doped interfacial layer to surround the first nanostructure which does not have support in the disclosure. The disclosure does not teach in-situ nitrogen doping during deposition rather the nitrogen is diffused into the interfacial layer. Claims 22-2 3 and 25 depend upon claim 21 and do not rectify the problem therefore, they are also rejected. Regarding claim 24 , the claim recites forming an interfacial layer around the nanostructure and doping it with nitrogen through an anneal, which does not have support in the disclosure. Nitrogen incorporation into the interfacial layer is achieved by nitrogen plasma treatment of the overlying high-k dielectric layer, followed by an annealing process that drives the diffusion of nitrogen from the high-k dielectric layer into the underlying interfacial layer rather than direct independent nitrogen incorporation into the interfacial layer alone. Claim 25 depends upon claim 24 and does not rectify the problem therefore, it is also rejected. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b ) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the appl icant regards as his invention. Claims 21-25 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention. Regarding claim 21 , the claim recites, “ forming a thickened interfacial layer to surround the second nanostructure, wherein a nitrogen concentration of the nitrogen-doped interfacial layer is greater than a nitrogen concentration of the thickened interfacial layer; ” which is indefinite as it is not clear and lacks antecedent basis since it is not clear how the thickened interfacial layer has nitrogen concentration. Claims 22-25 depend upon claim 21 and do not rectify the problem therefore, they are also rejected. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1 -2 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 2021/0202323 A1; hereafter Wu ) in view of Moriwaki (US 2018/0174926 A1) and Lisiansky et al. (US 2009/0181530 A1; hereafter Lisiansky ) . Regarding claim 1 , Wu teaches a method for forming a semiconductor structure (see e.g., Figure s 1 A-1B and 18 ) , comprising: forming a first nanostructure and a second nanostructure over a substrate (see e.g., GAA device s 18 and 20 in the core area including logic and memory circuits have vertically stacked multiple channel members 26 above the substrate 27, Para [0014], Figure s 1A, 1B ) ; forming a first interfacial layer on the first nanostructure and a second interfacial layer on the second nanostructure (see e.g., the channel members 26 of the GAA device s 18 and 20 are wrapped around by interfacial layers 30a and 30 b respectively, Para [0014], Figures 1A, 1B) ; forming a first gate dielectric layer on the first interfacial layer and a second gate dielectric layer on the second interfacial layer (see e.g., GAA devices 18 and 2 0 include high-k dielectric layers 32a, and 32 b respectively formed on the respective interfacial layers, Para [0014], Figures 1A, 1B ) ; Wu does not explicitly teach “ forming a patterned mask layer on the second gate dielectric layer while exposing the first gate dielectric layer ” ; Using patterned mask to selectively expose regions, in order to allow selective modification of one region while protecting the other region is well known in the art. In a similar field of endeavor Moriwaki teaches forming a patterned mask layer on the second gate dielectric layer while exposing the first gate dielectric layer (see e.g., patterned masking layers 82/84 extend across region 90 of the gate dielectric 80. Another region 90 of the gate dielectric layer 80 is not covered by the patterned masking layers 80/82, Para [0044], Figures 2-5) ; Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Moriwaki’s teachings of forming a patterned mask layer on the second gate dielectric layer while exposing the first gate dielectric layer in the method of Wu in order to selectively expose regions so that ions are implanted only in designated zones. Wu does not explicitly teach “ driving nitrogen into the first interfacial layer, thereby forming a nitrogen-doped interfacial layer ” . In a similar field of endeavor Lisiansky teaches driving nitrogen into the first interfacial layer, thereby forming a nitrogen-doped interfacial layer (see e.g., an amorphous high-k dielectric layer 213 is formed on an insulating silicon oxide layer 211. Nitrogen ions 215 are implanted into the upper surface of the amorphous high-k dielectric layer 213 followed by annealing process at a temperature of 830.degree.C or higher. As a result, the amorphous high-k dielectric layer 213 is transformed into a nitrided crystalline high-k dielectric layer 214. The nitrogen ions 215 exhibit a low segregation coefficient in the crystalline high-k dielectric layer 214, thereby resulting in an efficient out-diffusion of atomic nitrogen from this layer 214 into the adjacent silicon oxide layer 211. The nitrogen that diffuses into silicon oxide layer 211 is labeled with reference number 216 in FIG. 2E. As a result, silicon oxide layer 211 advantageously becomes strongly nitride, Paras [002 7 ] , [0028], [0033], Figures 2A-2E ) . Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Lisiansky’s teachings of driving nitrogen into the first interfacial layer, thereby forming a nitrogen-doped interfacial layer in the method of Wu in order to optimize gate dielectric of the CMOS transistor to be used for specific circuit purpose. Regarding claim 2 , Wu, as modified by Moriwaki and Lisiansky , teaches the limitations of claim 1 as mentioned above. Wu does not explicitly teach “wherein diffusing nitrogen into the first interfacial layer through the first gate dielectric layer comprises: plasma treating the first gate dielectric layer and the patterned mask layer using a nitrogen- containing gas; ” In a similar field of endeavor Moriwaki tecahes wherein diffusing nitrogen into the first interfacial layer through the first gate dielectric layer comprises: plasma treating the first gate dielectric layer and the patterned mask layer using a nitrogen- containing gas; and (see e.g., construction 10a is exposed to nitrogen plasma 94 which is implanted in the exposed region 92 of the gate dielectric layer 80 while the other region 90 of the gate dielectric layer is protected by the blocking mass 88, Para [0045], Figure 5) Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Moriwaki’s teachings of wherein diffusing nitrogen into the first interfacial layer through the first gate dielectric layer comprises: plasma treating the first gate dielectric layer and the patterned mask layer using a nitrogen- containing gas; and in the method of Wu in order to selectively expose regions so that ions are implanted only in designated zones. Wu does not explicitly teach “annealing the substrate so that nitrogen diffuses through the first gate dielectric layer into the first interfacial layer”. In a similar field of endeavor Lisiansky teaches annealing the substrate so that nitrogen diffuses through the first gate dielectric layer into the first interfacial layer (see e.g., after nitridation, the structure is exposed to high temperature which causes the nitrogen 216 to diffuse into the silicon oxide layer 211 to become nitride, Para [0033], Figures 2D-2E) . Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement annealing the substrate so that nitrogen diffuses through the first gate dielectric layer into the first interfacial layer in the method of Wu in order to be used as a gate dielectric of a high voltage CMOS transistor. Regarding claim 9 , Wu, as modified by Moriwaki and Lisiansky , teaches the limitations of claim 1 as mentioned above. Wu further teaches wherein the first nanostructure is formed in a logic device region of the substrate, and the second nanostructure is formed in a memory device region of the substrate (see e.g., GAA devices 18 and 20 are formed in the core area which includes logic circuits, memory circuits and other core circuits. GAA device 18 has a thin capacitance equivalent thickness to provide high speed operation and hence is suitable for logic circuits. GAA device 20 has a thicker CET and is suitable for low power low leakage applications in memory circuits, Paras [0013], [0015], Figures 1A, 1B ) . Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 2021/0202323 A1; hereafter Wu) in view of Moriwaki (US 2018/0174926 A1) and Lisiansky et al. (US 2009/0181530 A1; hereafter Lisiansky ) and further in view of Wang et al. (US 2006/0131672 A1; hereafter Wang) . Regarding claim 3 , Wu, as modified by Moriwaki and Lisiansky , teaches the limitations of claim 2 as mentioned above. Wu does not explicitly teach “ wherein plasma treating the first gate dielectric layer and the patterned mask layer with the nitrogen-containing gas is performed at a first temperature, and annealing the substrate is performed at a second temperature that is greater than the first temperature ” . In a similar field of endeavor Lisiansky teaches wherein plasma treating the first gate dielectric layer and the patterned mask layer with the nitrogen-containing gas is performed at a first temperature, and annealing the substrate is performed at a second temperature that is greater than the first temperature (see e.g., implanting nitrogen into the high-k dielectric layer 6 by plasma treatment and one or more bakes in a gas environment containing nitrogen atoms example N.sub.2, N.sub.2O, NO and/or NH.sub.3. The annealing is performed at a temperature of 830 .degree. C. or higher, which represents the crystallization temperature of amorphous alumina ) . Lisiansky does not specify the temperature during the nitridation process. However, as taught by Wang plasma nitridation process is performed at about 550.degree. C. for about 1 minute in nitrogen or decoupled plasma nitridation is performed at about 25.degree. C. (or at room temperature) for about 30 seconds in nitrogen (see e.g., paras [0032], [0033]) . Lisiansky when combined with the teaching of Wang, which teaches plasma nitridation at 550.degree.C or room temperature, provides a specific lower temperature nitrogen incorporation method compared to typical subsequent anneals. For instance, post-nitridation annealing is performed at high temperatures which exceed 830.degree.C to optimize dielectric integrity . Therefore, it would be obvious to one skilled in the art at the time the invention was effectively filed to implement Lisiansky’s teachings of wherein plasma treating the first gate dielectric layer and the patterned mask layer with the nitrogen-containing gas is performed at a first temperature, and annealing the substrate is performed at a second temperature that is greater than the first temperature in the device of Wu in order to improve reliability and performance for both peripheral and core devices. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 2021/0202323 A1; hereafter Wu) in view of Moriwaki (US 2018/0174926 A1) and Lisiansky et al. (US 2009/0181530 A1; hereafter Lisiansky ) and further in view of Lee (US 2020/0194267 A1) . Regarding claim 4 , Wu, as modified by Moriwaki and Lisiansky , teaches the limitations of claim 2 as mentioned above. Wu does not explicitly teach “f urther comprising: removing the patterned mask layer to expose the second gate dielectric layer after plasma treating and before annealing the substrate ” . There are two options either perform annealing after removing the patterned mask or before removing the patterned mask. It would be obvious to try any one of the combination. The rationale to support a conclusion that the claim would have been obvious is that “a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely that product [was] not of innovation but of ordinary skill and common sense. In that instance the fact that a combination was obvious to try might show that it was obvious under § 103.”KSR, 550 U.S. at 421, 82 USPQ2d at 1397. MPEP 2143 (E). In a similar field of endeavor Lee provides a generic teaching of providing a mask layer 14M as a barrier to ion implantation. This mask layer 14M may be removed in a subsequent annealing (oxide re-growth) process as shown in Figures 3C and 3D. Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to apply one of the options that is, remove the patterned mask after plasma treatment and before annealing in order to prevent contamination or damage from thermal decomposition of mask materials and ensure uniform thermal oxidation . Claim s 5 and 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 2021/0202323 A1; hereafter Wu) in view of Moriwaki (US 2018/0174926 A1) and Lisiansky et al. (US 2009/0181530 A1; hereafter Lisiansky ) and further in view of Hattangady et al. (US 6,716,695 B1 ) . Regarding claim 5 , Wu, as modified by Moriwaki and Lisiansky , teaches the limitations of claim 2 as mentioned above. Wu further teaches wherein the second interfacial layer regrows in the step of annealing the substrate to form a thickened interfacial layer (see e.g., an annealing process 270 initiates oxide regrowth process on the interfacial layer 252b. After the annealing process the thickness of the interfacial layer 252b is larger than the thickness of the interfacial layer 252a, Para [0034], Figure 15) Wu does not explicitly teach “ wherein the second interfacial layer ….. form a thickened interfacial layer that is thicker than the nitrogen-doped interfacial layer ” . However, this structural difference is the result of applying known techniques to optimize interfacial layers. In a similar field of endeavor Hattangady teaches f ormation of an oxide layer 20 beneath the nitride layer 18 by thermal oxidation of the substrate 10 and nitride layer 18. The nitride layer 18 retards the oxidation, resulting in control over the thickness of the oxide layer 20. By applying the teachings of Hattangandy to Wu a person of ordinary skill would understand that a nitrogen doped interfacial layer acts as an oxidation retardant (similar to the nitride layer in Hattangandy ) while a non-nitrogen doped layer (e.g., a pure SiO.sub.2) allows faster oxidation. Therefore, subjecting both to subsequent annealing/oxidation process (regrowth) predictable results in the non-nitrogen doped layer becoming a thickened layer compared doped one. Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to optimize device performance by manipulating interfacial thickness via controlled oxidation. Regarding claim 7 , Wu, as modified by Moriwaki and Lisiansky , teaches the limitations of claim 1 as mentioned above. Wu further teaches further comprising: forming a first gate electrode layer on the first gate dielectric layer (see e.g., gate electrode layer 282 formed around the GAA device 18 in the core area, Paras [0015], [0039], Figures 1A, 1B and 18) , wherein the first gate electrode layer, the first gate dielectric layer, the …. interfacial layer and the first nanostructure form a first transistor; and (see e.g., the gate electrode 282, high-k dielectric 254a and interfacial layer 252a and the nanowires 220 form a first transistor in the core region, Figure 18) forming a second gate electrode layer on the second gate dielectric layer (see e.g., gate electrode layer 282 formed around the GAA device 20 in the core area, Paras [0015], [0039], Figures 1A, 1B and 18) , wherein the second gate electrode layer, the second gate dielectric layer, the second interfacial layer and the second nanostructure form a second transistor (see e.g., gate electrode 282, high-k dielectric 254b, the interfacial layer 252b and nanowires 220 form the second transistor in the core area, Paras [0015], [0039], Figures 1A, 1B and 18) , wherein the first transistor has a first capacitance equivalent thickness (see e.g., the GAA device 18 in the core area includes a n interfacial layer 252a and a gate dielectric layer 254a (equivalent to 30a and 32a) has the thinnest capacitance equivalent thickness suitable for high-speed switching, Para [0015], Figures 1A, 1B and 18) , and the second transistor has a second capacitance equivalent thickness that is thinner than the first capacitance equivalent thickness (see e.g., the GAA device 20 in the core area includes an interfacial layer 252b and a gate dielectric 254b (equivalent to 30b and 32b) has a thicker gate dielectric layer suitable for low voltage and low leakage applications, Para [0015], Figure 1A, 1B and 18) . Wu does not explicitly teach “wherein the first gate electrode layer, the first gate dielectric layer, the nitrogen-doped interfacial layer and the first nanostructure form a first transistor”; In a similar field of endeavor Hattangady teaches wherein the first gate electrode layer, the first gate dielectric layer, the nitrogen-doped interfacial layer and the first nanostructure form a first transistor (see e.g., nitride oxide layer (20/18), gate dielectric 24 and conductive layer 26 and the underlying channel form a transistor, Figure 1G) ; T herefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Hattangandy’s teachings of wherein the first gate electrode layer, the first gate dielectric layer, the nitrogen-doped interfacial layer and the first nanostructure form a first transistor to achieve the expected functionality of a transistor to obtain improved gate to channel coupling and device performance. Regarding claim 8 , Wu, as modified by Moriwaki , Lisiansky and Hattangady , teaches the limitations of claim 7 as mentioned above. Wu further teaches wherein the first transistor has a first threshold voltage greater than zero, and the second transistor has a second threshold voltage greater than the first threshold voltage (see e.g., GAA device 18 has a thin capacitance equivalent thickness (CET) while GAA device 24 has a thick CET. Therefore, the threshold voltage of GAA device 24 would be higher) . Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 2021/0202323 A1; hereafter Wu) in view of Moriwaki (US 2018/0174926 A1) and Lisiansky et al. (US 2009/0181530 A1; hereafter Lisiansky ) and further in view of Burnham et al. (US 2006/0281265 A 1) . Regarding claim 6 , Wu, as modified by Moriwaki and Lisiansky , teaches the limitations of claim 2 as mentioned above. Wu does not explicitly teach “ wherein the nitrogen-containing gas is activated to form the nitrogen radical, and the nitrogen radical is adsorbed onto a surface of the first gate dielectric layer ” . In a similar field of endeavor Burnham teaches wherein the nitrogen-containing gas is activated to form the nitrogen radical, and the nitrogen radical is adsorbed onto a surface of the first gate dielectric layer (see e.g., Remote plasma nitridation (RPN) using microwave or decoupled plasma nitridation (DPN) using radio frequency may interact with a nitrogen-containing gas to generate plasma containing nitrogen radicals. Areas 810, 820 are exposed to the nitrogen radicals, Para [0039], Figures 8-10) . Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Burnham’s teachings of wherein the nitrogen-containing gas is activated to form the nitrogen radical, and the nitrogen radical is adsorbed onto a surface of the first gate dielectric layer in the method of Wu as nitrogen radical adsorption onto the surface of the dielectric is a known mechanism for forming high-quality interfacial layers . Claim s 10 and 13 -14 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 2021/0202323 A1; hereafter Wu) in view of Lisiansky et al. (US 2009/0181530 A1; hereafter Lisiansky ). Regarding claim 10 , Wu teaches a method for forming a semiconductor structure (see e.g., Figures 1A-1B and 18) , comprising: forming a plurality of first nanostructures over a substrate (see e.g., GAA device 18 in the core region has vertically stacked multiple channel members 220 above the substrate 208, Paras [0014], [0018], [0021] Figures 1A, 1B and 18) ; forming a first interfacial layer around the plurality of first nanostructures (see e.g., interfacial layer 252a formed around the plurality of channel members 220 in the GAA device 18, Para [0031], Figures 1A, 1B and 18) ; forming a first high-k dielectric layer around the first interfacial layer (see e.g., a high-k dielectric layer 254a formed around the interfacial layer 252a, Para [0032], Figures 1A, 1B and 18) ; forming a first work function layer around the first high-k dielectric layer (see e.g., gate electrode 282 formed around the high-k dielectric layer 254a, Para [0039], Figures 1A, 1B and 18) . Wu does not explicitly teach “treating a surface of the first high-k dielectric layer so that a dopant adsorbs onto the surface of the first high-k dielectric layer; annealing the substrate to drive the dopant into the first interfacial layer;” In a similar field of endeavor Lisiansky teaches treating a surface of the first high-k dielectric layer so that a dopant adsorbs onto the surface of the first high-k dielectric layer; annealing the substrate to drive the dopant into the first interfacial layer (see e.g., an amorphous high-k dielectric layer 213 is formed on an insulating silicon oxide layer 211. Nitrogen ions 215 are implanted into the upper surface of the amorphous high-k dielectric layer 213 followed by annealing process at a temperature of 830.degree.C or higher. As a result, the amorphous high-k dielectric layer 213 is transformed into a nitrided crystalline high-k dielectric layer 214. The nitrogen ions 215 exhibit a low segregation coefficient in the crystalline high-k dielectric layer 214, thereby resulting in an efficient out-diffusion of atomic nitrogen from this layer 214 into the adjacent silicon oxide layer 211. The nitrogen that diffuses into silicon oxide layer 211 is labeled with reference number 216 in FIG. 2E. As a result, silicon oxide layer 211 advantageously becomes strongly nitride, Paras [0027], [0028], [0033], Figures 2A-2E) . Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Lisiansky’s teachings of treating a surface of the first high-k dielectric layer so that a dopant adsorbs onto the surface of the first high-k dielectric layer; annealing the substrate to drive the dopant into the first interfacial layer in the method of Wu in order to optimize the CET leading to improved electrical performance in the final CMOS device . Regarding claim 1 3 , Wu, as modified by Lisiansky , teaches the limitations of claim 12 as explained above. Wu does not explicitly teach “ wherein the dopant is nitrogen, and after annealing the substrate, a nitrogen concentration of the interfacial layer increases from an interior of the interfacial layer to an interface between the interfacial layer and the second high-k dielectric layer ” . In a similar field of endeavor Lisiansky teaches wherein the dopant is nitrogen, and after annealing the substrate, a nitrogen concentration of the interfacial layer increases from an interior of the interfacial layer to an interface between the interfacial layer and the second high-k dielectric layer (see e.g., an amorphous high-k dielectric layer 213 is formed on an insulating silicon oxide layer 211. Nitrogen ions 215 are implanted into the upper surface of the amorphous high-k dielectric layer 213 followed by annealing process at a temperature of 830.degree.C or higher. As a result, the amorphous high-k dielectric layer 213 is transformed into a nitrided crystalline high-k dielectric layer 214. The nitrogen ions 215 exhibit a low segregation coefficient in the crystalline high-k dielectric layer 214, thereby resulting in an efficient out-diffusion of atomic nitrogen from this layer 214 into the adjacent silicon oxide layer 211. The nitrogen that diffuses into silicon oxide layer 211 is labeled with reference number 216 in FIG. 2E. As a result, silicon oxide layer 211 advantageously becomes strongly nitride, Paras [0027], [0028], [0033], Figures 2A-2E) As nitrogen diffuses from the upper high-k layer downwards into the interfacial layer, the resulting nitrogen concentration in the interfacial layer is higher at the interface with the high-k dielectric and lower in the interior of the interfacial layer creating a graded concentration. Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Lisiansky’s teachings of wherein the dopant is nitrogen, and after annealing the substrate, a nitrogen concentration of the interfacial layer increases from an interior of the interfacial layer to an interface between the interfacial layer and the second high-k dielectric layer in the method of Wu in order to optimize the CET leading to improved electrical performance in the final CMOS device. Regarding claim 1 4 , Wu, as modified by Lisiansky , teaches the limitations of claim 10 as explained above. Wu does not explicitly teach “wherein the dopant is driven into the first interfacial layer to form a doped interfacial layer, and a dielectric constant of the doped interfacial layer is greater than a dielectric constant of the first interfacial layer”. In a similar field of endeavor Lisiansky teaches wherein the dopant is driven into the first interfacial layer to form a doped interfacial layer (see e.g., Nitrogen ions 215 are implanted into the upper surface of the amorphous high-k dielectric layer 213 followed by annealing process at a temperature of 830.degree.C or higher. As a result, the amorphous high-k dielectric layer 213 is transformed into a nitrided crystalline high-k dielectric layer 214. The nitrogen ions 215 exhibit a low segregation coefficient in the crystalline high-k dielectric layer 214, thereby resulting in an efficient out-diffusion of atomic nitrogen from this layer 214 into the adjacent silicon oxide layer 211. The nitrogen that diffuses into silicon oxide layer 211 is labeled with reference number 216 in FIG. 2E. As a result, silicon oxide layer 211 advantageously becomes strongly nitride, Paras [0027], [0028], [0033], Figures 2A-2E) , and a dielectric constant of the doped interfacial layer is greater than a dielectric constant of the first interfacial layer (see e.g. nitride silicon oxide layer has a higher dielectric constant than the silicon oxide layer. The resulting structure is similar to that of the instant application therefore the outcome must also be similar) . Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Lisiansky’s teachings of wherein the dopant is driven into the first interfacial layer to form a doped interfacial layer, and a dielectric constant of the doped interfacial layer is greater than a dielectric constant of the first interfacial layer in the method of Wu in order to optimize the CET leading to improved electrical performance in the final CMOS device. Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 2021/0202323 A1; hereafter Wu) in view of Lisiansky et al. (US 2009/0181530 A1; hereafter Lisiansky ) and further in view of Gandikota et al. (US 2021/0111020 A1; hereafter Gandikota ) and Siddiqui et al. (US 9,741,720 B1; hereafter Siddiqui) . Regarding claim 11 , Wu, as modified by Lisiansky , teaches the limitations of claim 10 as explained above. Wu does not explicitly teach “ further comprising, after annealing the substrate: forming a first capping layer around the first high-k dielectric layer; forming a second capping layer around the first capping layer, wherein the second capping layer and the first capping layer are made of different materials; ” . In a similar field of endeavor Gandikota teaches further comprising, after annealing the substrate (see e.g., after subjecting a high-k dielectric 306 to a plasma nitridation process followed by a post nitridation anneal process, Paras [0043], [0044], Figure 2) : forming a first capping layer around the first high-k dielectric layer (see e.g., after the nitridation and post nitridation anneal process a metal gate structure 500 is formed over the gate dielectric layer 306. A high-k dielectric capping layer 502, metal nitride material including titanium (Ti) or tantalum (Ta) doped with silicon (Si), aluminum (Al), gallium (Ga), germanium (Ge), indium (In), or hafnium (Hf), such as TiSiN , TaSiN , TiAlN , TaAlN , TiGaN , TaGaN , TiGeN , TaGeN , TilnN , TaInN , TiHfN or TaHfN , is formed on the high-k dielectric layer 306, Paras [0046], [0047], Figures 4 and 5A) ; forming a second capping layer around the first capping layer, wherein the second capping layer and the first capping layer are made of different materials; and (see e.g., a silicon cap layer 504 is formed on the high-k dielectric cap layer 502, Para [0052], Figures 4 and 5B) Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Gandikota’s teachings of further comprising, after annealing the substrate: forming a first capping layer around the first high-k dielectric layer; forming a second capping layer around the first capping layer, wherein the second capping layer and the first capping layer are made of different materials in the method of Wu constitutes a routine optimization of the gate stack technique relying on known properties of materials in the art to enhance device performance . Wu does not explicitly teach “ removing the second capping layer and the first capping layer to expose the first high-k dielectric layer ” In a similar field of endeavor Siddiqui teaches removing the second capping layer and the first capping layer to expose the first high-k dielectric layer (see e.g., sacrificial metal cap for example, TiN 254 and sacrificial gate filler material, for example, amorphous silicon 256 are formed over the gate dielectric layer 252. The structure is subjected to an anneal process 258 after which the sacrificial metal cap 254 and the sacrificial gate filler material 256 are removed, Column 5, Lines 52-60, Column 6, Lines 1-15, Figures 5 and 6) T herefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Siddiqui’s teachings of removing the second capping layer and the first capping layer to expose the first high-k dielectric layer in the method of Wu to ensure the final metal gate work function and voltage threshold match the design specification with minimal variability. Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 2021/0202323 A1; hereafter Wu) in view of Lisiansky et al. (US 2009/0181530 A1; hereafter Lisiansky ) and further in view of Moriwaki (US 2018/0174926 A1) . Regarding claim 1 2 , Wu, as modified by Lisiansky , teaches the limitations of claim 10 as explained above. Wu further teaches further comprising: forming a second high-k dielectric layer around the first interfacial layer, wherein the first high-k dielectric layer is formed around the second high-k dielectric layer, (see e.g., the high-k dielectric layer 254 maybe a combination of different materials such as metal oxide (e.g., LaO , AlO , ZrO , TiO , Ta.sub.2O.sub.5, Y.sub.2O.sub.3, SrTiO.sub.3 (STO), BaTiO.sub.3 (BTO), BaZrO , HfZrO , HfLaO , HfTaO , HfTiO , ( Ba,Sr )TiO.sub.3 (BST), Al.sub.2O.sub.3, etc.) a metal silicate (e.g., HfSiO , LaSiO , AlSiO , etc.), a metal or semiconductor nitride, a metal or semiconductor oxynitride . Para [0032], Figure 18) . Wu’s high-k dielectric layer may be a combination of different high-k materials . Wu does not explicitly teach “a dielectric constant of the first high-k dielectric layer is greater than a dielectric constant of the second high-k dielectric layer” In a similar field of endeavor Moriwaki teaches a dielectric constant of the first high-k dielectric layer is greater than a dielectric constant of the second high-k dielectric layer (see e.g., dielectric layers 48 and 50 are deposited over the nitrogen doped dielectric material 46. the dielectric material 48 may comprise, consist essentially of, or consist of hafnium oxide, and the dielectric material 50 may comprise, consist essentially of, or consist of aluminum oxide . The dielectric constant of hafnium oxide is greater than the dielectric constant of aluminum oxide, Para [0024], Figure 1). Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively field to implement Moriwaki’s teachings of a dielectric constant of the first high-k dielectric layer is greater than a dielectric constant of the second high-k dielectric layer in the method of Wu in order to optimize the gate dielectric and improve device performance. Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 2021/0202323 A1; hereafter Wu) in view of Lisiansky et al. (US 2009/0181530 A1; hereafter Lisiansky ) and further in view of Moriwaki (US 2018/0174926 A1) and Lee (US 2020/0194267 A1) . Regarding claim 15 , Wu, as modified by Lisiansky , teaches the limitations of claim 10 as explained above. Wu further teaches further comprising: forming a plurality of second nanostructures laterally spaced apart from the plurality of first nanostructures (see e.g., GAA device 20 in the core region has vertically stacked multiple channel members 220 above the substrate 208, Paras [0014], [0018], [0021] Figures 1A, 1B and 18) ; forming a second interfacial layer around the plurality of second nanostructures (see e.g., interfacial layer 252 b formed around the plurality of channel members 220 in the GAA device 20 , Para [0031], Figures 1A, 1B and 18) ; forming a second high-k dielectric layer around the second interfacial layer (see e.g., a high-k dielectric layer 254 b formed around the interfacial layer 252 b , Para [0032], Figures 1A, 1B and 18); forming a second work function layer around the second high-k dielectric layer (see e.g., gate electrode 282 formed around the high-k dielectric layer 254 b , Para [0039], Figures 1A, 1B and 18) . Wu does not explicitly teach “ forming a patterned mask layer around the second high-k dielectric layer; treating a surface of the patterned mask layer; removing the patterned mask layer ; ” Using patterned mask to selectively expose regions, in order to allow selective modification of one region while protecting the other region is well known in the art. In a similar field of endeavor Moriwaki teaches forming a patterned mask layer around the second high-k dielectric layer; treating a surface of the patterned mask layer; removing the patterned mask layer (see e.g., patterned masking layers 82/84 extend across region 90 of the gate dielectric 80. Another region 90 of the gate dielectric layer 80 is not covered by the patterned masking layers 80/82 . The patterned mask is subjected to a nitrogen implant 94 after which it is removed , Para s [0044], [0045], [0055] - [0057], Figures 2- 11 ) ; Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Moriwaki’s teachings of forming a patterned mask layer around the second high-k dielectric layer; treating a surface of the patterned mask layer; removing the patterned mask layer in the method of Wu in order to selectively expose regions so that ions are implanted only in designated zones. Wu does not explicitly teach “removing the patterned mask layer before annealing the substrate” There are two options either perform annealing after removing the patterned mask or before removing the patterned mask. It would be obvious to try any one of the combination. The rationale to support a conclusion that the claim would have been obvious is that “a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely that product [was] not of innovation but of ordinary skill and common sense. In that instance the fact that a combination was obvious to try might show that it was obvious under § 103.”KSR, 550 U.S. at 421, 82 USPQ2d at 1397. MPEP 2143 (E). In a similar field of endeavor Lee provides a generic teaching of providing a mask layer 14M as a barrier to ion implantation. This mask layer 14M may be removed in a subsequent annealing (oxide re-growth) process as shown in Figures 3C and 3D. Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to apply one of the options that is, remove the patterned mask after plasma treatment and before annealing in order to prevent contamination or damage from thermal decomposition of mask materials and ensure uniform thermal oxidation. Claim s 21 -23 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 2021/0202323 A1; hereafter Wu) in view of Min et al. (US 2014/0035058 A1; hereafter Min) and Hattangandy et al. (US 6, 716,695 B1; hereafter Hattangandy ) . Regarding claim 21 , Wu teaches a method for forming a semiconductor structure (see e.g., Figures 1A-1B and 18 ) , comprising: forming a first nanostructure and a second nanostructure over a substrate (see e.g., GAA device s 18 and 20 in the core region including logic and memory circuits region s have vertically stacked multiple channel members 2 20 above the substrate 27, Para [00 21 ], Figures 1A, 1B and 18 ) ; forming a … interfacial layer to surround the first nanostructure (see e.g., interfacial layer 252a formed around the channel members 220 in the GAA device region 18, Para [0031], Figures 1A, 1B and 18) ; forming a thickened interfacial layer to surround the second nanostructure, (see e.g., interfacial layer 252 b formed around the channel members 220 in the GAA device region 2 0 . Interfacial layer 252 b (equivalent to 30 b ) has a greater thickness than the interfacial layer 252a (equivalent to 30a), Para [0015], Figures 1A, 1B and 18) ; forming an n-type work function layer over the … interfacial layer; and forming a p-type work function layer over the thickened interfacial layer. Wu teaches the device structures 206a, 206b and 206c shown in Figure 18 (see e.g., Para [0019]) configured as either n-type or p-type. Wu teaches the formation of separate gate electrodes for n-type and p-type transistors using different metal layers. The work function metal layer in Wu’s disclosure may be tailored to be either p-type or an n-type. Consequently , GAA device 18 may function as an n-type device while GAA device 24 may function as a p-type device with work function layers designed as n-type or p-type accordingly, adhering to the requirements of the device structure. Wu does not explicitly teach “ forming a nitrogen-doped interfacial layer to surround the first nanostructure wherein a nitrogen concentration of the nitrogen-doped interfacial layer is greater than a nitrogen concentration of the … interfacial layer forming an n-type work function layer over the nitrogen-doped interfacial layer; ” In a similar field of endeavor Min teaches forming a nitrogen-doped interfacial layer to surround the first nanostructure wherein a nitrogen concentration of the nitrogen-doped interfacial layer is greater than a nitrogen concentration of the thickened interfacial layer forming an n-type work function layer over the nitrogen-doped interfacial layer (see e.g., The first thin layer pattern 122 may include an oxide of a material , silicon oxide, forming the substrate 100, and the second thin layer pattern 124 may include an oxynitride of a material , silicon oxynitride, forming the substrate 100 . T he second thin layer pattern 124 may include about 2 to 40 wt % of nitrogen based on the total amount of the layer. The first thin layer pattern 122 may substantially exclude nitrogen so that the PMOS transistor has an improved NBTI property, Paras [0044], [0045], Figures 1-8 ) Min teaches performing an annealing step after the nitridation of the interfacial layer of an NMOS transistor. Although Min is silent regarding oxide regrowth during this annealing process, the absence of explicit instruction does not preclude its occurrence. Consequently, the annealing step would result in an uncontrolled oxide regrowth which would increase the thickness of the interfacial layer for the PMOS transistor which possess substantially no nitrogen. Conversely, the nitrogen doped interfacial layer for the NMOS transistor inhibits further oxide growth as taught by Hattangandy . Hattangandy teaches formation of an oxide layer 20 beneath the nitride layer 18 by thermal oxidation of the substrate 10 and nitride layer 18. The nitride layer 18 retards the oxidation, resulting in control over the thickness of the oxide layer 20. Therefore, the combined process results in the NMOS transistor with a thinner nitrogen-doped interfacial layer while the PMOS transistor has a thicker substantially nitrogen free interfacial layer optimizing both devices for different channel functionalities. Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Min ’s teachings of forming a nitrogen-doped interfacial layer to surround the first nanostructure wherein a nitrogen concentration of the nitrogen-doped interfacial layer is greater than a nitrogen concentration of the thickened interfacial layer forming an n-type work function layer over the nitrogen-doped interfacial layer in the method of Wu as higher nitrogen concentration in the NMOS interfacial layer facilitates tailoring desired operational characteristics. Regarding claim 22 , Wu, as modified by M in and Hottangandy , teaches the limitations of claim 21 as mentioned above. Wu further teaches wherein a capacitance equivalent thickness of the interfacial layer is thinner than a capacitance equivalent thickness of the thickened interfacial layer (see e.g., the capacitance equivalent thickness (CET) of the interfacial layer 30a of GAA device 18 is thinner than the CET of the interfacial layer 30 b , Para [0015], Figures 1A, 1B and 18) . Wu does not explicitly teach “ wherein a capacitance equivalent thickness of the nitrogen-doped interfacial layer is thinner than a capacitance equivalent thickness of the thickened interfacial layer ” As established in the analysis of 21, the combination of Min and Hattangandy , inherently yields a structure corresponding to the instant application. Consequently, the resulting device demonstrates a similar functional outcome that is, the capacitance equivalent thickness (CET) of nitrogen doped layer would be thinner than the CET of the thickened interfacial layer. Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to utilize nitrogen doping to achieve a thinner CET for enhanced device performance . Regarding claim 23 , Wu, as modified by Min and Hattangandy , teaches the limitations of claim 21 as mentioned above. Wu further teaches wherein a thickness of the nitrogen-doped interfacial layer is thinner than a thickness of the thickened interfacial layer (see e.g., the thickness of the interfacial layer 30a is less than the thickness of the interfacial layer 30 b , Para [0015], Figures 1A, 1B and 18) . Wu does not explicitly teach “ wherein a thickness of the nitrogen-doped interfacial layer is thinner than a thickness of the thickened interfacial layer” As established in the analysis of 21, the combination of Min and Hattangandy , inherently yields a structure corresponding to the instant application. Consequently, the resulting device demonstrates a similar functional outcome that is, the thickness of the nitrogen doped layer would be thinner than the thickness of the thickened interfacial layer. Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to utilize nitrogen doping so that a thinner interfacial layer can be designed to enhance performance. Claim s 24-25 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 2021/0202323 A1; hereafter Wu) in view of Min et al. (US 2014/0035058 A1; hereafter Min) and Hattangandy et al. (US 6, 716,695 B1; hereafter Hattangan