DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Newly submitted claims 21-23 and 31 are directed to an invention that is independent or distinct from the invention originally claimed for the following reasons:
This application contains claims directed to the following patentably distinct species.
Species A, directed to Figures 3F-3I, for example claims 1, 3-4, 6-11, 13-14 and 26-30 which involve forming n-type and p-type transistor, protecting the p-type transistor with a patterned mask, plasma treating both the transistors with a nitrogen-containing gas and applying an anneal so the n-type transistor forms a nitrogen doped interfacial layer while the interfacial layer of the p-type transistor regrows into a thickened interfacial layer.
Species B, directed to Figure 8 for example, claims 21-23 and 31, which involve forming first, second and third n-type transistors and employs a different nitrogen incorporation sequence. Nitrogen is driven into a first interfacial layer of the first n-type transistor using a first plasma treatment and a first anneal. Thereafter, second nitrogen radicals are driven into both the first interfacial layer and the second interfacial layer using a second plasma treatment and a second anneal. The process is controlled such that the third transistor does not include a nitrogen doped interfacial layer.
The species are independent or distinct because they employ materially different transistor arrangements, masking schemes and nitrogen incorporation sequences. In addition, these species are not obvious variants of each other based on the current record.
Since applicant has received an action on the merits for the originally presented invention, this invention has been constructively elected by original presentation for prosecution on the merits. Accordingly, claims 21-23 and 31 are withdrawn from consideration as being directed to a non-elected invention. See 37 CFR 1.142(b) and MPEP § 821.03.
To preserve a right to petition, the reply to this action must distinctly and specifically point out supposed errors in the restriction requirement. Otherwise, the election shall be treated as a final election without traverse. Traversal must be timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are subsequently added, applicant must indicate which of the subsequently added claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed on July 01, 2026. Claims 1, 3-4, 6-7, 10, 13-14 and 21-23 have been amended. New claims 26-31 have been added. Claims 2, 5, 12, 15-20 and 24-25 have been canceled. Claims 21-23 and 31 have been withdrawn. Currently, claims 1, 3-4, 6-11, 13-14 and 26-30 are pending.
Applicant’s amendment to claims 7, 10 successfully overcomes the 112(a) rejection of claims 7, 10 set forth in the previous Office Action. Cancellation of claim 24 renders moot the 112(a) rejection of claim 24 set forth in the previous Office Action.
Response to Arguments
Applicant's arguments filed on July 01, 2026 have been fully considered but they are not persuasive. The Applicant argues that Hattangandy discloses a nitride layer functioning as an oxidation barrier and does not teach that the oxidation-retarding behavior of a separate nitride layer would necessarily be exhibited by a nitrogen-doped interfacial layer nor the claimed thickness relationship between the two interfacial layers.
The Examiner respectfully disagrees with the assertion. Hattangady is relied upon for the established principle that nitrogen incorporation retards silicon oxide growth. Specifically, Hattangady teaches that during thermal oxidation, a silicon oxide layer 20 grows beneath the nitride layer 18. Because this oxide layer contains amount of nitrogen it functions as a nitrogen-doped layer. The instant specification does not define the claimed “nitrogen-doped interfacial layer” by requiring any particular nitrogen concentration, bonding arrangement or material composition that would distinguish it from other nitrogen-containing silicon-based interfacial layers.
Accordingly, when the combined teachings of the cited references are considered, one of ordinary skill in the art would have reasonably expected the nitrogen-doped first interfacial layer to undergo less oxidation and interfacial layer regrowth during annealing than the non-nitrogen doped second interfacial layer. Because the second interfacial layer is not subject to the same oxidation retarding effect, it predictable regrows to a greater extent during annealing and therefore, becomes thicker than the nitrogen doped first interfacial layer.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1, 3-4 and 6-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as failing to set forth the subject matter which the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the applicant regards as the invention.
Regarding claim 1, the claim recites, “form a thickened interfacial layer that is greater than the nitrogen-doped interfacial layer” is indefinite as it is unclear which characteristic of the thickened interfacial layer is being compared with the nitrogen-doped interfacial layer. For example, it is unclear whether the thickened interfacial layer is greater in thickness, volume, amount of growth, nitrogen concentration or some other structural or compositional property.
Claims 3-4 and 6-9 depend upon claim 1 and do not rectify the problem therefore, they are also rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 7-9 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 2021/0202323 A1; hereafter Wu) in view of Moriwaki (US 2018/0174926 A1), Lisiansky et al. (US 2009/0181530 A1; hereafter Lisiansky) and Hattangady et al. (US 6,716,695 B1; hereafter Hattangady).
Regarding claim 1, Wu teaches a method for forming a semiconductor structure (see e.g., Figures 1A-1B and 18), comprising:
forming a first nanostructure and a second nanostructure over a substrate (see e.g., GAA devices 18 and 20 in the core area including logic and memory circuits have vertically stacked multiple channel members 26 above the substrate 27, Para [0014], Figures 1A, 1B);
forming a first interfacial layer on the first nanostructure and a second interfacial layer on the second nanostructure (see e.g., the channel members 26 of the GAA devices 18 and 20 are wrapped around by interfacial layers 30a and 30b respectively, Para [0014], Figures 1A, 1B);
forming a first gate dielectric layer on the first interfacial layer and a second gate dielectric layer on the second interfacial layer (see e.g., GAA devices 18 and 20 include high-k dielectric layers 32a, and 32b respectively formed on the respective interfacial layers, Para [0014], Figures 1A, 1B);
wherein the second interfacial layer regrows in the step of annealing the substrate to form a thickened interfacial layer (see e.g., an annealing process 270 initiates oxide regrowth process on the interfacial layer 252b. After the annealing process the thickness of the interfacial layer 252b is larger than the thickness of the interfacial layer 252a, Para [0034], Figure 15)
Wu does not explicitly teach
“forming a patterned mask layer on the second gate dielectric layer while exposing the first gate dielectric layer;
plasma treating the first gate dielectric layer and the patterned mask layer using a nitrogen- containing gas”;
Using patterned mask to selectively expose regions, in order to allow selective modification of one region while protecting the other region is well known in the art.
In a similar field of endeavor Moriwaki teaches
forming a patterned mask layer on the second gate dielectric layer while exposing the first gate dielectric layer (see e.g., patterned masking layers 82/84 extend across region 90 of the gate dielectric 80. Another region 90 of the gate dielectric layer 80 is not covered by the patterned masking layers 80/82, Para [0044], Figures 2-5);
plasma treating the first gate dielectric layer and the patterned mask layer using a nitrogen- containing gas; and (see e.g., construction 10a is exposed to nitrogen plasma 94 which is implanted in the exposed region 92 of the gate dielectric layer 80 while the other region 90 of the gate dielectric layer is protected by the blocking mass 88, Para [0045], Figure 5)
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Moriwaki’s teachings of driving nitrogen into the first interfacial layer, thereby forming a nitrogen-doped interfacial layer, wherein driving nitrogen into the first interfacial layer through the first gate dielectric layer comprises: annealing the substrate so that nitrogen diffuses through the first gate dielectric layer into the first interfacial layer in the method of Wu in order to selectively expose regions so that ions are implanted only in designated zones.
Wu does not explicitly teach
“driving nitrogen into the first interfacial layer, thereby forming a nitrogen-doped interfacial layer, wherein driving nitrogen into the first interfacial layer through the first gate dielectric layer comprises:
annealing the substrate so that nitrogen diffuses through the first gate dielectric layer into the first interfacial layer”.
In a similar field of endeavor Lisiansky teaches
driving nitrogen into the first interfacial layer, thereby forming a nitrogen-doped interfacial layer, wherein driving nitrogen into the first interfacial layer through the first gate dielectric layer comprises: (see e.g., an amorphous high-k dielectric layer 213 is formed on an insulating silicon oxide layer 211. Nitrogen ions 215 are implanted into the upper surface of the amorphous high-k dielectric layer 213 followed by annealing process at a temperature of 830.degree.C or higher. As a result, the amorphous high-k dielectric layer 213 is transformed into a nitrided crystalline high-k dielectric layer 214. The nitrogen ions 215 exhibit a low segregation coefficient in the crystalline high-k dielectric layer 214, thereby resulting in an efficient out-diffusion of atomic nitrogen from this layer 214 into the adjacent silicon oxide layer 211. The nitrogen that diffuses into silicon oxide layer 211 is labeled with reference number 216 in FIG. 2E. As a result, silicon oxide layer 211 advantageously becomes strongly nitride, Paras [0027], [0028], [0033], Figures 2A-2E),
annealing the substrate so that nitrogen diffuses through the first gate dielectric layer into the first interfacial layer (see e.g., after nitridation, the structure is exposed to high temperature which causes the nitrogen 216 to diffuse into the silicon oxide layer 211 to become nitride, Para [0033], Figures 2D-2E).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Lisiansky’s teachings of driving nitrogen into the first interfacial layer, thereby forming a nitrogen-doped interfacial layer, wherein driving nitrogen into the first interfacial layer through the first gate dielectric layer comprises: annealing the substrate so that nitrogen diffuses through the first gate dielectric layer into the first interfacial layer in the method of Wu in order to optimize gate dielectric of the CMOS transistor to be used for specific circuit purpose.
Wu does not explicitly teach
“wherein the second interfacial layer ….. form a thickened interfacial layer that is greater than the nitrogen-doped interfacial layer”.
However, this structural difference is the result of applying known techniques to optimize interfacial layers.
In a similar field of endeavor Hattangady teaches formation of an oxide layer 20 beneath the nitride layer 18 by thermal oxidation of the substrate 10 and nitride layer 18. The nitride layer 18 retards the oxidation, resulting in control over the thickness of the oxide layer 20. This oxide layer 20 contains amount of nitrogen and functions as a nitrogen-doped layer.
One of ordinary skill in the art would have reasonably expected the nitrogen-doped first interfacial layer to undergo less oxidation and interfacial layer regrowth during annealing than the non-nitrogen doped second interfacial layer. Because the second interfacial layer is not subject to the same oxidation retarding effect, it predictable regrows to a greater extent during annealing and therefore, becomes thicker than the nitrogen doped first interfacial layer.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to optimize device performance by manipulating interfacial thickness via controlled oxidation.
Regarding claim 7, Wu, as modified by Moriwaki, Lisiansky and Hattangady, teaches the limitations of claim 1 as mentioned above. Wu further teaches
further comprising:
forming a first gate electrode layer on the first gate dielectric layer (see e.g., gate electrode layer 282 formed around the GAA device 18 in the core area, Paras [0015], [0039], Figures 1A, 1B and 18), wherein the first gate electrode layer, the first gate dielectric layer, the …. interfacial layer and the first nanostructure form a first transistor; and (see e.g., the gate electrode 282, high-k dielectric 254a and interfacial layer 252a and the nanowires 220 form a first transistor in the core region, Figure 18)
forming a second gate electrode layer on the second gate dielectric layer (see e.g., gate electrode layer 282 formed around the GAA device 20 in the core area, Paras [0015], [0039], Figures 1A, 1B and 18), wherein the second gate electrode layer, the second gate dielectric layer, the second interfacial layer and the second nanostructure form a second transistor (see e.g., gate electrode 282, high-k dielectric 254b, the interfacial layer 252b and nanowires 220 form the second transistor in the core area, Paras [0015], [0039], Figures 1A, 1B and 18),
wherein the first transistor has a first capacitance equivalent thickness (see e.g., the GAA device 18 in the core area includes an interfacial layer 252a and a gate dielectric layer 254a (equivalent to 30a and 32a) has the thinnest capacitance equivalent thickness suitable for high-speed switching, Para [0015], Figures 1A, 1B and 18) , and the second transistor has a second capacitance equivalent thickness that is thinner than the first capacitance equivalent thickness (see e.g., the GAA device 20 in the core area includes an interfacial layer 252b and a gate dielectric 254b (equivalent to 30b and 32b) has a thicker gate dielectric layer suitable for low voltage and low leakage applications, Para [0015], Figure 1A, 1B and 18).
Wu does not explicitly teach
“wherein the first gate electrode layer, the first gate dielectric layer, the nitrogen-doped interfacial layer and the first nanostructure form a first transistor”;
In a similar field of endeavor Hattangady teaches
wherein the first gate electrode layer, the first gate dielectric layer, the nitrogen-doped interfacial layer and the first nanostructure form a first transistor (see e.g., oxide layer 20, nitride layer 20, gate dielectric 24 and conductive layer 26 and the underlying channel form a transistor, Figure 1G);
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Hattangandy’s teachings of wherein the first gate electrode layer, the first gate dielectric layer, the nitrogen-doped interfacial layer and the first nanostructure form a first transistor to achieve the expected functionality of a transistor to obtain improved gate to channel coupling and device performance.
Regarding claim 8, Wu, as modified by Moriwaki, Lisiansky and Hattangady, teaches the limitations of claim 7 as mentioned above. Wu further teaches
wherein the first transistor has a first threshold voltage greater than zero, and the second transistor has a second threshold voltage greater than the first threshold voltage (see e.g., GAA device 18 has a thin capacitance equivalent thickness (CET) while GAA device 24 has a thick CET. Therefore, the threshold voltage of GAA device 24 would be higher).
Regarding claim 9, Wu, as modified by Moriwaki, Lisiansky and Hattangady, teaches the limitations of claim 1 as mentioned above. Wu further teaches
wherein the first nanostructure is formed in a logic device region of the substrate, and the second nanostructure is formed in a memory device region of the substrate (see e.g., GAA devices 18 and 20 are formed in the core area which includes logic circuits, memory circuits and other core circuits. GAA device 18 has a thin capacitance equivalent thickness to provide high speed operation and hence is suitable for logic circuits. GAA device 20 has a thicker CET and is suitable for low power low leakage applications in memory circuits, Paras [0013], [0015], Figures 1A, 1B).
Regarding claim 27, Wu, as modified by Moriwaki, Lisiansky and Hattangady, teaches the limitations of claim 7 as mentioned above. Wu further teaches
Wu discloses that p-type GAA devices are formed over n-type wells, while n-type GAA devices are formed over p-type wells. Each of the device structures 206a, 206b, and 206c may individually be an n-type or a p-type device. Therefore, 206a may represent an n-type device formed over an n-type device region while device structure 206b may represent a p-type device formed over a p-type device region.
wherein the first transistor is an n-channel nanostructure transistor and the second transistor is a p-channel nanostructure transistor (see e.g., GAA device 206a and 206b in the core region have vertically stacked multiple channel members 220 above the substrate 208, 206a may represent an n-type device and 206b may represent a p-type device, Paras [0014], [0018], [0021] Figures 1A, 1B, 15, 17 and 18);
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 2021/0202323 A1; hereafter Wu) in view of Moriwaki (US 2018/0174926 A1), Lisiansky et al. (US 2009/0181530 A1; hereafter Lisiansky) and Hattangady et al. (US 6,716,695 B1; hereafter Hattangady) and further in view of Wang et al. (US 2006/0131672 A1; hereafter Wang).
Regarding claim 3, Wu, as modified by Moriwaki, Lisiansky and Hattangady, teaches the limitations of claim 1 as mentioned above. Wu does not explicitly teach
“wherein plasma treating the first gate dielectric layer and the patterned mask layer with the nitrogen-containing gas is performed at a first temperature, and annealing the substrate is performed at a second temperature that is greater than the first temperature”.
In a similar field of endeavor Lisiansky teaches
wherein plasma treating the first gate dielectric layer and the patterned mask layer with the nitrogen-containing gas is performed at a first temperature, and annealing the substrate is performed at a second temperature that is greater than the first temperature (see e.g., implanting nitrogen into the high-k dielectric layer 6 by plasma treatment and one or more bakes in a gas environment containing nitrogen atoms example N.sub.2, N.sub.2O, NO and/or NH.sub.3. The annealing is performed at a temperature of 830.degree. C. or higher, which represents the crystallization temperature of amorphous alumina).
Lisiansky does not specify the temperature during the nitridation process.
However, as taught by Wang plasma nitridation process is performed at about 550.degree. C. for about 1 minute in nitrogen or decoupled plasma nitridation is performed at about 25.degree. C. (or at room temperature) for about 30 seconds in nitrogen (see e.g., paras [0032], [0033]).
Lisiansky when combined with the teaching of Wang, which teaches plasma nitridation at 550.degree.C or room temperature, provides a specific lower temperature nitrogen incorporation method compared to typical subsequent anneals. For instance, post-nitridation annealing is performed at high temperatures which exceed 830.degree.C to optimize dielectric integrity.
Therefore, it would be obvious to one skilled in the art at the time the invention was effectively filed to implement Lisiansky’s teachings of wherein plasma treating the first gate dielectric layer and the patterned mask layer with the nitrogen-containing gas is performed at a first temperature, and annealing the substrate is performed at a second temperature that is greater than the first temperature in the device of Wu in order to improve reliability and performance for both peripheral and core devices.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 2021/0202323 A1; hereafter Wu) in view of Moriwaki (US 2018/0174926 A1), Lisiansky et al. (US 2009/0181530 A1; hereafter Lisiansky) and Hattangady et al. (US 6,716,695 B1; hereafter Hattangady) and further in view of Lee (US 2020/0194267 A1).
Regarding claim 4, Wu, as modified by Moriwaki, Lisiansky and Hattangady, teaches the limitations of claim 1 as mentioned above. Wu does not explicitly teach
“further comprising: removing the patterned mask layer to expose the second gate dielectric layer after plasma treating and before annealing the substrate”.
There are two options either perform annealing after removing the patterned mask or before removing the patterned mask. It would be obvious to try any one of the combination. The rationale to support a conclusion that the claim would have been obvious is that “a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely that product [was] not of innovation but of ordinary skill and common sense. In that instance the fact that a combination was obvious to try might show that it was obvious under § 103.”KSR, 550 U.S. at 421, 82 USPQ2d at 1397. MPEP 2143 (E).
In a similar field of endeavor Lee provides a generic teaching of providing a mask layer 14M as a barrier to ion implantation. This mask layer 14M may be removed in a subsequent annealing (oxide re-growth) process as shown in Figures 3C and 3D.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to apply one of the options that is, remove the patterned mask after plasma treatment and before annealing in order to prevent contamination or damage from thermal decomposition of mask materials and ensure uniform thermal oxidation.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 2021/0202323 A1; hereafter Wu) in view of Moriwaki (US 2018/0174926 A1), Lisiansky et al. (US 2009/0181530 A1; hereafter Lisiansky) and Hattangady et al. (US 6,716,695 B1; hereafter Hattangady) and further in view of Burnham et al. (US 2006/0281265 A1).
Regarding claim 6, Wu, as modified by Moriwaki, Lisiansky and Hattangady, teaches the limitations of claim 1 as mentioned above. Wu does not explicitly teach
“wherein the nitrogen-containing gas is activated to form the nitrogen radical, and the nitrogen radical is adsorbed onto a surface of the first gate dielectric layer”.
In a similar field of endeavor Burnham teaches
wherein the nitrogen-containing gas is activated to form the nitrogen radical, and the nitrogen radical is adsorbed onto a surface of the first gate dielectric layer (see e.g., Remote plasma nitridation (RPN) using microwave or decoupled plasma nitridation (DPN) using radio frequency may interact with a nitrogen-containing gas to generate plasma containing nitrogen radicals. Areas 810, 820 are exposed to the nitrogen radicals, Para [0039], Figures 8-10).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Burnham’s teachings of wherein the nitrogen-containing gas is activated to form the nitrogen radical, and the nitrogen radical is adsorbed onto a surface of the first gate dielectric layer in the method of Wu as nitrogen radical adsorption onto the surface of the dielectric is a known mechanism for forming high-quality interfacial layers.
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 2021/0202323 A1; hereafter Wu) in view of Moriwaki (US 2018/0174926 A1), Lisiansky et al. (US 2009/0181530 A1; hereafter Lisiansky) and Hattangady et al. (US 6,716,695 B1; hereafter Hattangady) and further in view of Okuno et al. (6,110,842; hereafter Okuno).
Regarding claim 26, Wu, as modified by Moriwaki, Lisiansky and Hattangady, teaches the limitations of claim 7 as mentioned above. Wu does not explicitly teach
“wherein plasma treating the first gate dielectric layer and the patterned mask layer using the nitrogen-containing gas is performed in a time of about 10 microseconds to about 1000 microseconds”.
"[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, "[i]t is a settled principle of law that a mere carrying forward of an original patented conception involving only change of form, proportions, or degree, or the substitution of equivalents doing the same thing as the original invention, by substantially the same means, is not such an invention as will sustain a patent, even though the changes of the kind may produce better results than prior inventions." In re Williams, 36 F.2d 436, 438 (CCPA 1929).
In a similar field of endeavor Okuno teaches
wherein plasma treating the first gate dielectric layer and the patterned mask layer using the nitrogen-containing gas is performed in a time of about 10 microseconds to about 1000 microseconds (see e.g., mask 44 is formed over a dielectric 42 and a plasma nitridation is performed in the range of 1 second to 60 seconds, Column 4, Lines 42-64, Figures 2A and 2B).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Okuno’s teachings of wherein plasma treating the first gate dielectric layer and the patterned mask layer using the nitrogen-containing gas is performed in a time of about 10 microseconds to about 1000 microseconds in the method of Wu in order to determine an appropriate plasma treatment duration that provides the desired degree of surface nitridation in view of plasma conditions and dielectric dimensions.
Claims 10, 13-14 and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 2021/0202323 A1; hereafter Wu) in view of Lisiansky et al. (US 2009/0181530 A1; hereafter Lisiansky), Chiang et al. (US 10,937,704 B1; hereafter Chiang), Burnham et al. (US 2006/0281265 A1; hereafter Burnham) and Zhang et al. (US 2020/0373300 A1; hereafter Zhang).
Regarding claim 10, Wu teaches a method for forming a semiconductor structure (see e.g., Figures 1A-1B, 15, 17 and 18), comprising:
Wu discloses that p-type GAA devices are formed over n-type wells, while n-type GAA devices are formed over p-type wells. Each of the device structures 206a, 206b, and 206c may individually be an n-type or a p-type device. Therefore, 206a may represent an n-type device formed over an n-type device region while device structure 206b may represent a p-type device formed over a p-type device region.
forming a plurality of first nanostructures over an n-type device region of a substrate (see e.g., GAA device 206a in the core region has vertically stacked multiple channel members 220 above the substrate 208, 206a may represent an n-type device, Paras [0014], [0018], [0021] Figures 1A, 1B, 15, 17 and 18);
forming a plurality of second nanostructures over a p-type device region of the substrate (see e.g., GAA device 206b in the core region has vertically stacked multiple channel members 220 above the substrate 208, 206b may represent a p-type device, Paras [0014], [0018], [0021] Figures 1A, 1B, 15, 17 and 18)
forming a first interfacial layer and a second interfacial layer around the plurality of first nanostructures and the plurality of second nanostructures, respectively (see e.g., interfacial layer 252a and 252b are formed around the plurality of channel members 220 in the GAA devices 206a and 206b respectively, Para [0031], Figures 1A, 1B, 15, 17 and 18);
forming a first high-k dielectric layer and a second high-k dielectric layer around the first interfacial layer and the second interfacial layer, respectively (see e.g., high-k dielectric layer 254a and 254b formed around the interfacial layers 252a and 252b respectively, Para [0032], Figures 1A, 1B, 15, 17 and 18);
forming a p-type work function layer around …. the second high-k dielectric layer;
forming an n-type work function layer around the first high-k dielectric layer ….; and forming a metal fill layer around the n-type work function layer (see e.g., gate electrode 282 formed around the high-k dielectric layer 254a and 254b. The gate electrode layer 282 may be formed separately for n-type and p-type transistors which may use different metal layers. The work function metal layer may be a p-type or an n-type work function layer. The gate electrode layer 282 may comprise multiple work function metal layers, such as a first metal layer and a second metal layer. The gate electrode layer 282 also includes a metal fill layer, Para [0039], Figures 1A, 1B, 15, 17 and 18).
Wu does not explicitly teach
“treating a surface of the first high-k dielectric layer so that a nitrogen radicle adsorbs onto the surface of the first high-k dielectric layer;
annealing the substrate to drive the nitrogen radicle into the first interfacial layer;”
In a similar field of endeavor Lisiansky teaches
treating a surface of the first high-k dielectric layer so that a nitrogen radicle adsorbs onto the surface of the first high-k dielectric layer;
annealing the substrate to drive the nitrogen radicle into the first interfacial layer (see e.g., An amorphous high-k dielectric layer 213 is formed on an insulating silicon oxide layer 211. Nitrogen is introduced into amorphous high-k dielectric layer 213 by plasma treatment in an environment containing nitrogen atoms, such as N.sub.2, N.sub.2O or NH.sub.3, including neutral or activated nitrogen species. This is followed by annealing process at a temperature of 830.degree.C or higher. As a result, the amorphous high-k dielectric layer 213 is transformed into a nitrided crystalline high-k dielectric layer 214. The nitrogen species 215 exhibit a low segregation coefficient in the crystalline high-k dielectric layer 214, thereby resulting in an efficient out-diffusion of atomic nitrogen from this layer 214 into the adjacent silicon oxide layer 211. The nitrogen that diffuses into silicon oxide layer 211 is labeled with reference number 216 in FIG. 2E. As a result, silicon oxide layer 211 advantageously becomes strongly nitride, Paras [0027], [0028], [0031], [0033], Figures 2A-2E).
The neutral or activated nitrogen species utilized in plasma treatment include nitrogen radicals which contact and adsorb onto the exposed surface of he high-k dielectric layer as taught by Burnham (see e.g., Para [0039], Figure 8).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Lisiansky’s teachings of treating a surface of the first high-k dielectric layer so that a nitrogen radicle adsorbs onto the surface of the first high-k dielectric layer; annealing the substrate to drive the nitrogen radicle into the first interfacial layer in the method of Wu in order to optimize the CET leading to improved electrical performance in the final CMOS device.
Wu does not explicitly teach
“forming a patterned mask layer to surround the second high-k dielectric layer;
removing the patterned mask layer”;
In a similar field of endeavor Zhang teaches
forming a patterned mask layer to surround the second high-k dielectric layer (see e.g., a patterning layer 502 deposited over dielectric layer 404 on the channel layer 110 and fill in the gap between each channel layer 110 for nanosheet stacks 106, Para [0064], Figures 7 and 8);
removing the patterned mask layer (see e.g., the patterning layer 502 on the nanosheet stack 106 is removed after the selective dielectric modification is performed on the transistor 104, Para [0065], Figures 7 and 8);
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Zhang’s teachings of forming a patterned mask layer to surround the second high-k dielectric layer; removing the patterned mask layer in the method of Wu in order to allow selective processing of exposed transistor regions while protecting the covered transistor regions.
Wu does not explicitly teach
“forming a p-type work function layer around the first high-k dielectric layer and the second high-k dielectric layer;
removing a portion of the p-type work function layer in the n-type device region of the substrate;
forming an n-type work function layer around the first high-k dielectric layer and a portion of the p-type work function layer over the p-type device region”;
In a similar field of endeavor Chiang teaches
forming a p-type work function layer around the first high-k dielectric layer and the second high-k dielectric layer (see e.g., a first conductive material 202, a p-type work function metal, is formed around the p-type channel stack 101 and the n-type channel stack 103, Column 4, Lines 58-67, Figures 2 and 3A);
removing a portion of the p-type work function layer in the n-type device region of the substrate (see e.g., etching process 308 applied to the n-type channel stack 103 to fully remove the first conductive material 202, Column 5, Lines 38-40, Figure 3C);
forming an n-type work function layer around the first high-k dielectric layer and a portion of the p-type work function layer over the p-type device region (see e.g., a second conductive material 310, an n-type work function metal, surrounds the p-type channel stack 101 and the n-type channel stack 103, Column 6, Lines 15-22, Figure 3D);
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Chiang’s teachings of forming a p-type work function layer around the first high-k dielectric layer and the second high-k dielectric layer;
removing a portion of the p-type work function layer in the n-type device region of the substrate;
forming an n-type work function layer around the first high-k dielectric layer and a portion of the p-type work function layer over the p-type device region in the method of Wu in order to improve threshold voltages of the p-type and n-type devices.
Regarding claim 13, Wu, as modified by Lisiansky, Chiang, Burnham and Zhang, teaches the limitations of claim 10 as explained above. Wu does not explicitly teach
“wherein after annealing the substrate, a nitrogen concentration of the interfacial layer increases from an interior of the interfacial layer to an interface between the interfacial layer and the first high-k dielectric layer”.
In a similar field of endeavor Lisiansky teaches
wherein after annealing the substrate, a nitrogen concentration of the interfacial layer increases from an interior of the interfacial layer to an interface between the interfacial layer and the first high-k dielectric layer (see e.g., an amorphous high-k dielectric layer 213 is formed on an insulating silicon oxide layer 211. Nitrogen species 215 are implanted into the upper surface of the amorphous high-k dielectric layer 213 followed by annealing process at a temperature of 830.degree.C or higher. As a result, the amorphous high-k dielectric layer 213 is transformed into a nitrided crystalline high-k dielectric layer 214. The nitrogen species 215 exhibit a low segregation coefficient in the crystalline high-k dielectric layer 214, thereby resulting in an efficient out-diffusion of atomic nitrogen from this layer 214 into the adjacent silicon oxide layer 211. The nitrogen that diffuses into silicon oxide layer 211 is labeled with reference number 216 in FIG. 2E. As a result, silicon oxide layer 211 advantageously becomes strongly nitride, Paras [0027], [0028], [0033], Figures 2A-2E)
As nitrogen diffuses from the upper high-k layer downwards into the interfacial layer, the resulting nitrogen concentration in the interfacial layer is higher at the interface with the high-k dielectric and lower in the interior of the interfacial layer creating a graded concentration.
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Lisiansky’s teachings of wherein after annealing the substrate, a nitrogen concentration of the interfacial layer increases from an interior of the interfacial layer to an interface between the interfacial layer and the first high-k dielectric layer in the method of Wu in order to optimize the CET leading to improved electrical performance in the final CMOS device.
Regarding claim 14, Wu, as modified by Lisiansky, Chiang, Burnham and Zhang, teaches the limitations of claim 10 as explained above. Wu does not explicitly teach
“wherein the nitrogen radical is driven into the first interfacial layer to form a doped interfacial layer, and a dielectric constant of the doped interfacial layer is greater than a dielectric constant of the first interfacial layer”.
In a similar field of endeavor Lisiansky teaches
wherein the nitrogen radical is driven into the first interfacial layer to form a doped interfacial layer (see e.g., Nitrogen ions 215 are implanted into the upper surface of the amorphous high-k dielectric layer 213 followed by annealing process at a temperature of 830.degree.C or higher. As a result, the amorphous high-k dielectric layer 213 is transformed into a nitrided crystalline high-k dielectric layer 214. The nitrogen ions 215 exhibit a low segregation coefficient in the crystalline high-k dielectric layer 214, thereby resulting in an efficient out-diffusion of atomic nitrogen from this layer 214 into the adjacent silicon oxide layer 211. The nitrogen that diffuses into silicon oxide layer 211 is labeled with reference number 216 in FIG. 2E. As a result, silicon oxide layer 211 advantageously becomes strongly nitride, Paras [0027], [0028], [0033], Figures 2A-2E), and a
dielectric constant of the doped interfacial layer is greater than a dielectric constant of the first interfacial layer (see e.g. nitride silicon oxide layer has a higher dielectric constant than the silicon oxide layer. The resulting structure is similar to that of the instant application therefore the outcome must also be similar)
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Lisiansky’s teachings of wherein the dopant is driven into the first interfacial layer to form a doped interfacial layer, and a dielectric constant of the doped interfacial layer is greater than a dielectric constant of the first interfacial layer in the method of Wu in order to optimize the CET leading to improved electrical performance in the final CMOS device.
Regarding claim 30, Wu, as modified by Lisiansky, Chiang, Burnham and Zhang, teaches the limitations of claim 10 as explained above. Wu does not explicitly teach
“wherein the patterned mask layer partially fills a gap between adjacent two of second nanostructures”.
In a similar field of endeavor Zhang teaches
wherein the patterned mask layer partially fills a gap between adjacent two of second nanostructures (see e.g., a patterning layer 502 deposited over dielectric layer 404 on the channel layer 110 and fill in the gap between each channel layer 110 for nanosheet stacks 106, Para [0064], Figure 7);
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Zhang’s teachings of wherein the patterned mask layer partially fills a gap between adjacent two of second nanostructures in the method of Wu in order to allow selective processing of exposed transistor regions while protecting the covered transistor regions.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 2021/0202323 A1; hereafter Wu) in view of Lisiansky et al. (US 2009/0181530 A1; hereafter Lisiansky), Chiang et al. (US 10,937,704 B1; hereafter Chiang), Burnham et al. (US 2006/0281265 A1; hereafter Burnham) and Zhang et al. (US 2020/0373300 A1; hereafter Zhang) and further in view of Gandikota et al. (US 2021/0111020 A1; hereafter Gandikota) and Siddiqui et al. (US 9,741,720 B1; hereafter Siddiqui).
Regarding claim 11, Wu, as modified by Lisiansky, Chiang, Burnham and Zhang, teaches the limitations of claim 10 as explained above. Wu does not explicitly teach
“further comprising, after annealing the substrate:
forming a first capping layer around the first high-k dielectric layer;
forming a second capping layer around the first capping layer, wherein the second capping layer and the first capping layer are made of different materials;”.
In a similar field of endeavor Gandikota teaches
further comprising, after annealing the substrate (see e.g., after subjecting a high-k dielectric 306 to a plasma nitridation process followed by a post nitridation anneal process, Paras [0043], [0044], Figure 2):
forming a first capping layer around the first high-k dielectric layer (see e.g., after the nitridation and post nitridation anneal process a metal gate structure 500 is formed over the gate dielectric layer 306. A high-k dielectric capping layer 502, metal nitride material including titanium (Ti) or tantalum (Ta) doped with silicon (Si), aluminum (Al), gallium (Ga), germanium (Ge), indium (In), or hafnium (Hf), such as TiSiN, TaSiN, TiAlN, TaAlN, TiGaN, TaGaN, TiGeN, TaGeN, TilnN, TaInN, TiHfN or TaHfN, is formed on the high-k dielectric layer 306, Paras [0046], [0047], Figures 4 and 5A);
forming a second capping layer around the first capping layer, wherein the second capping layer and the first capping layer are made of different materials; and (see e.g., a silicon cap layer 504 is formed on the high-k dielectric cap layer 502, Para [0052], Figures 4 and 5B)
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Gandikota’s teachings of further comprising, after annealing the substrate:
forming a first capping layer around the first high-k dielectric layer; forming a second capping layer around the first capping layer, wherein the second capping layer and the first capping layer are made of different materials in the method of Wu constitutes a routine optimization of the gate stack technique relying on known properties of materials in the art to enhance device performance.
Wu does not explicitly teach
“removing the second capping layer and the first capping layer to expose the first high-k dielectric layer”
In a similar field of endeavor Siddiqui teaches
removing the second capping layer and the first capping layer to expose the first high-k dielectric layer (see e.g., sacrificial metal cap for example, TiN 254 and sacrificial gate filler material, for example, amorphous silicon 256 are formed over the gate dielectric layer 252. The structure is subjected to an anneal process 258 after which the sacrificial metal cap 254 and the sacrificial gate filler material 256 are removed, Column 5, Lines 52-60, Column 6, Lines 1-15, Figures 5 and 6)
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Siddiqui’s teachings of removing the second capping layer and the first capping layer to expose the first high-k dielectric layer in the method of Wu to ensure the final metal gate work function and voltage threshold match the design specification with minimal variability.
Claims 28 and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al. (US 2021/0202323 A1; hereafter Wu) in view of Lisiansky et al. (US 2009/0181530 A1; hereafter Lisiansky), Chiang et al. (US 10,937,704 B1; hereafter Chiang), Burnham et al. (US 2006/0281265 A1; hereafter Burnham) and Zhang et al. (US 2020/0373300 A1; hereafter Zhang) and further in view of Chu et al. (US 2021/0366783 A1; hereafter Chu) and Chang et al. (US 2021/0399104 A1; hereafter Chang).
Regarding claim 28, Wu, as modified by Lisiansky, Chiang, Burnham and Zhang, teaches the limitations of claim 10 as explained above. Wu further teaches
wherein forming the first high-k dielectric layer comprises:
depositing a first high-k dielectric material (see e.g., forming a high-k dielectric layer 254a for device structure 206a, Para [0032], Figure 18);
Wu does not explicitly teach
“forming an n-type dipole material over the first high-k dielectric material;
driving the n-type dipole material into the first high-k dielectric material;
removing the n-type dipole material; and”
In a similar field of endeavor Chu teaches
forming an n-type dipole material over the first high-k dielectric material (see e.g., device 200B may be n-type or p-type transistor. A high-k dielectric layer 282 is deposited on an interfacial layer 280. A dipole layer 410 deposited on the high-k dielectric layer 282 of transistor 200B.
Where the transistor 200B is an n-type transistor, the dipole elements may be lanthanum, yttrium, strontium, or some other chemical elements, and the dipole layer 410 may include an oxide or a nitride of the dipole elements. For example, the dipole layer 410 may include La.sub.2O.sub.3, Y.sub.2O.sub.3, SrO, LaN, YN, Sr.sub.3N.sub.2, or other suitable materials.
Where the transistor 200B is a p-type transistor, the dipole elements may be aluminum, titanium, niobium, or scandium, or some other chemical elements, and the dipole layer 410 may include an oxide or a nitride of the dipole elements. For example, the dipole layer 410 may include Al.sub.2O.sub.3, TiO.sub.2, niobium oxide (e.g., Nb.sub.2O.sub.5), AlN, TiN, NbN, or other suitable materials.
The dipole pattern 410 is for n-type transistor, Paras [0024], [0026], [0031], [0035], [0041], Figures 4D);
driving the n-type dipole material into the first high-k dielectric material (see e.g., A dipole drive-in process is performed so that the dipole materials from the dipole pattern 410 are driven into the gate dielectric layer. The dipole drive-in process is an annealing process, Para [0035], Figures 4D);
removing the n-type dipole material; and (see e.g., dipole pattern 410 is removed by applying etching techniques, Para [0036], Figure 7)
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Chu’s teachings of forming an n-type dipole material over the first high-k dielectric material; driving the n-type dipole material into the first high-k dielectric material; removing the n-type dipole material in the method of Wu in order to modify the dipole characteristics and effective work function of the high-k gate dielectric in the n-type device region.
Wu does not explicitly teach
“depositing a second high-k dielectric material after removing the n-type dipole material”.
In a similar field of endeavor Chang teaches
depositing a second high-k dielectric material after removing the n-type dipole material (see e.g., a second high-k material is deposited over the first high-k layer after driving the dipole elements and removing the dipole layer. For transistor 200N, high-k dielectric 286 is deposited over the layer 284n, Figures 8, 9, 14, 15 and 16).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Chang’s teachings of depositing a second high-k dielectric material after removing the n-type dipole material in the method of Wu in order to preserve the dipole species incorporated in the first high-k gate dielectric and provide a desired overall gate dielectric thickness.
Regarding claim 29, Wu, as modified by Lisiansky, Chiang, Burnham and Zhang, teaches the limitations of claim 28 as explained above. Wu further teaches
wherein forming the second high-k dielectric layer comprises:
depositing the first high-k dielectric material (see e.g., forming a high-k dielectric layer 254b for device structure 206b, Para [0032], Figure 18);
Wu does not explicitly teach
“forming a p-type dipole material over the first high-k dielectric material, wherein the p-type dipole material is different from the n-type dipole material;
driving the p-type dipole material into the first high-k dielectric material;
removing the p-type dipole material; and”
In a similar field of endeavor Chu teaches
forming a p-type dipole material over the first high-k dielectric material, wherein the p-type dipole material is different from the n-type dipole material (see e.g., device 200D may be n-type or p-type transistor. A high-k dielectric layer 282 is deposited on an interfacial layer 280. A dipole layer 410 deposited on the high-k dielectric layer 282 of transistor 200B.
Where the transistor 200D is an n-type transistor, the dipole elements may be lanthanum, yttrium, strontium, or some other chemical elements, and the dipole layer 420 may include an oxide or a nitride of the dipole elements. For example, the dipole layer 420 may include La.sub.2O.sub.3, Y.sub.2O.sub.3, SrO, LaN, YN, Sr.sub.3N.sub.2, or other suitable materials.
Where the transistor 200D is a p-type transistor, the dipole elements may be aluminum, titanium, niobium, or scandium, or some other chemical elements, and the dipole layer 420 may include an oxide or a nitride of the dipole elements. For example, the dipole layer 420 may include Al.sub.2O.sub.3, TiO.sub.2, niobium oxide (e.g., Nb.sub.2O.sub.5), MN, TiN, NbN, or other suitable materials.
The dipole pattern 420 is for p-type transistor, Paras [0024], [0026], [0031], [0035], [0041], Figures 4D);
driving the p-type dipole material into the first high-k dielectric material (see e.g., A dipole drive-in process is performed so that the dipole materials from the dipole pattern 420 are driven into the gate dielectric layer. The dipole drive-in process is an annealing process, Para [0035], Figures 4D);
removing the p-type dipole material; and (see e.g., dipole pattern 410 is removed by applying etching techniques, Para [0036], Figure 7)
Wu does not explicitly teach
“depositing the second high-k dielectric material after removing the p-type dipole material”.
In a similar field of endeavor Chang teaches
depositing the second high-k dielectric material after removing the p-type dipole material (see e.g., a second high-k material is deposited over the first high-k layer after driving the dipole elements and removing the dipole layer. For transistor 200p, high-k dielectric 284 is deposited over the layer 282p, Figures 8, 9, 14, 15 and 16).
Therefore, it would have been obvious to one skilled in the art at the time the invention was effectively filed to implement Chang’s teachings of depositing a second high-k dielectric material after removing the n-type dipole material in the method of Wu in order to preserve the dipole species incorporated in the first high-k gate dielectric and provide a desired overall gate dielectric thickness.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
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/FAKEHA SEHAR/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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