DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant's response to the Office Final Action filed on 12/31/2025 is acknowledged.
Applicant amended claims 1 and 5.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/31/2025 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 5, 8, and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Zang et al. (US 2018/0308759) (hereafter Zang), in view of You et al. (US 2017/0047326) (hereafter You326).
Regarding claim 1, Zang discloses a semiconductor device, comprising:
a first fin (first 104 from the right corner of Fig. 8A, paragraph 0073), a second fin (second 104 from the right corner of Fig. 8A, paragraph 0073), and a third fin (third 104 from the right corner of Fig. 8A, paragraph 0073) rising from a substrate 102 (Fig. 8A, paragraph 0044) and extending lengthwise along a first direction (stacking direction in Fig. 8A);
a first gate structure 142A (Fig. 8A, paragraph 0071) wrapping over channel regions (first and second 104 from the left corner of Fig. 8A) of the first fin (first 104 from the right corner of Fig. 8A) and the second fin (second 104 from the right corner of Fig. 8A) and extending along a second direction (horizontal direction in Fig. 8A) perpendicular to the first direction (stacking direction in Fig. 8A); and
a second gate structure 142B (Fig. 8A, paragraph 0071) wrapping over a channel region (third 104 from the right corner of Fig. 8A) of the third fin (third 104 from the right corner of Fig. 8A).
Zang does not disclose the first fin bends away from the second fin along the second direction and the second fin bends away from the first fin along the second direction,
wherein the second fin and the third fin bend toward one another along the second direction.
You326 discloses the first fin 310 (Fig. 20a, paragraph 0219) bends away from the second fin 320 (Fig. 20a, paragraph 0219) along the second direction (horizontal direction in Fig. 20a; and see paragraph 0071, wherein “FIG. 20a is a cross-sectional view taken along the line D-D of FIG. 19”) and the second fin 320 (Fig. 20a) bends away from the first fin 310 (Fig. 20a) along the second direction (horizontal direction in Fig. 20a),
wherein the second fin 320 (Fig. 20a) and the third fin 330 (Fig. 20a, paragraph 0219) bend toward one another along the second direction (horizontal direction in Fig. 20a).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Zang to form the first fin bends away from the second fin along the second direction and the second fin bends away from the first fin along the second direction, wherein the second fin and the third fin bend toward one another along the second direction, as taught by You326, since a semiconductor device (You326, paragraph 0007) whose performance can be improved by increasing a width effect through the adjustment of the channel shape of a fin-shaped field effect transistor (FinFET).
Regarding claim 2, Zang further discloses the semiconductor device of claim 1, further comprising: a first isolation feature (first 108 from the right corner of Fig. 8A, paragraph 0046) adjacent to the first fin (first 104 from the right corner of Fig. 8A) and away from the second fin (second 104 from the right corner of Fig. 8A); a second isolation feature (second 108 from the right corner of Fig. 8A, paragraph 0046) disposed between the first fin (first 104 from the right corner of Fig. 8A) and the second fin (second 104 from the right corner of Fig. 8A); and a third isolation feature 156 (Fig. 8A, paragraph 0051) disposed between the second fin (second 104 from the right corner of Fig. 8A) and the third fin (third 104 from the right corner of Fig. 8A).
Zang does not disclose a top surface of the second isolation feature is lower than top surfaces of the first isolation feature and the third isolation feature.
You326 discloses a top surface (topmost surface of second 105 from the left corner of Fig. 20a) of the second isolation feature (second 105 from the left corner of Fig. 20a) is lower than top surfaces (bottommost surfaces of third 105 and first 105 from the left corner of Fig. 20a) of the first isolation feature (third 105 from the left corner of Fig. 20a) and the third isolation feature (first 105 from the left corner of Fig. 20a).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Zang to form a top surface of the second isolation feature is lower than top surfaces of the first isolation feature and the third isolation feature, as taught by You326, since a shallow trench isolation (STI) structure (You326, paragraph 0091) which has superior device isolation properties and is advantageous for high-density integration because it occupies a small area. In addition, since a change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955).
Regarding claim 5, Zang further discloses the semiconductor device of claim 2, further comprising: the first gate structure 142A (Fig. 8A) is insulated from the second gate structure 142B (Fig. 8A) along the second direction (horizontal direction in Fig. 8A) by a gate cut feature 118 (Fig. 8A, paragraph 0052).
Regarding claim 8, Zang further discloses the semiconductor device of claim 1, wherein the first fin (first 104 from the right corner of Fig. 8A) and the second fin (second 104 from the right corner of Fig. 8A) comprise at least one double-fin device.
Regarding claim 21, Zang further discloses the semiconductor device of claim 5, wherein the gate cut feature 118 (Fig. 8A) is disposed on the second isolation feature 108 (Fig. 8A, paragraph 0046).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Zang in view of You326 as applied to claim 2 above, and further in view of Guler et al. (US 2019/0287966) (hereafter Guler).
Regarding claim 3, Zang in view of You326 discloses the semiconductor device of claim 2, however Zang and You326 do not disclose a width of the first isolation feature along the second direction is greater than a width of the second isolation feature along the second direction.
Guler discloses a width of the first isolation feature (third 108 from the left corner of Fig. 3, paragraph 0022) along the second direction (horizontal direction in Fig. 3) is greater than a width of the second isolation feature (fourth 108 from the left corner of Fig. 3, paragraph 0022) along the second direction (horizontal direction in Fig. 3).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Zang in view of You326 to form a width of the first isolation feature along the second direction is greater than a width of the second isolation feature along the second direction, as taught by Guler, since a change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955). Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Zang in view of You326 as applied to claim 2 above, and further in view of Wang et al. (US 2019/0348422) (hereafter Wang).
Regarding claim 6, Zang in view of You326 discloses the semiconductor device of claim 2, however Zang and You326 do not disclose the top surface of the second isolation feature is lower than top surfaces of the first isolation feature and the third isolation feature by a difference between about 3 nm and about 5 nm.
Wang discloses the top surface of the second isolation feature (second 250 from the right corner of Fig. 12, paragraph 0095) is lower than top surfaces of the first isolation feature (first 250 from the right corner of Fig. 12, paragraph 0095) and the third isolation feature (third 250 from the right corner of Fig. 12, paragraph 0095) by a difference (see paragraph 0095, wherein “about 1 nm to about 5 nm”) between about 3 nm and about 5 nm.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Zang in view of You326 to form the top surface of the second isolation feature is lower than top surfaces of the first isolation feature and the third isolation feature by a difference between about 3 nm and about 5 nm, as taught by Wang, since a change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955). In addition, in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Claims 7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Zang in view of You326 as applied to claim 1 above, and further in view of Kim et al. (US 2018/0190821) (hereafter Kim).
Regarding claim 7, Zang in view of You326 discloses the semiconductor device of claim 1, however Zang and You326 do not disclose the first fin and the second fin comprise germanium.
Kim discloses the first fin (F1 in Fig. 14, paragraph 0044) and the second fin (F2 in Fig. 14, paragraph 0044) comprise germanium (“germanium” in paragraph 0044).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Zang in view of You326 to form the first fin and the second fin comprise germanium, as taught by Kim, since applicant has not disclosed that the claimed material is for a particular unobvious purpose, produces an unexpected result, or is otherwise critical, which are criteria that have been held to be necessary for material limitations to be prima facie unobvious. The claimed material is considered to be a "preferred" or "optimum" material out of a plurality of well known materials that a person of ordinary skill in the art at the time the invention was made would have found obvious to provide to the invention of the cited prior art reference, using routine experimentation and optimization of the invention. In re Leshin, 125 USPQ 416 (CCPA 1960).
Regarding claim 9, Zang in view of You326 discloses the semiconductor device of claim 1, however Zang and You326 do not disclose a first source/drain feature over a source/drain region of the first fin; and a second source/drain feature over a source/drain of the second fin, wherein the first source/drain feature and the second source/drain feature bend away from one another along the second direction.
Kim discloses a first source/drain feature (left 115 in Fig. 14, paragraph 0170) over a source/drain region of the first fin (F1 in Fig. 14, paragraph 017); and a second source/drain feature (right 115 in Fig. 14, paragraph 0170) over a source/drain of the second fin (F2 in Fig. 14, paragraph 017), wherein the first source/drain feature (left 115 in Fig. 14) and the second source/drain feature (right 115 in Fig. 14) bend away from one another along the second direction (horizontal direction in Fig. 14).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Zang in view of You326 to form a first source/drain feature over a source/drain region of the first fin; and a second source/drain feature over a source/drain of the second fin, wherein the first source/drain feature and the second source/drain feature bend away from one another along the second direction, as taught by Kim, since a larger gap C1 (Kim, Fig. 14, paragraph 0171) may be ensured among the contacts 195 (Kim, Fig. 14, paragraph 0171) formed on the respective source/drains 115 (Kim, Fig. 14, paragraph 0171) such that an electrical short (Kim, paragraph 0171) among the plurality of contacts 195 (Kim, Fig. 14, paragraph 0171) can be prevented and reliability of the semiconductor device can be increased.
Claims 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Ching et al. (US 2019/0035912) (hereafter Ching), in view of You et al. (US 2017/0047326) (hereafter You326).
Regarding claim 10, Ching discloses a semiconductor structure, comprising:
a substrate 100 (Fig. 14A, paragraph 0017) comprising a first area (upper right portion of 100 in Fig. 14A) and a second area (lower left portion of 100 in Fig. 14A);
a first pair (second and third 100A from the left corner of Fig. 14A) of fins 100A (Fig. 14A, paragraph 0037) and a second pair (fourth and fifth 100A from the left corner of Fig. 14A) of fins over the first area (upper right portion of 100 in Fig. 14A); and
a third pair (sixth and seventh 100A from the left corner of Fig. 14A) of fins and a fourth pair (eighth and ninth 100A from the left corner of Fig. 14A) of fins over the second area (lower left portion of 100 in Fig. 14A),
wherein the first pair (second and third 100A from the left corner of Fig. 14A) of fins and the second pair (fourth and fifth 100A from the left corner of Fig. 14A) of fins rise straight from the first area of the substrate 100 (Fig. 14A).
Ching does not explicitly disclose a pitch of the first pair of fins and the second pair of fins is the same as a pitch of the third pair of fins and the fourth pair of fins.
Regarding the limitation, “a pitch of the first pair of fins and the second pair of fins is the same as a pitch of the third pair of fins and the fourth pair of fins”, Ching discloses a first pair (second and third 100A from the left corner of Fig. 14A) of fins 100A (Fig. 14A, paragraph 0037) and a second pair (fourth and fifth 100A from the left corner of Fig. 14A) of fins over the first area (upper right portion of 100 in Fig. 14A); and a third pair (sixth and seventh 100A from the left corner of Fig. 14A) of fins and a fourth pair (eighth and ninth 100A from the left corner of Fig. 14A) of fins over the second area (lower left portion of 100 in Fig. 14A). In addition, Paragraph 0022 of Ching discloses the pitch between the fin-shaped features 140A (along the Y-axis) may or may not be the same. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Ching to include a pitch of the first pair of fins and the second pair of fins is the same as a pitch of the third pair of fins and the fourth pair of fins, since a person of ordinary skill has good reason to pursue the known options within his or her technical grasp, in the instant case choosing a pitch of the first pair of fins and the second pair of fins being the same as a pitch of the third pair of fins and the fourth pair of fins from the structures listed in paragraph 0022 of Ching (e.g. pitches between fins may be the same or may not be the same); if this leads to the anticipated success, in the instant case providing fins for FinFETs, it is likely the product not of innovation but of ordinary skill. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007).
Ching does not disclose fins in the third pair of fins bend away from each other, and
wherein fins in the fourth pair of fins bend away from each other.
You326 discloses fins (310-340 in Fig. 20a, paragraph 0219) in the third pair (310 and 320 in Fig. 20a, paragraph 0219) of fins bend away from each other, and
wherein fins in the fourth pair (330 and 340 in Fig. 20a, paragraph 0219) of fins bend away from each other.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Ching to form fins in the third pair of fins bend away from each other, and wherein fins in the fourth pair of fins bend away from each other, as taught by You326, since a semiconductor device (You326, paragraph 0007) whose performance can be improved by increasing a width effect through the adjustment of the channel shape of a fin-shaped field effect transistor (FinFET).
Regarding claim 11, Ching in view of You326 discloses the semiconductor structure of claim 10, however Ching does not disclose an isolation feature disposed over the substrate, wherein portions of the isolation feature disposed between the third pair of fins or between the fourth pair of fins is thinner than a portion of the isolation feature between the third pair of fins and the fourth pair of fins.
You326 discloses an isolation feature 105 (Fig. 20a, paragraph 0090) disposed over the substrate 100 (Fig. 20a, paragraph 0090), wherein portions (portions of 105 between 310 and 320 in Fig. 20a) of the isolation feature 105 (Fig. 20a) disposed between the third pair (310 and 320 in Fig. 20a, paragraph 0219) of fins (310-340 in Fig. 20a, paragraph 0219) or between the fourth pair of fins is thinner than a portion (portions of 105 between 320 and 330 in Fig. 20a) of the isolation feature 105 (Fig. 20a) between the third pair (310 and 320 in Fig. 20a) of fins and the fourth pair (330 and 340 in Fig. 20a) of fins.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Ching to form an isolation feature disposed over the substrate, wherein portions of the isolation feature disposed between the third pair of fins or between the fourth pair of fins is thinner than a portion of the isolation feature between the third pair of fins and the fourth pair of fins, as taught by You326, since a change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955). Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Claims 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Ching in view of You326 as applied to claim 10 above, and further in view of You et al. (US 2017/0221771) (hereafter You771).
Regarding claim 12, Ching in view of You326 discloses the semiconductor structure of claim 10, however Ching and You326 do not disclose a first gate structure wrapping over the first pair of fins; a second gate structure wrapping over the second pair of fins; a third gate structure wrapping over the third pair of fins; and a fourth gate structure wrapping over the fourth pair of fins.
You771 discloses a first gate structure (421 of 420A in Fig. 30, paragraph 0096) wrapping (see Fig. 31) over the first pair (F1 and F2 of 420A in Fig. 30, paragraph 0096) of fins (F1-F4 in Fig. 30, paragraph 0096); a second gate structure (421 of 420C in Fig. 30, paragraph 0096) wrapping (see Fig. 31) over the second pair (F3 and F4 of 420C in Fig. 30, paragraph 0096) of fins; a third gate structure (423 of 420B in Fig. 30, paragraph 0096) wrapping over the third pair (F1 and F2 of 420B in Fig. 30, paragraph 0096) of fins; and a fourth gate structure (423 of 420D in Fig. 30, paragraph 0096) wrapping over the fourth pair (F3 and F4 of 420D in Fig. 30, paragraph 0096) of fins.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Ching in view of You326 to form a first gate structure wrapping over the first pair of fins; a second gate structure wrapping over the second pair of fins; a third gate structure wrapping over the third pair of fins; and a fourth gate structure wrapping over the fourth pair of fins, as taught by You771, since the fourth trench R4 (You771, Fig. 30, paragraph 0099) and the fifth trench R5 (You771, Fig. 30, paragraph 0099) may separate a first region 420A (You771, Fig. 30, paragraph 0099) to a fourth region 420D (You771, Fig. 30, paragraph 0099) from each other to short-circuit the device.
Regarding claim 13, Ching in view of You326 and You771 discloses the semiconductor structure of claim 12, however Ching and You326 do not disclose the first gate structure is spaced apart from the second gate structure by a first gate cut feature,
wherein the third gate structure is spaced apart from the fourth gate structure by a second gate cut feature.
You771 discloses the first gate structure (421 of 420A in Fig. 30, paragraph 0096) is spaced apart from the second gate structure (421 of 420C in Fig. 30, paragraph 0096) by a first gate cut feature (upper portion of R4, paragraph 0097),
wherein the third gate structure (423 of 420B in Fig. 30, paragraph 0096) is spaced apart from the fourth gate structure (423 of 420D in Fig. 30, paragraph 0096) by a second gate cut feature (lower portion of R4, paragraph 0097).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Ching in view of You326 to form the first gate structure is spaced apart from the second gate structure by a first gate cut feature, wherein the third gate structure is spaced apart from the fourth gate structure by a second gate cut feature, as taught by You771, since the fourth trench R4 (You771, Fig. 30, paragraph 0099) and the fifth trench R5 (You771, Fig. 30, paragraph 0099) may separate a first region 420A (You771, Fig. 30, paragraph 0099) to a fourth region 420D (You771, Fig. 30, paragraph 0099) from each other to short-circuit the device.
Regarding claim 14, Ching in view of You326 discloses the semiconductor structure of claim 10, however Ching and You326 do not disclose the first pair of fins comprise a first double-fin device, wherein the third pair of fins comprise a second double-fin device.
You771 discloses the first pair (F1 and F2 of 420A in Fig. 30, paragraph 0096) of fins (F1-F4 in Fig. 30, paragraph 0096) comprise a first double-fin device (“transistors” (paragraph 0130) in 420A (Fig. 30)), wherein the third pair (F1 and F2 of 420B in Fig. 30, paragraph 0096) of fins comprise a second double-fin device (“transistors” (paragraph 0130) in 420B (Fig. 30)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Ching in view of You326 to form the first pair of fins comprise a first double-fin device, wherein the third pair of fins comprise a second double-fin device, as taught by You771, since the fourth trench R4 (You771, Fig. 30, paragraph 0099) and the fifth trench R5 (You771, Fig. 30, paragraph 0099) may separate a first region 420A (You771, Fig. 30, paragraph 0099) to a fourth region 420D (You771, Fig. 30, paragraph 0099) from each other to short-circuit the device.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Ching in view of You326 and You771 as applied to claim 14 above, and further in view of Chiang et al. (US 2018/0102278) (hereafter Chiang).
Regarding claim 15, Ching in view of You326 and You771 discloses the semiconductor structure of claim 14, however Ching, You326, and You771 do not disclose the first double-fin device comprises a first threshold voltage,
wherein the second double-fin device comprise a second threshold voltage different from the first threshold voltage.
Chiang discloses the first double-fin device (FinFET with 210a in Fig. 10B, paragraph 0029) comprises a first threshold voltage,
wherein the second double-fin device (FinFET with 210b in Fig. 10B, paragraph 0029) comprise a second threshold voltage different (see paragraph 0029, wherein “The resulting FinFETs including the second fin structures 210b may have a lower threshold voltage and a larger driving current, as compared to the FinFETs including the first fin structures 210a”) from the first threshold voltage.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Ching in view of You326 and You771 to form the first double-fin device comprises a first threshold voltage, wherein the second double-fin device comprise a second threshold voltage different from the first threshold voltage, as taught by Chiang, since FinFETs (Chiang, paragraph 0037) in each specific region can have a desired threshold voltage and driving current by tuning the fin heights such that device performance is improved (Chiang, paragraph 0037).
Claims 16, 18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2018/0190821) (hereafter Kim).
Regarding claim 16, Kim discloses a semiconductor device, comprising:
a first fin (F1 in Figs. 12 and 14, paragraph 0158) and a second fin (F2 in Figs. 12 and 14, paragraph 0158) rising from a substrate 100 (Fig. 14, paragraph 0040) and extending lengthwise along a first direction (horizontal direction in Fig. 12);
a gate structure 202 (Figs. 12 and 13, paragraph 0151) wrapping (see Fig. 13, wherein 202 is wrapping over F1 and F2) over channel regions (F1 and F2 in Fig. 13) of the first fin (F1 in Fig. 13) and the second fin (F2 in Fig. 13) and extending along a second direction (vertical direction in Fig. 12) perpendicular to the first direction (horizontal direction in Fig. 12);
a first source/drain feature (left 115 in Fig. 14, paragraph 0170) over a source/drain region of the first fin (F1 in Fig. 14); and
a second source/drain feature (right 115 in Fig. 14, paragraph 0170) over a source/drain of the second fin (F2 in Fig. 14),
wherein the first fin (F1 in Fig. 14) bends away from the second fin (F2 in Fig. 14) along the second direction (horizontal direction in Fig. 14) and the second fin (F2 in Fig. 14) bends away from the first fin (F1 in Fig. 14) for a first bending amount along the second direction (horizontal direction in Fig. 14),
wherein the first source/drain feature (left 115 in Fig. 14) and the second source/drain feature (right 115 in Fig. 14) bend away from one another for a second bending amount along the second direction (horizontal direction in Fig. 14).
Kim does not explicitly disclose the second bending amount is greater than the first bending amount.
Regarding the limitation, “the second bending amount is greater than the first bending amount”, paragraph 0030 of the specification filed on 7/28/2023 discloses “Because the source/drain features 224 may be formed taller than the fins 204, the second bending amount B2 may be equal to or greater than the first bending amount B1.” Kim discloses the first source/drain feature (left 115 in Fig. 14) and the second source/drain feature (right 115 in Fig. 14) are formed taller than the bended fins (F1 and F2 in Fig. 14). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kim to form the second bending amount is greater than the first bending amount, since, in the light of the specification of claimed invention, a person of ordinary skill in the art would reasonably understood that the first source/drain feature (Kim, left 115 in Fig. 14) and the second source/drain feature (Kim, right 115 in Fig. 14) being taller than the bended fins (Kim, F1 and F2 in Fig. 14) could produce a second bending amount greater than a first bending amount.
Regarding claim 18, Kim further discloses the semiconductor device of claim 16, further comprising: a first isolation feature (first 120 from the left corner of Fig. 14, paragraph 0052) adjacent to the first fin (F1 in Fig. 14) and away from the second fin (F2 in Fig. 14); a second isolation feature (second 120a from the left corner of Fig. 14, paragraph 0070) disposed between the first fin (F1 in Fig. 14) and the second fin (F2 in Fig. 14); and a third isolation feature (third 120 from the left corner of Fig. 14, paragraph 0052) adjacent to the second fin (F2 in Fig. 14) and away from the first fin (F1 in Fig. 14), wherein a top surface of the second isolation feature (second 120a from the left corner of Fig. 14) is lower than top surfaces of the first isolation feature (first 120 from the left corner of Fig. 14) and the third isolation feature (third 120 from the left corner of Fig. 14).
Regarding claim 20, Kim further discloses the semiconductor device of claim 17, wherein the first fin (F1 in Fig. 14; and see paragraph 0040, wherein “silicon germanium”) and the second fin comprise germanium.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Kim as applied to claim 16 above, and further in view of Tsai et al. (US 2015/0004772) (hereafter Tsai).
Regarding claim 17, Kim discloses the semiconductor device of claim 16, however Kim does not disclose the first bending amount is between about 0.3 nm and about 1.5 nm, wherein the second bending amount is between about 0.3 nm and about 3.0 nm.
Tsai discloses the first bending amount (see paragraph 0039, wherein “about three nanometers (3 nm)”) is between about 0.3 nm and about 1.5 nm.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kim to form the first bending amount is between about 0.3 nm and about 1.5 nm, as taught by Tsai, since a change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955). In addition, since a prima facie case of obviousness exists where the claimed ranges and prior art ranges do not overlap but are close enough that one skilled in the art would have expected them to have the same properties. Titanium Metals Corp. v. Banner, 778 F.2d 775, 227 USPQ 773 (Fed. Cir. 1985). Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Kim and Tsai do not explicitly disclose the second bending amount is between about 0.3 nm and about 3.0 nm.
Regarding the limitation, “the second bending amount is between about 0.3 nm and about 3.0 nm”, paragraph 0030 of the specification filed on 7/28/2023 discloses “Because the source/drain features 224 may be formed taller than the fins 204, the second bending amount B2 may be equal to or greater than the first bending amount B1.” Kim discloses the first source/drain feature (left 115 in Fig. 14) and the second source/drain feature (right 115 in Fig. 14) are formed taller than the bended fins (F1 and F2 in Fig. 14). In addition, Tsai discloses the first bending amount (see paragraph 0039) is about 3 nm. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kim in view of Tsai to form the second bending amount is between about 0.3 nm and about 3.0 nm, since, in the light of the specification of claimed invention, a person of ordinary skill in the art would reasonably understood that the first source/drain feature (Kim, left 115 in Fig. 14) and the second source/drain feature (Kim, right 115 in Fig. 14) being taller than the bended fins (Kim, F1 and F2 in Fig. 14) could produce the second bending amount is between about 0.3 nm and about 3.0 nm.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Kim as applied to claim 18 above, and further in view of You et al. (US 2017/0047326) (hereafter You326).
Regarding claim 19, Kim discloses the semiconductor device of claim 18, however Kim does not disclose a third fin spaced apart from the first fin by the first isolation feature, wherein a width of the first isolation feature along the second direction is greater than a width of the second isolation feature along the second direction.
You326 discloses a third fin 320 (Fig. 20a, paragraph 0219) spaced apart from the first fin 330 (Fig. 20a, paragraph 0219) by the first isolation feature (105 between 320 and 330 in Fig. 20a, paragraph 0224), wherein a width of the first isolation feature (105 between 320 and 330 in Fig. 20a, paragraph 0224) along the second direction (horizontal direction in Fig. 20a) is greater than a width of the second isolation feature (105 between 330 and 340 in Fig. 20a, paragraph 0224) along the second direction (horizontal direction in Fig. 20a).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Kim to form a third fin spaced apart from the first fin by the first isolation feature, wherein a width of the first isolation feature along the second direction is greater than a width of the second isolation feature along the second direction, as taught by You326, since a change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955). Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Response to Arguments
1. Applicant's arguments filed 12/31/2025 have been fully considered.
Applicant's arguments with respect to claims 1-3 and 5-21 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
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/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813