DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant's response to the Office Non-Final Action filed on 12/31/2025 is acknowledged.
Applicant amended claims 1-3 and 8.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 2 are rejected under 35 U.S.C. 103 as being unpatentable over Ching et al. (US 2019/0035912) (hereafter Ching), in view of Liao et al. (US 2021/0091075) (hereafter Liao).
Regarding claim 1, Ching discloses a semiconductor structure, comprising:
a substrate 100 (Fig. 15A, paragraph 0017);
a fin structure 100A (Fig. 15A, paragraph 0036) over the substrate 100 (Fig. 15A);
an isolation structure 220A (Fig. 15A, paragraph 0058) over the substrate 100 (Fig. 15A) and adjacent the fin structure 100A (Fig. 15A);
two source/drain (S/D) features 280 (Fig. 15A, paragraph 0075) over the fin structure 100A (Fig. 15A);
one or more channel semiconductor layers (not shown in Fig. 15A but see portions of 100A covered by 240 in Fig. 11A) laterally connecting the two S/D features 280 (Fig. 15A);
a high-k metal gate (310 and 320 in Figs. 15A and 16, paragraph 0089) between the two S/D features 280 (Fig. 15A) and engaging the one or more channel semiconductor layers (portions of 100A covered by 320 in Fig. 16).
Ching does not disclose a dielectric structure over the isolation structure and adjacent to the two S/D features and the high-k metal gate, wherein a first portion of the dielectric structure adjacent to the high-k metal gate is narrower than a second portion of the dielectric structure adjacent to the two S/D features,
wherein the high-k metal gate comprises a gate dielectric layer and a gate electrode,
wherein a topmost surface of the dielectric structure is higher than a topmost surface of the gate electrode.
Liao discloses a dielectric structure 820 (Figs. 8A and 8B, paragraph 0074) over the isolation structure 806 (Fig. 8A, paragraph 0072) and adjacent to the two S/D features (804A and 804B in Fig. 8B, paragraph 0080) and the high-k metal gate 808 (Fig. 8A, paragraph 0086), wherein a first portion (lower portion of 820 below 852A in Fig. 8A) in Fig. 8A) of the dielectric structure 820 (Fig. 8A) adjacent to the high-k metal gate 808 (Fig. 8A) is narrower (see Fig. 8A, wherein a vertical length of lower portion of 820 below 852A is less than a vertical length of upper portion of 820 above 852A) than a second portion (upper portion of 820 above 852A in Fig. 8A) of the dielectric structure 820 (Fig. 8A) adjacent to the two S/D features (804A and 804B in Fig. 8B),
wherein the high-k metal gate 808 (Fig. 8A) comprises a gate dielectric layer 852B (Fig. 8A, paragraph 0086) and a gate electrode 850 (Fig. 8A, paragraph 0085),
wherein a topmost surface of the dielectric structure 820 (Fig. 8A) is higher than a topmost surface of the gate electrode 850 (Fig. 8A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Ching to form a dielectric structure over the isolation structure and adjacent to the two S/D features and the high-k metal gate, wherein a first portion of the dielectric structure adjacent to the high-k metal gate is narrower than a second portion of the dielectric structure adjacent to the two S/D features, wherein the high-k metal gate comprises a gate dielectric layer and a gate electrode, wherein a topmost surface of the dielectric structure is higher than a topmost surface of the gate electrode, as taught by Liao, since the gate structures 808 (Liao, Fig. 8B, paragraph 0079) are shown as over the protruding fin portions 804 (Liao, Fig. 8B, paragraph 0079), as isolated by self-aligned gate endcap isolation structures 820 (Liao, Fig. 8B, paragraph 0079).
Regarding claim 2, Ching discloses the semiconductor structure of claim 1, however Ching does not explicitly disclose the first portion of the dielectric structure is narrower than the second portion of the dielectric structure by about 2 nm to about 12 nm.
Regarding the limitation, “the first portion of the dielectric structure is narrower than the second portion of the dielectric structure by about 2 nm to about 12 nm”, Ching discloses the second portion (upper portion of 210A in Fig. 7C) of the dielectric structure 210a (Fig. 7C) is in a range (see paragraph 0052) from about 8 nm to about 12 nm and the first portion (lower portion of 210A in Fig. 7C) of the dielectric fin 210a (Fig. 17) is near 0 nm (see Fig. 7C). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Ching to form the first portion of the dielectric structure is narrower than the second portion of the dielectric structure by about 2 nm to about 12 nm, since a change in size is generally recognized as being within the level of ordinary skill in the art In re Rose, 105 USPQ 237 (CCPA 1955). In addition, in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990). Note that the specification contains no disclosure of either the critical nature of the claimed ranges or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 f.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
Allowable Subject Matter
1. Claims 3-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
2. Claim 3 would be allowable because closest prior art, Liao et al. (US 2021/0091075), discloses a dielectric structure 820 (Figs. 8A and 8B, paragraph 0074) over the isolation structure 806 (Fig. 8A, paragraph 0072) and adjacent to the two S/D features (804A and 804B in Fig. 8B, paragraph 0080) and the high-k metal gate 808 (Fig. 8A, paragraph 0086), wherein a first portion (lower portion of 820 below 852A in Fig. 8A) in Fig. 8A) of the dielectric structure 820 (Fig. 8A) adjacent to the high-k metal gate 808 (Fig. 8A) is narrower than a second portion (upper portion of 820 above 852A in Fig. 8A) of the dielectric structure 820 (Fig. 8A) adjacent to the two S/D features (804A and 804B in Fig. 8B), wherein the high-k metal gate 808 (Fig. 8A) comprises a gate dielectric layer 852B (Fig. 8A, paragraph 0086) and a gate electrode 850 (Fig. 8A, paragraph 0085), wherein a topmost surface of the dielectric structure 820 (Fig. 8A) is higher than a topmost surface of the gate electrode 850 (Fig. 8A) but fails to disclose the first portion of the dielectric structure comprises a dielectric liner disposed on and in contact with the isolation structure, a low-k dielectric layer over the dielectric liner, and a high-k helmet layer over the low-k dielectric layer. Additionally, the prior art of record neither anticipates nor renders obvious the limitations of the claim that recites a semiconductor structure, comprising: the first portion of the dielectric structure comprises a dielectric liner disposed on and in contact with the isolation structure, a low-k dielectric layer over the dielectric liner, and a high-k helmet layer over the low-k dielectric layer in combination with other elements of the base claim 1. The other claims each depend from one of these claims, and each would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims for the same reasons as the claim from which it depends. Claims 4-8 depend on claim 3.
Claims 9-20 are allowed. The following is an examiner’s statement of reasons for allowance: a closest prior art, Ching et al. (US 2020/0243666), discloses a first dielectric fin (second 118 and first 120 from the left corner of Fig. 8E, paragraph 0036) disposed on the isolation structure 114 (Fig. 8E) and extending between the first plurality of channel layers (106 vertically over the second vertical portion of 102 from the left corner of Fig. 8E) and the second plurality of channel layers (106 vertically over the third vertical portion of 102 from the left corner of Fig. 8E) along a direction (horizontal direction in Fig. 8E); a second dielectric fin (first 118 from the left corner of Fig. 8E, paragraph 0036) disposed on the isolation structure 114 (Fig. 8E) such that the first plurality of channel layers (106 vertically over the second vertical portion of 102 from the left corner of Fig. 8E) are disposed between the first dielectric fin (second 118 and first 120 from the left corner of Fig. 8E) and the second dielectric fin (first 118 from the left corner of Fig. 8E) along the direction (horizontal direction in Fig. 8E); a third dielectric fin (third 118 from the left corner of Fig. 8E, paragraph 0036) disposed on the isolation structure 114 (Fig. 8E) such that the second plurality of channel layers (106 vertically over the third vertical portion of 102 from the left corner of Fig. 8E) are disposed between the first dielectric fin (second 118 and first 120 from the left corner of Fig. 8E) and the third dielectric fin along the direction (third 118 from the left corner of Fig. 8E) but fails to disclose the first dielectric fin comprises a first dielectric liner in contact with a top surface of the isolation structure, a first low-k dielectric layer disposed on the first dielectric liner, and a high-k helmet layer disposed on the first low-k dielectric layer, wherein each of the second dielectric fin and the third dielectric fin comprises a second dielectric liner in contact with the top surface of the isolation structure and a second low-k dielectric layer disposed on the first dielectric liner. Additionally, the prior art does not teach or suggest a semiconductor structure, comprising: the first dielectric fin comprises a first dielectric liner in contact with a top surface of the isolation structure, a first low-k dielectric layer disposed on the first dielectric liner, and a high-k helmet layer disposed on the first low-k dielectric layer, wherein each of the second dielectric fin and the third dielectric fin comprises a second dielectric liner in contact with the top surface of the isolation structure and a second low-k dielectric layer disposed on the first dielectric liner in combination with other elements of claim 9.
In addition, a closest prior art, Ching et al. (US 2020/0243666), discloses a first dielectric fin (second 118 and first 120 from the left corner of Fig. 8E, paragraph 0036) disposed on the isolation structure 114 (Fig. 8E) and extending between the first plurality of channel layers (106 vertically over the second vertical portion of 102 from the left corner of Fig. 8E) and the second plurality of channel layers (106 vertically over the third vertical portion of 102 from the left corner of Fig. 8E) along a direction (horizontal direction in Fig. 8E); and a gate dielectric layer 154 (Fig. 8E, paragraph 0066) wrapping around each of the first plurality of channel layers (106 vertically over the second vertical portion of 102 from the left corner of Fig. 8E) and each of the second plurality of channel layers (106 vertically over the third vertical portion of 102 from the left corner of Fig. 8E) but fails to disclose a gate dielectric layer in contact with top surfaces and sidewalls of the first dielectric fin. Additionally, the prior art does not teach or suggest a semiconductor structure, comprising: a gate dielectric layer in contact with top surfaces and sidewalls of the first dielectric fin in combination with other elements of claim 18.
A closest prior art, Ching et al. (US 2020/0243666), discloses a semiconductor structure, comprising: a first fin (second vertical portion of 102 from the left corner of Fig. 8E) and a second fin (third vertical portion of 102 from the left corner of Fig. 8E) disposed in an isolation structure 114 (Fig. 8E, paragraph 0034); a first plurality of channel layers (106 vertically over the second vertical portion of 102 from the left corner of Fig. 8E) disposed over the first fin (second vertical portion of 102 from the left corner of Fig. 8E); a second plurality of channel layers (106 vertically over the third vertical portion of 102 from the left corner of Fig. 8E) disposed over the second fin (third vertical portion of 102 from the left corner of Fig. 8E); a first dielectric fin (second 118 and first 120 from the left corner of Fig. 8E, paragraph 0036) disposed on the isolation structure 114 (Fig. 8E) and extending between the first plurality of channel layers (106 vertically over the second vertical portion of 102 from the left corner of Fig. 8E) and the second plurality of channel layers (106 vertically over the third vertical portion of 102 from the left corner of Fig. 8E) along a direction (horizontal direction in Fig. 8E); a second dielectric fin (first 118 from the left corner of Fig. 8E, paragraph 0036) disposed on the isolation structure 114 (Fig. 8E) such that the first plurality of channel layers (106 vertically over the second vertical portion of 102 from the left corner of Fig. 8E) are disposed between the first dielectric fin (second 118 and first 120 from the left corner of Fig. 8E) and the second dielectric fin (first 118 from the left corner of Fig. 8E) along the direction (horizontal direction in Fig. 8E); a third dielectric fin (third 118 from the left corner of Fig. 8E, paragraph 0036) disposed on the isolation structure 114 (Fig. 8E) such that the second plurality of channel layers (106 vertically over the third vertical portion of 102 from the left corner of Fig. 8E) are disposed between the first dielectric fin (second 118 and first 120 from the left corner of Fig. 8E) and the third dielectric fin along the direction (third 118 from the left corner of Fig. 8E) but fails to teach the first dielectric fin comprises a first dielectric liner in contact with a top surface of the isolation structure, a first low-k dielectric layer disposed on the first dielectric liner, and a high-k helmet layer disposed on the first low-k dielectric layer, wherein each of the second dielectric fin and the third dielectric fin comprises a second dielectric liner in contact with the top surface of the isolation structure and a second low-k dielectric layer disposed on the first dielectric liner as the context of claim 9. The other allowed claims each depend from one of these claims, and each is allowable for the same reasons as the claim from which it depends. Claims 10-17 depend on claim 9.
In addition, a closest prior art, Ching et al. (US 2020/0243666), discloses a semiconductor structure, comprising: a first fin (second vertical portion of 102 from the left corner of Fig. 8E) and a second fin (third vertical portion of 102 from the left corner of Fig. 8E) disposed in an isolation structure 114 (Fig. 8E, paragraph 0034); a first plurality of channel layers (106 vertically over the second vertical portion of 102 from the left corner of Fig. 8E) disposed over the first fin (second vertical portion of 102 from the left corner of Fig. 8E); a second plurality of channel layers (106 vertically over the third vertical portion of 102 from the left corner of Fig. 8E) disposed over the second fin (third vertical portion of 102 from the left corner of Fig. 8E); a first dielectric fin (second 118 and first 120 from the left corner of Fig. 8E, paragraph 0036) disposed on the isolation structure 114 (Fig. 8E) and extending between the first plurality of channel layers (106 vertically over the second vertical portion of 102 from the left corner of Fig. 8E) and the second plurality of channel layers (106 vertically over the third vertical portion of 102 from the left corner of Fig. 8E) along a direction (horizontal direction in Fig. 8E); a second dielectric fin (first 118 from the left corner of Fig. 8E, paragraph 0036) disposed on the isolation structure 114 (Fig. 8E) such that the first plurality of channel layers (106 vertically over the second vertical portion of 102 from the left corner of Fig. 8E) are disposed between the first dielectric fin (second 118 and first 120 from the left corner of Fig. 8E) and the second dielectric fin (first 118 from the left corner of Fig. 8E) along the direction (horizontal direction in Fig. 8E); a third dielectric fin (third 118 from the left corner of Fig. 8E, paragraph 0036) disposed on the isolation structure 114 (Fig. 8E) such that the second plurality of channel layers (106 vertically over the third vertical portion of 102 from the left corner of Fig. 8E) are disposed between the first dielectric fin (second 118 and first 120 from the left corner of Fig. 8E) and the third dielectric fin along the direction (third 118 from the left corner of Fig. 8E); a gate dielectric layer 154 (Fig. 8E, paragraph 0066) wrapping around each of the first plurality of channel layers (106 vertically over the second vertical portion of 102 from the left corner of Fig. 8E) and each of the second plurality of channel layers (106 vertically over the third vertical portion of 102 from the left corner of Fig. 8E), in contact with top surfaces and sidewalls of the second dielectric fin (first 118 from the left corner of Fig. 8E), and the third dielectric fin (third 118 from the left corner of Fig. 8E); a first gate electrode 160a (Fig. 8E, paragraph 0070) disposed over the gate dielectric layer 154 (Fig. 8E) and wrapping around each of the first plurality of channel layers (106 vertically over the second vertical portion of 102 from the left corner of Fig. 8E); and a second gate electrode 160b (Fig. 8E, paragraph 0070) disposed over the gate dielectric layer 154 (Fig. 8E) and wrapping around each of the second plurality of channel layers (106 vertically over the third vertical portion of 102 from the left corner of Fig. 8E), wherein a top surface of the first dielectric fin (second 118 and first 120 from the left corner of Fig. 8E) rises above top surfaces of the first gate electrode 160a (Fig. 8E) and the second gate electrode 160b (Fig. 8E) but fails to teach a gate dielectric layer in contact with top surfaces and sidewalls of the first dielectric fin as the context of claim 18. The other allowed claims each depend from one of these claims, and each is allowable for the same reasons as the claim from which it depends. Claims 19-20 depend on claim 18.
Response to Arguments
1. Applicant's arguments filed 12/31/2025 have been fully considered.
Applicant's arguments with respect to claims 1 and 2 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAMONT B KOO whose telephone number is (571)272-0984. The examiner can normally be reached 7:00 AM - 3:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
Prosecution Insights