Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention II, which includes original claims 13- 20 and newly added claims 21-32 in the reply filed on 11/20/2025 is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 13, 15-21, 25-27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ching et al. (US 20100224925 A1; hereinafter “Ching”) in view of Park et al. (US 20190019787 A1; hereinafter “Park”).
In re claim 13, Ching discloses in figs. 4-5, a method of forming capacitors in an integrated device, comprising:
forming an interlayer dielectric 140, 144 over a substrate 124 (fig. 5B; ¶15, 16);
depositing a first masking layer 504 over an upper surface of the interlayer dielectric 140, 144 (fig. 5C; ¶28);
patterning the first masking layer 504, resulting in a first opening and a second opening in the first masking layer 504 (fig. 5C; ¶28; in the device region 106, a first opening is formed in the photoresist layer 504 and in the device region 104, a second opening is formed in the photoresist layer 504),
etching the interlayer dielectric 140, 144 using a single etching process 510, resulting in a first trench 512 directly beneath the first opening and a second trench 514 directly beneath the second opening (¶28); and
forming a first capacitor 530 in the first trench 512 and a second capacitor 114 in the second trench 514 (fig. 5E; ¶31),
the first trench 512 having a first depth and the second trench 514 having a second depth less than the first depth (as shown in fig. 5C; a second depth of the second trench 514 is less than a first depth of the first trench 512).
Ching does not expressly disclose the first opening having a first width and the second opening having a second width less than the first width.
In the same field of endeavor, Park discloses a method of forming capacitors in an integrated device (figs. 1-3, 11-12), comprising:
patterning a first masking layer, resulting in a first opening 205b and a second opening 205a in the masking layer (¶126),
the first opening 205b having a first width and the second opening 205a having a second width less than the first width (fig. 12; ¶125-126).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Park into the MIM capacitors of Ching to provide different capacitors with different areas by adjusting both the heights and the widths of the trenches in an integrated circuit capable of implementing capacitance flexibility (¶5, 35, 125-126).
In re claim 15, Ching, as modified by Park, discloses the method of claim 13 outlined above.
Ching further discloses in figs. 4-5, wherein the single etching process etches the first trench and the second trench (fig. 5C; ¶28).
In re claim 16, Ching, as modified by Park, discloses the method of claim 13 outlined above.
Ching further discloses in figs. 4-5, the method further comprising:
forming a third opening having a third width when patterning the first masking layer 504 (Fig. 5C shows forming a third opening when patterning the first masking layer 504 in the first device region 106); and
forming a third trench (trench 512 into which the capacitor portion 530b is formed) during the single etching process, wherein the third trench is directly beneath the third opening in the first masking layer (fig. 5C; ¶28), and
wherein the first capacitor 530 is formed in the third trench (trench 512 into which the capacitor portion 530b is formed) in addition to the first trench (trench 512 into which the capacitor portion 530a is formed).
In re claim 17, Ching, as modified by Park, discloses the method of claim 13 outlined above.
Ching further discloses in figs. 4-5, wherein the first trench 512 extends through one or more etch stop layers 134 within the interlayer dielectric 140, 144, and wherein the second trench 514 does not extend through the one or more etch stop layers 134 within the interlayer dielectric 140, 144 (fig. 5C; ¶24, 28).
In re claim 18, Ching, as modified by Park, discloses the method of claim 13 outlined above.
Ching further discloses in figs. 4-5, the method further comprising:
forming a first plurality of wires 132, 142 within the interlayer dielectric 140, 144 before depositing the first masking layer 504 (fig. 5A; ¶24); and
forming a second plurality of wires after forming the first capacitor 114 and the second capacitor 530 (¶34; “The interconnect structure includes a plurality of metal layers (a first level metal layer 172 is illustrated) and intermetal dielectric for insulating each of the metal layers. Further, the interconnect structure includes vertical connections (vias/contacts) and horizontal connections (lines)”),
where bottom electrodes 312a, 150 of the first capacitor 530 and the second capacitor 114 are coupled to the first plurality of wires 132, 142 (fig. 5E; ¶31).
Regarding claim limitations “top electrodes of the first capacitor and the second capacitor are coupled to the second plurality of wires”: Ching further discloses in figs. 4-5, “The method 400 continues with block 4222 in which an interconnect structure is formed over the third ILD. The semiconductor device 500 includes an interconnect structure formed over the ILD layer 168 for interconnecting the various devices in the regions 102 (not shown), 104, 106 to form an integrated circuit or system-on-chip (SoC) device. The interconnect structure includes a plurality of metal layers (a first level metal layer 172 is illustrated) and intermetal dielectric for insulating each of the metal layers. The interconnect structure includes a plurality of metal layers (a first level metal layer 172 is illustrated) and intermetal dielectric for insulating each of the metal layers. Further, the interconnect structure includes vertical connections (vias/contacts) and horizontal connections (lines)” (¶34).
Therefore, Ching teaches top electrodes 314, 152 of the first capacitor 530 and the second capacitor 114 are coupled to the second plurality of wires (i.e., the plurality of metal layers).
In re claim 19, Ching, as modified by Park, discloses the method of claim 13 outlined above.
Ching further discloses the method further comprising:
forming a first plurality of vias (e.g., vertical connections (vias/contacts)) after forming the first capacitor 530 and the second capacitor 114; and forming a first plurality of wires (e.g., plurality of M1) (see ¶34 of Ching: “The method 400 continues with block 4222 in which an interconnect structure is formed over the third ILD. The semiconductor device 500 includes an interconnect structure formed over the ILD layer 168 for interconnecting the various devices in the regions 102 (not shown), 104, 106 to form an integrated circuit or system-on-chip (SoC) device. The interconnect structure includes a plurality of metal layers (a first level metal layer 172 is illustrated) and intermetal dielectric for insulating each of the metal layers. The interconnect structure includes a plurality of metal layers (a first level metal layer 172 is illustrated) and intermetal dielectric for insulating each of the metal layers. Further, the interconnect structure includes vertical connections (vias/contacts) and horizontal connections (lines)”),
top electrodes of the first capacitor and the second capacitor are coupled to the first plurality of wires by the first plurality of vias (as explained above, based on ¶34, Ching teaches top electrodes 314, 152 of the first capacitor 530 and the second capacitor 114 are coupled to the second plurality of wires by the first plurality of vias (i.e., the plurality of metal layers)).
Ching does not expressly disclose wherein bottom electrodes of the first capacitor and the second capacitor are coupled to the first plurality of wires by the first plurality of vias.
In the same field of endeavor, Park discloses in figs. 1-3 and 11-12, wherein bottom electrodes 121’, 123’ (¶53) of the first capacitor 120a and the second capacitor 120b are coupled to the first plurality of wires M1, M2 by the first plurality of vias 171, 172 (¶57).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Park into the MIM capacitors of Ching to utilize back-end-of-line metallization and connect both electrodes from the front side and simplify electrode connection steps of the MIM capacitors.
In re claim 20, Ching, as modified by Park, discloses the method of claim 13 outlined above.
Ching further discloses in figs. 4-5, wherein forming the first capacitor 530 and the second capacitor 114 further comprises forming a first horizontal portion of the first capacitor 530 (e.g., a first horizontal portion between 530a and 530b) and a second horizontal portion of the second capacitor 114 (e.g., a second horizontal portion at the bottom of the capacitor 114), and
Ching does not expressly disclose wherein the first horizontal portion has a first area and the second horizontal portion has a second area different from the first area.
However, Park teaches wherein a first horizontal portion of the first capacitor formed in the first capacitor region S1 has different area than a second horizontal portion of the second capacitor formed the second capacitor region S2 (¶125-126).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Park into the MIM capacitors of Ching to provide different capacitors with different areas by adjusting both the heights and the widths of the trenches in an integrated circuit capable of implementing capacitance flexibility (¶5, 35, 125-126).
In re claim 21, Ching discloses in figs. 4-5, a method of forming capacitors in an integrated device, comprising:
forming an interlayer dielectric 140, 144 over a substrate 124 (fig. 5B; ¶15, 16);
depositing a first masking layer 504 over a first upper surface (e.g., an upper surface of layer 144. Hereinafter “S1”) of the interlayer dielectric 140, 144 (fig. 5C; ¶28);
patterning the first masking layer 504, resulting in a first opening and a second opening in the first masking layer 504 (fig. 5C; ¶28; in the device region 106, a first opening is formed in the photoresist layer 504 and in the device region 104, a second opening is formed in the photoresist layer 504),
etching the interlayer dielectric 140, 144, resulting in a first trench 512 at the first opening and extending to a first depth (e.g., a depth of the first trench 512, labeling as D1) beneath the first upper surface S1 and a second trench 514 at second opening and extending to a second depth (e.g., a depth of the second trench 514, labeling as D2) beneath the first upper surface S1 (fig. 5C; ¶28);
depositing a first electrode layer 312, 150 conforming to sidewalls of the first trench 512 and the second trench 514 and having a bottom surface at the first depth D1 and the second depth D2 (fig. 5E, ¶31); and
subsequently depositing a dielectric layer 316, 154 and a second electrode layer 314, 152 over the first electrode layer 312, 150, thereby filling the first trench 512 and the second trench 514 (fig. 5E; ¶32).
Ching does not expressly disclose the first opening having a first width and the second opening having a second width less than the first width.
In the same field of endeavor, Park discloses a method of forming capacitors in an integrated device (figs. 1-3, 11-12), comprising:
patterning a first masking layer, resulting in a first opening 205b and a second opening 205a in the masking layer (¶126),
the first opening 205b having a first width and the second opening 205a having a second width less than the first width (fig. 12; ¶125-126).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Park into the MIM capacitors of Ching to provide different capacitors with different areas by adjusting both the heights and the widths of the trenches in an integrated circuit capable of implementing capacitance flexibility (¶5, 35, 125-126).
In re claim 25, Ching, as modified by Park, discloses the method of claim 21 outlined above.
Ching further discloses in figs. 4-5, further comprising removing the first masking layer 504 after the first trench 512 and the second trench 514 are respectively etched to the first depth D1 and to the second depth D2 (figs. 5D-5E; “The photoresist 504 may be employed as a mask during an etching process 510 and subsequently stripped, such as by wet stripping or plasma ashing”; ¶28).
In re claim 26, Ching, as modified by Park, discloses the method of claim 21 outlined above.
Ching further discloses in figs. 4-5, the method 400 continues with block 408 in which an etching process is performed that stops at least at the conductive layer in the first region thereby forming a first trench and that stops at the etch stop layer in the second region thereby forming a second trench (¶28). Therefore, Ching discloses wherein material removed from the interlayer dielectric 140, 144 to form the first trench 512 is etched at a first etch rate and material removed from the interlayer dielectric 140, 144 to form the second trench 514 is etched at a second etch rate during the etching of the interlayer dielectric (note, claim 26 in its current form does not claim that first and second etch rates are different and hence, does not distinguish over the prior art).
In re claim 27, Ching, as modified by Park, discloses the method of claim 21 outlined above.
Ching further discloses in figs. 4-5, wherein after the etching of the interlayer dielectric, the interlayer dielectric 140, 144 has a second upper surface within the first trench 512 at the first depth D1 beneath the first upper surface S1 and a third upper surface within the second trench 514 at the second depth D2 beneath the first upper surface S1 (fig. 5C shows the second upper surface within the first trench 512 and a third upper surface within the second trench 514).
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ching in view of Park, as applied to claim 13 above and further in view of Kim et al. (US 20040232557 A1; hereinafter “Kim”) and Yang et al. (US 6127070 A; hereinafter “Yang”).
In re claim 14, Ching, as modified by Park, discloses the method of claim 13 outlined above.
Ching discloses the first masking layer is formed by using a photoresist layer for patterning the underlying layers.
However, Ching, as modified by Park, does not expressly disclose depositing a hard mask over the interlayer dielectric; and patterning the hard mask, resulting in a first opening and a second opening in the hard mask, the first opening of the hard mask having the first width and the second opening of the hard mask having the second width.
In the same field of endeavor, Kim discloses in figs. 1A-1F, a method of forming capacitors in an integrated device, comprising:
depositing a hard mask 18 over an interlayer dielectric (12-17) (hereinafter “ILD”) (fig. 1A; ¶38); and
patterning the hard mask 18, resulting in a first opening and a second opening in the hard mask 18 (fig. 1B; Among the plurality of trenches shown in fig. 1B, the leftmost trench has been interpreted as a first opening and the middle trench 19 has been interpreted as a second opening. Hereinafter “OPN1” and “OPN2”, respectively).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Kim into the MIM capacitors of Ching/Park.
One would have been motivated to employ a combination of a hard mask layer and a photoresist layer as a masking layer for patterning underlying layers as Yang teaches that this would enable using an ultra-thin photoresist layer, improved critical dimension control is realized (see Yang: Col. 7, 2nd and 3rd paragraphs).
The combined teachings of Ching, as modified by Park, Kim and Yang disclose the first opening of the hard mask having the first width and the second opening of the hard mask having the second width.
Claim(s) 22-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ching in view of Park, as applied to claim 21 above and further in view of Lei et al. (CN 102569250 A; hereinafter “Lei”).
In re claim 22, Ching, as modified by Park, discloses the method of claim 21 outlined above.
Ching does not expressly disclose etching the second electrode layer and the dielectric layer, resulting in a first top electrode and a first dielectric overlying the first electrode layer and having first sidewalls facing a first direction and overlying the first electrode layer; and
etching the first electrode layer, resulting in a first bottom electrode extending past the first sidewalls of the first top electrode and the first dielectric in the first direction.
Park discloses in figs. 1-3, 11-12,
forming the second electrode layer and the dielectric layer, as a first top electrode 123 and a first dielectric 111 overlying the first electrode layer 122 and having first sidewalls facing a first direction X and overlying the first electrode layer 122 (fig. 2; ¶37-39); and
forming the first electrode layer, as a first bottom electrode 122 extending past the first sidewalls of the first top electrode 123 and the first dielectric 111 in the first direction X (fig. 2).
However, Park does not expressly disclose forming the top electrode, the first dielectric and the bottom electrode from etching the second electrode layer, the dielectric layer and the first electrode layer. In other words, Park does not show the etching steps for patterning the top and bottom electrode layers and the dielectric layer.
In the same field of endeavor, Lei discloses in figs. 1-4, a method of forming capacitors in an integrated device, comprising:
forming the top electrode, the first dielectric and the bottom electrode from etching the conformally formed second electrode layer 10, the dielectric layer 3 and the first electrode layer 11 (see figs. 2-3).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of the electrode leading-out method of Lei into the MIM capacitors of Ching/Park to have a high-density capacitor with high precision and high reliability (see abstract of Lei).
In re claim 23, Ching, as modified by Park and Lei, discloses the method of claim 22 outlined above.
Ching further discloses in figs. 4-5, the method further comprising: forming a first wire level (e.g., a plurality of metal layers (a first level metal layer 172 is illustrated)) over the first top electrode 314 and the first bottom electrode 312, wherein the first wire level comprises a first wire electrically coupled to the first top electrode (see ¶34 of Ching).
Ching does not expressly disclose a second wire spaced from the first wire and the first top electrode in the first direction and electrically coupled to the first bottom electrode.
In the same field of endeavor, Park discloses in figs. 1-3, 11-12, the method further comprising:
a second wire (wire M1 electrically connected to electrode layer 122 in fig. 2) spaced from a first wire (wire M1 electrically connected to electrode layer 123 in fig. 2) and the first top electrode 123 in the first direction X and electrically coupled to the first bottom electrode 122 (fig. 2; ¶57).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Park into the MIM capacitors of Ching/Lei to utilize back-end-of-line metallization and connect both electrodes from the front side and simplify electrode connection steps of the MIM capacitors.
In re claim 24, Ching, as modified by Park, discloses the method of claim 21 outlined above.
Ching does not expressly disclose the method further comprising: etching the second electrode layer, the dielectric layer, and the first electrode layer, resulting in a first top electrode and a second top electrode respectively extending over a first bottom electrode and a second bottom electrode, wherein the first top electrode is spaced from the second top electrode by a first distance and the first bottom electrode is spaced from the second top electrode by a second distance that is less than the first distance.
In the same field of endeavor, Park discloses in figs. 1-3, 11-12, the method comprising:
forming from the second electrode layer, the dielectric layer, and the first electrode layer, a first top electrode (123 in first capacitor region S1) and a second top electrode (123 in second capacitor region S2) respectively extending over a first bottom electrode (122 in first capacitor region S1) and a second bottom electrode (122 in second capacitor region S2),
wherein the first top electrode (123 in first capacitor region S1) is spaced from the second top electrode (123 in second capacitor region S2) by a first distance (e.g., a distance. X1) and the first bottom electrode (122 in first capacitor region S1) is spaced from the second top electrode (123 in second capacitor region S2) by a second distance (e.g., a distance. X2) that is less than the first distance (X1) (see fig. 2; because of the tapered shape of the top and bottom electrodes, the bottom electrodes 122 extend further from the top electrodes 123 and hence, X2<X1).
However, Park does not expressly disclose forming the top electrode, the first dielectric and the bottom electrode from etching the second electrode layer, the dielectric layer and the first electrode layer. In other words, Park does not show the etching steps for patterning the top and bottom electrode layers and the dielectric layer.
In the same field of endeavor, Lei discloses in figs. 1-4, a method of forming capacitors in an integrated device, comprising:
forming the top electrode, the first dielectric and the bottom electrode from etching the conformally formed second electrode layer 10, the dielectric layer 3 and the first electrode layer 11 (see figs. 2-3).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of the electrode leading-out method of Lei into the MIM capacitors of Ching/Park to have a high-density capacitor with high precision and high reliability (see abstract of Lei).
Claim(s) 28-31 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20190019787 A1; hereinafter “Park”) in view of Bernstein et al. (US 20110027962 A1; hereinafter “Bernstein”).
In re claim 28, Park discloses in figs. 1-3, 11-12, a method of forming capacitors in an integrated device, comprising:
forming an interlayer dielectric (e.g., an upper oxide layer of 210) over a substrate (e.g., a lower oxide layer of 210) (“the substrate 210 formed of any one selected from the group consisting of Si, SiO.sub.2, Al.sub.2O.sub.3, MgO, LaAlO.sub.3, and SrTiO.sub.3, or a combination thereof”; ¶91);
etching the interlayer dielectric 210 (¶93), concurrently removing dielectric material from a first region 205a at a first etch rate and removing dielectric material from a second region 205b at a second etch rate (¶126);
depositing a first electrode layer 221, 223 over interlayer dielectric 210 (¶95, 104), the first electrode layer 221 having first outer sidewalls within the first region 205a that are separated by a first width (¶93) and second outer sidewalls within the second region 205b separated by a second width (¶102); and
subsequently depositing a dielectric layer 211, 212 and a second electrode layer 222, 224 over the first electrode layer 221, 223, wherein the dielectric layer 211, 212 and the second electrode layer 222, 224 extend into the first region 205a and the second region 205b (¶97-98, 106-107).
Park does not expressly disclose the second etch rate is less than the first etch rate. In other words, Ching does not expressly disclose the etch rate of the shallower trench is less than the etch rate of the deeper trench.
In the same field of endeavor, Bernstein discloses a method of forming deep and shallow trenches 45, 50 in a substrate 10 with a hard mask layer 15 (figs. 1-7):
wherein, an etch rate of the shallower trench 50 is less than the etch rate of the deeper trench 45 (fig. 5; ¶24. “More specifically, due to the relatively smaller second dimension d2, RIE lag will effectively stop the etching of the capacitor trench 50 at a particular depth while the etching of the TSV trench 45 continues to a greater depth in the wafer 10 during the same etch process. In this manner, a same etching process may be used to substantially simultaneously form the TSV trench 45 and the capacitor trench 50, with the TSV trench 45 being deeper than the capacitor trench 50”).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of deep and shallow trench formation method of Bernstein into the method of Park.
One would have been motivated to do so as Bernstein teaches RIE lag is used to selectively control a depth of the shallow trench (i.e., capacitor trench) relative to a depth of the deep trench (i.e., TSV trench). In this manner, shallow trench and a deep trench can be formed using the same etch, thereby reducing process complexity and overall manufacturing cost (¶14 of Bernstein).
In re claim 29, Park, as modified by Bernstein, discloses the method of claim 28 outlined above.
Park does not expressly disclose: the method further comprising:
forming a first masking layer over the interlayer dielectric before etching the interlayer dielectric; and
patterning the first masking layer before etching the interlayer dielectric,
removing material from the first masking layer to form a first opening with the first width and a second opening with the second width,
wherein the interlayer dielectric is subsequently etched in the first region underlying the first opening and the second region underlying the second opening.
In the same field of endeavor, Bernstein discloses in figs. 1-7,
forming a first masking layer 20, 15 over the substrate 10 before etching the substrate (fig. 2; ¶19); and
patterning the first masking layer 20, 15 before etching the substrate 10 (fig. 3; ¶20),
removing material from the first masking layer 20, 15 to form a first opening 35 with the first width and a second opening 40 with the second width (fig. 3; ¶20),
wherein the substrate 10 is subsequently etched in the first region 45 underlying the first opening 35 and the second region 50 underlying the second opening 40 (fig. 5; ¶23-24).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Bernstein and pattern the interlayer dielectric of Park employing a making layer as this would allow to selectively control the dimensions of different openings in a hard mask and employ the RIE lag to form trenches of varying depth in a single etch (¶15 of Bernstein).
In re claim 30, Park, as modified by Bernstein, discloses the method of claim 28, wherein the etching of the interlayer dielectric (Park: 210) results in both a first opening in the first region (Park: 205a) having the first width and a first depth (Park: figs. 11-12; ¶126) and a second opening in the second region (Park: 205b) having the second width and a second depth (Park: figs. 11-12; ¶126), wherein the second depth (depth of 205b in Park, in fig. 11) is less than the first depth (depth of 205b in Park, in fig. 11).
In re claim 31, Park, as modified by Bernstein, discloses the method of claim 28 outlined above.
Park further discloses in figs. 11-12, wherein the second electrode layer 222, 224 is deposited after the dielectric layer 211, 212,
wherein a portion of the second electrode layer within the first region 222 has third outer sidewalls separated by a third width (i.e., width of the upper electrode layer 222 in the first trench 205a), and
wherein a portion of the second electrode layer within the second region 224 has fourth outer sidewalls separated by a fourth width (i.e., width of the upper electrode layer 224 in the second trench 205b) that is less than the first width (¶126; all the electrode layers and the dielectric layers are formed having uniform thickness, hence, the upper electrode 222 in the wider trench 205a has a larger width than the upper electrode 224 in the narrower trench 205b).
Allowable Subject Matter
Claim 32 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
In re claim 32, Park, as modified by Bernstein, discloses the method of claim 28 outlined above.
Park does not expressly disclose the method further comprising forming a hard mask layer over the interlayer dielectric, wherein the etching of the interlayer dielectric further comprises etching through the hard mask layer, and
wherein after the etching of the interlayer dielectric and the hard mask layer,
the hard mask layer has a first thickness between the first region and the second region, and a second thickness spaced from the first region and the second region that is greater than the first thickness.
In the same field of endeavor, Bernstein discloses in figs. 1-7,
forming a hard mask layer 15 over the substrate 10 (fig. 1; ¶17),
wherein the etching of the substrate 10 further comprises etching through the hard mask layer 15 (fig. 5; ¶23).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to employ the teachings of Bernstein and pattern the interlayer dielectric of Park employing a hard mask layer as this would allow to selectively control the dimensions of different openings in a hard mask and employ the RIE lag to form trenches of varying depth in a single etch (¶15 of Bernstein).
Park, as modified by Bernstein, does not expressly disclose wherein after the etching of the interlayer dielectric and the hard mask layer, the hard mask layer has a first thickness between the first region and the second region, and a second thickness spaced from the first region and the second region that is greater than the first thickness.
In the same field of endeavor, Kawahara et al. (US 20100123199 A1) teaches in figs. 1-16, a method of forming capacitive elements 90, wherein after the etching of an interlayer dielectric 41 and a hard mask layer 94, the hard mask layer 94 has a first reduced thickness between the first region (e.g., a left opening) and the second region (e.g., a right opening) because of over-etching (figs. 6-8; ¶111).
However, Kawahara does not teach a second thickness of the hard mask layer spaced from the first region and the second region that is greater than the first thickness and it would not have been obvious to one of ordinary skill in the art to do so and arrive at the claimed invention.
Therefore, the combination of Park, Bernstein and Kawahara do not teach entire claim 32.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NILUFA RAHIM whose telephone number is (571)272-8926. The examiner can normally be reached M-F 9am-5:30pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara J. Green can be reached at (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/NILUFA RAHIM/Primary Examiner, Art Unit 2893