DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/12/2026 has been entered.
Response to Arguments
Applicant's arguments filed 2/6/2026 have been fully considered but they are moot in view of the new grounds of rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (US PGPub 2020/0328186; hereinafter “Liu”) in view of Liu et al. (US PGPub 2020/0328188; hereinafter “Liu2”), Yamazaki et al. (US PGPub 2022/0375529; hereinafter “Yamazaki”), and Majhi et al. (US PGPub 2021/0375873; hereinafter “Majhi”).
Re claim 1: Liu teaches (e.g. fig. 14) a method of fabricating a memory structure, comprising: forming a first device (microprocessor 101; e.g. paragraphs 63 and 88) located in a first memory region (region of 300) of a die (3D IC device 1400; e.g. paragraph 166); forming a second memory array (DRAM chip 103; e.g. paragraph 63) located in a second memory region (region of 103) of the die (1400), the second memory array (103) comprising an array of 1T1C memory devices (DRAM device 404 and DRAM capacitor 430; e.g. paragraph 94); forming a second interconnect level structure (DRAM interconnect layer 414; e.g. paragraph 144) over the second memory region (region of 103); forming a third memory array (NAND memory device 740; e.g. paragraph 125) located in a third memory region (region of 740) of the die (1400) over the second interconnect level structure (414) and the first memory region (region of 300), the third memory region (region of 740) comprising 3-dimensional array of memory devices (array of memory strings 946; e.g. paragraph 140) including word lines (conductor layer 948 connected to word line contacts 966; e.g. paragraph 188) that are shared between a plurality of stacked active device layers (layers of memory string 946) within the 3-dimensional array (array of memory strings 946; e.g. paragraph 140); forming at least one data bus (conductive lines 418; e.g. paragraph 92 and fig. 14) laterally extending across the first memory region, the second memory region (region of 103), and third memory region and configured to provide data transfer among the first memory array, the second memory array (103), and the third memory array; and forming peripheral circuit devices (CPU devices 204; e.g. paragraph 65) at a semiconductor material layer (202) of the die (1400), the peripheral circuit devices (204) configured to control the first device (300), the second memory array (103), and the third memory array (740).
Liu is silent as to explicitly teaching the first device area having a first memory array, the first memory array comprising an array of SRAM memory devices; the third memory region comprising an array of FeFET memory devices.
Liu2 teaches (e.g. figs. 1A, 4A) the first device area (CPU chip 402 has processor regions 412 and an array of SRAM cells 414; e.g. paragraph 54) having a first memory array (SRAM cells 414; e.g. paragraph 54), the first memory array (414) comprising an array of SRAM memory devices (SRAM cells 414; e.g. paragraph 54).
Yamazaki teaches the third memory region comprising an array of FeFET memory devices (non-volatile memory structures include 3D NAND flash, resistive RAM, and ferroelectric RAM; e.g. paragraph 96).
It would be obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the method of forming processor chip with SRAM cells as taught by Liu2 and the method of forming FeRAM cells for the 3D NAND storage elements as taught by Yamazaki in the method of Liu in order to have the predictable result of increasing device integration such that more powerful devices can be manufactures within a smaller overall device used by a person and in order to have the predictable result of using ferroelectric memory cells which have higher operating speeds with low power consumption to improve memory device efficiency, respectively.
Liu in view of Liu2 and Yamazaki is silent as to explicitly teaching the first memory array, the second memory array, and the third memory array are monolithically formed on the die.
Majhi teaches (e.g. figs. 1 and 4) the first memory array (101 of Liu), the second memory array (103 of Liu), and the third memory array (740 of Liu) are monolithically formed (DRAM, SRAM, MRAM, RRAM, NAND memory devices can be formed within die 1502 in a monolithic memory stack; e.g. paragraphs 43 and 32) on the die (1502).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the monolithically formed memory stack as taught by Majhi in the method of Liu in view of Liu2 and Yamazaki in order to have the predictable result of improving latency and higher bandwidth of the device of Liu (see paragraph 16 of Majhi).
Re claim 2: Liu in view of Liu2, Yamazaki, and Majhi teaches the method of claim 1, wherein: forming the at least one data bus (418 of Liu) further comprises forming a plurality of interconnect level structures (214, 218, 414, 914 of Liu); forming the first memory array (414 of Liu2) further comprises forming the SRAM memory devices (SRAM cells 414; e.g. paragraph 54 of Liu2) on the semiconductor material layer (408 of Liu2) of the die (1400 of Liu); forming the second memory array (103 of Liu) further comprises forming the 1T1C memory devices (DRAM device 404 and DRAM capacitor 430; e.g. paragraph 94 of Liu) over a first interconnect level structure (218 of Liu) of the plurality of interconnect level structures (214, 218, 414, 914 of Liu); forming the third memory array (740 of Liu/FeRam of Yamazaki) further comprises forming the FeFET memory devices over a second interconnect level structure (414 of Liu) of the plurality of interconnect level structures (214, 218, 414, 914 of Liu); and forming the peripheral circuit devices (microprocessor 101; e.g. paragraphs 63 and 88 of Liu; processor regions 412; e.g. paragraph 54 of Liu2) further comprises configuring the peripheral circuit devices (processor regions 412; e.g. paragraph 54 of Liu2) to provide control access across array boundaries (microprocessor 101 of Liu would control read and write operations of data; e.g. paragraphs 63 and 88).
Re claim 3: Liu in view of Liu2, Yamazaki, and Majhi teaches the method of claim 1, wherein the peripheral circuit devices comprise sense amplifiers and decoder circuits (decoders and sense amplifiers; e.g. paragraph 93 of Liu) for the one or more of the respective first memory array (SRAM cells 414; e.g. paragraph 54 of Liu2), the second memory array (DRAM device 404 and DRAM capacitor 430; e.g. paragraph 94 of Liu), and the third memory array (740 of Liu/FeRam of Yamazaki).
Re claim 4: Liu in view of Liu2, Yamazaki, and Majhi teaches the method of claim 3, wherein forming the peripheral circuit devices (processor regions 412; e.g. paragraph 54 of Liu2) further comprises forming data bus switching devices (decoders and sense amplifiers, timing, and controls signals; e.g. paragraph 93 of Liu) that are configured to control data transfer between the first memory array (SRAM cells 414; e.g. paragraph 54 of Liu2), the second memory array (DRAM device 404 and DRAM capacitor 430; e.g. paragraph 94 of Liu), and the third memory array (740 of Liu/FeRam of Yamazaki).
Re claim 5: Liu in view of Liu2, Yamazaki, and Majhi teaches the method of claim 3, wherein forming the peripheral circuit devices (processor regions 412; e.g. paragraph 54 of Liu2) further comprises forming thin film transistor devices (transistors 704 formed by thin film depositions; e.g. paragraph 99 of Liu2) located at one or both of a first interconnect level (107b of Liu) and a second interconnect level (740 of Liu).
Re claim 6: Liu in view of Liu2, Yamazaki, and Majhi teaches the method of claim 1, further comprising: forming computing logic devices (CPU chip 402 has processor regions 412 and an array of SRAM cells 414; e.g. paragraph 54 of Liu2) located on the semiconductor material layer (202 of Liu/408 of Liu2) of the die, wherein forming the at least one data bus further comprises coupling the computing logic devices (processor regions 412 and an array of SRAM cells 414; e.g. paragraph 54 of Liu2) to the first memory array (an array of SRAM cells 414; e.g. paragraph 54 of Liu2), the second memory array (DRAM device 404 and DRAM capacitor 430; e.g. paragraph 94 of Liu), the third memory array (740 of Liu/FeRam of Yamazaki), and the peripheral circuit devices (processor regions 412; e.g. paragraph 54 of Liu2), wherein the peripheral circuit devices (processor regions 412; e.g. paragraph 54 of Liu2) are located beneath the second memory array (DRAM device 404 and DRAM capacitor 430; e.g. paragraph 94 of Liu) and the third memory array (740 of Liu/FeRam of Yamazaki) such that the peripheral circuit devices (412 of Liu2) overlap with the second memory array (404,430 of Liu) and the third memory array (740 of Liu) in a plan view.
Re claim 7: Liu in view of Liu2, Yamazaki, and Majhi teaches the method of claim 1, further comprising forming one or more of the second memory array and the third memory array (740 of Liu/FeRam of Yamazaki) as a 3-dimensional memory array.
Claim(s) 21-26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (US PGPub 2020/0328186; hereinafter “Liu”) in view of Liu et al. (US PGPub 2020/0328188; hereinafter “Liu2”) and Yamazaki et al. (US PGPub 2022/0375529; hereinafter “Yamazaki”), Jeon et al. (US PGPub 2019/0267088; hereinafter “Jeon”), and Majhi.
Re claim 21: Liu teaches (e.g. fig. 14) a method of forming a memory structure on a single semiconductor die (1400), the method comprising: forming a first device (microprocessor 101; e.g. paragraphs 63 and 88) in a first memory region (region of 101) at a semiconductor material layer (202) of the die (1400); forming a second memory array (DRAM chip 103; e.g. paragraph 63) comprising 1T1C memory devices (DRAM device 404 and DRAM capacitor 430; e.g. paragraph 94) in a second memory region (location of 103) located over a first interconnect level structure (214); forming a third memory array (3D NAND memory device 740; e.g. paragraph 125) comprising memory devices in a third memory region (region of 740) located over a second interconnect level structure (414), the third memory region (740) vertically above the second memory region (103); and forming a data bus (conductive lines 418; e.g. paragraph 92 and fig. 14) configured to provide data transfer among the first device (101), the second memory array (103), and the third memory array (740), the data bus (418) comprising interconnects laterally and vertically extending across the first, second, and third memory regions (regions of 101, 103, 740, respectively).
Liu is silent as to explicitly teaching the first device being a first memory array comprising SRAM memory devices; the third memory array comprising FeFET memory devices; forming peripheral circuit devices at the semiconductor material layer of the die, the peripheral circuit devices located beneath the second memory array and the third memory array and configured to control the first memory array, the second memory array, and the third memory array, wherein the peripheral circuit devices overlap with the second memory array and the third memory array.
Liu2 teaches (e.g. figs. 1A, 4A) the first device being a first memory array (CPU chip 402 has processor regions 412 and an array of SRAM cells 414; e.g. paragraph 54) comprising SRAM memory devices (SRAM cells 414; e.g. paragraph 54); wherein the peripheral circuit devices (processor regions 412; e.g. paragraph 54 of Liu2) overlap with the second memory array (DRAM device 404 and DRAM capacitor 430; e.g. paragraph 94 of Liu) and the third memory array (740 of Liu/FeRam of Yamazaki).
Yamazaki teaches the third memory array (740 of Liu) comprising FeFET memory devices (non-volatile memory structures include 3D NAND flash, resistive RAM, and ferroelectric RAM; e.g. paragraph 96).
Jeon teaches the general concept of integrating diverse memory types within a single or between plural chips and further teaches (e.g. paragraphs 45, 50, 93) forming peripheral circuit devices (peripheral circuit region 50; e.g. paragraph 45) at the semiconductor material layer (202 of CPU 101 of Liu) of the die (1400 of Liu), the peripheral circuit devices (50) located beneath the second memory array (103 of Liu) and the third memory array (740 of Liu) and configured to control the first memory array (414 of Liu2), the second memory array (103 of Liu), and the third memory array (740 of Liu)
It would be obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the method of forming processor chip with SRAM cells as taught by Liu2 and the method of forming FeRAM cells for the 3D NAND storage elements as taught by Yamazaki and the method of using a peripheral circuit as taught by Jeon in the method of Liu in order to have the predictable result of increasing device integration such that more powerful devices can be manufactures within a smaller overall device used by a person and in order to have the predictable result of using ferroelectric memory cells which have higher operating speeds with low power consumption to improve memory device efficiency, and in order to have the predictable result of using an appropriate peripheral circuit so that data reading, writing, and transferring operations can effectively be processed since memory ells do not program themselves and require appropriate circuitry, respectively.
Liu in view of Liu2 and Yamazaki is silent as to explicitly teaching the first memory array, the second memory array, and the third memory array are monolithically formed in one or more physical levels above a single substrate.
Majhi teaches (e.g. figs. 1 and 4) the first memory array (101 of Liu), the second memory array (103 of Liu), and the third memory array (740 of Liu) are monolithically formed (DRAM, SRAM, MRAM, RRAM, NAND memory devices can be formed within die 1502 in a monolithic memory stack; e.g. paragraphs 43 and 32) in one or more physical levels above a single substrate (110, 115; e.g. paragraph 19).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the monolithically formed memory stack as taught by Majhi in the method of Liu in view of Liu2 and Yamazaki in order to have the predictable result of improving latency and higher bandwidth of the device of Liu (see paragraph 16 of Majhi).
Re claim 22: Liu in view of Liu2, Yamazaki, Jeon, and Majih teaches the method of claim 21, wherein the third memory array (740 of Liu) is formed as a three-dimensional memory array (3D NAND memory device 740; e.g. paragraph 125) comprising word lines (conductor layers 948 of a 3D NAND are wordlines of Liu) that are shared between two or more stacked active device layers.
Re claim 23: Liu in view of Liu2, Yamazaki, Jeon, and Majih teaches the method of claim 21, wherein forming the peripheral circuit devices comprises forming sense amplifiers, decoder circuits, and data bus switching devices (decoders and sense amplifiers; e.g. paragraph 93 of Liu) configured to control access across the first memory array (414 of Liu2), the second memory array (101 of Liu), and the third memory array (740 of Liu).
Re claim 24: Liu in view of Liu2, Yamazaki, Jeon, and Majih teaches the method of claim 21, wherein forming the second memory array (101 of Liu), and the third memory array (740 of Liu) comprises forming thin film transistor selector devices (transistors 704 formed by thin film depositions; e.g. paragraph 99 of Liu2) at respective interconnect levels of the die.
Re claim 25: Liu in view of Liu2 and Yamazaki teaches the method of claim 21, further comprising forming computing logic devices (CPU chip 402 has processor regions 412 and an array of SRAM cells 414; e.g. paragraph 54 of Liu2) located on the semiconductor material layer (202 of Liu/408 of Liu2) of the die, wherein forming the at least one data bus further comprises coupling the computing logic devices (processor regions 412 and an array of SRAM cells 414; e.g. paragraph 54 of Liu2) to the first memory array (an array of SRAM cells 414; e.g. paragraph 54 of Liu2), the second memory array (DRAM device 404 and DRAM capacitor 430; e.g. paragraph 94 of Liu), the third memory array (740 of Liu/FeRam of Yamazaki), and the peripheral circuit devices (412 of Liu2) such that data transfer initiated by the computing logic devices (CPU chip 402 has processor regions 412 and an array of SRAM cells 414; e.g. paragraph 54 of Liu2) are controlled by the peripheral circuit devices (412 of Liu2).
Re claim 26: Liu in view of Liu2, Yamazaki, Jeon, and Majih teaches the method of claim 21, further comprising forming peripheral circuit devices (peripheral circuit region 50; e.g. paragraph 45) are formed at the semiconductor material layer (202 of CPU 101 of Liu/110 of Majhi), prior to forming (monolithic memory stacks as disclosed by Majhi requires the peripheral CMOS devices 115 to be formed first) the second memory array (103 of Liu) and the third memory array (740 of Liu).
Allowable Subject Matter
Claims 12, 13, and 16-20 are allowed.
The prior art of record is silent as to explicitly teaching “data bus to comprises common bit lines that are switchably shared between the first memory region, the second memory region, and the third memory region such that the at least one data bus is configured to switchably transfer data among the first memory region, the second memory region, and the third memory region”
Conclusion
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/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2898
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