DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-9, 14-18, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chee (US 2017/0179145) in view of Hsu et al. (US 2021/0083109).
With regard to claim 1, Chee teaches, in Fig 19, a semiconductor device, comprising: a substrate (100) that includes a first portion (LV), a second portion (MV), and a third portion (HV); a first device on the first portion of the substrate (see figure, device including 240); a second device on the second portion of the substrate (see figure, device including 210); and a third device on the third portion of the substrate (see figure, device including 190) and comprising: an oxide layer (190) on the third portion, wherein a thickness of the oxide layer is greater than thicknesses of other oxide layers utilized for the first device and the second device ([0012]), a gate on the oxide layer (shown but not labeled in figure, see [0012]), a set of spacers on opposite sides of the gate (shown but not labeled in figure, see [0058]).
Chee does not explicitly teach a source region in the third portion of the substrate on one side of the gate, a drain region in the third portion of the substrate on another side of the gate, and a protective oxide layer on a portion of the gate and a portion of the drain region.
Hsu teaches, in Fig 1, a source region (30B) in the third portion of the substrate (of Chee) on one side of the gate (20), a drain region (30A) in the third portion of the substrate on another side of the gate, and a protective oxide layer (40) on a portion of the gate and a portion of the drain region, “for reducing the channel resistance in the high voltage semiconductor device 101 and increasing the current of the high voltage semiconductor device,” ([0018]).
Therefore, it would have been obvious to the ordinary artisan at the effective time of filing to combine the device of Chee with the transistor details and protective layer of Hsu to reduce channel resistance and increase current of the high voltage semiconductor device.
With regard to claim 2, Hsu teaches, in Fig 1, silicide layers (50) over portions of the gate, the source region, and the drain region.
With regard to claim 3, Hsu teaches, in Fig 1, that the protective oxide layer covers a portion of the third portion of the substrate and covers an entire surface of a spacer (26) in the set of spacers.
With regard to claim 4, Hsu teaches, in Fig 1, that the third device further comprises: silicide layers (50) over portions of the gate, the source region, and the drain region except for the portion of the gate and the portion of the drain region covered by the protective oxide layer (see figure).
With regard to claim 5, Chee teaches, in Fig 19, that the third device is a high voltage device ([0045]).
In reference to the claim language referring to "the first device is a core device, the second device is an input/output device" intended use and other types of functional language must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. In a claim drawn to a process of making, the intended use must result in a manipulative difference as compared to the prior art. In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963); Ex parte Masham, 2USPQ2d 1647 (Bd. Pat. App. &Inter. 1987). In the instant case, Chee/Hsu teaches shows all structural limitations specifically recited in the claim and it appears that the recited functional limitation does not affect the structure of Chee/Hsu teaches device.
With regard to claim 6, Hsu teaches, in Fig 1, that the third portion of the substrate includes a p-type body region (W2) and an n-type drift region (W1), wherein the source region is in the p-type body region and the drain region is in the n-type drift region.
With regard to claim 7, Chee teaches, in Fig 19, that the third device is a high voltage device ([0045]).
With regard to claim 8, Chee teaches, in Fig 19, a semiconductor device, comprising: a substrate (100) that includes a first portion (LV), a second portion (MV), and a third portion (HV); a first device (see figure, device including 240) on the first portion of the substrate and comprising: a first oxide layer (240) on the first portion; a second device (see figure, device including 210) on the second portion of the substrate and comprising: a second oxide layer (210) on the second portion, wherein a thickness of the second oxide layer is greater than a thickness of the first oxide layer ([0012]); and a third device (see figure, device including 190) on the third portion of the substrate and comprising: a third oxide layer (190) on the third portion, wherein a thickness of the third oxide layer is greater than the thickness of the second oxide layer ([0012]), a gate on the third oxide layer (shown but not labeled in figure, see [0012]), a set of spacers on opposite sides of the gate (shown but not labeled in figure, see [0058]).
Chee does not explicitly teach a source region in the third portion of the substrate on a first side of the gate, a drain region in the third portion of the substrate on a second side of the gate, and a fourth oxide layer on a portion of the gate and a portion of the drain region.
Hsu teaches, in Fig 1, a source region (30B) in the third portion of the substrate (of Chee) on a first side of the gate (20), a drain region (30A) in the third portion of the substrate on a second side of the gate, and a fourth oxide layer (40) on a portion of the gate and a portion of the drain region, “for reducing the channel resistance in the high voltage semiconductor device 101 and increasing the current of the high voltage semiconductor device,” ([0018]).
Therefore, it would have been obvious to the ordinary artisan at the effective time of filing to combine the device of Chee with the transistor details and protective layer of Hsu to reduce channel resistance and increase current of the high voltage semiconductor device.
With regard to claim 9, Hsu teaches, in Fig 1, a first silicide layer (relevant instance of 50) over another portion of the gate; a second silicide layer (relevant instance of 50) over a portion of the source region; and a third silicide layer (relevant instance of 50) over a portion of the drain region.
With regard to claim 14, Chee teaches, in Fig 19, that that the third device is a high voltage device ([0045]).
In reference to the claim language referring to "the first device is a core device, the second device is an input/output device" intended use and other types of functional language must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. In a claim drawn to a process of making, the intended use must result in a manipulative difference as compared to the prior art. In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963); Ex parte Masham, 2USPQ2d 1647 (Bd. Pat. App. &Inter. 1987). In the instant case, Chee/Hsu teaches shows all structural limitations specifically recited in the claim and it appears that the recited functional limitation does not affect the structure of Chee/Hsu teaches device.
With regard to claim 15, Chee teaches, in Fig 19, a semiconductor device, comprising: a substrate (100) that includes a first portion (LV), a second portion (MV), and a third portion (HV); a first device (see figure, device including 240) on the first portion of the substrate and comprising: a first oxide layer (240) on the first portion, and a first gate (shown but not labeled in figure, see [0012]) on the first oxide layer; a second device (see figure, device including 210) on the second portion of the substrate and comprising: a second oxide layer (210) on the second portion, wherein a thickness of the second oxide layer is greater than a thickness of the first oxide layer ([0012]), and a second gate (shown but not labeled in figure, see [0012]) on the second oxide layer; and a third device (see figure, device including 190) on the third portion of the substrate and comprising: a third oxide layer (190) on the third portion, wherein a thickness of the third oxide layer is greater than the thickness of the second oxide layer ([0012]), a third gate (shown but not labeled in figure, see [0012]) on the third oxide layer, a first spacer on a first side of the third gate, a second spacer on a second side of the third gate (shown but not labeled in figure, see [0058]).
Chee does not explicitly teach a source region in the third portion of the substrate on the first side of the third gate, a drain region in the third portion of the substrate on the second side of the third gate, and a fourth oxide layer on a portion of the third gate and a portion of the drain region.
Hsu teaches, in Fig 1, a source region (30B) in the third portion of the substrate (of Chee) on the first side of the third gate (20), a drain region (30A) in the third portion of the substrate on the second side of the third gate, and a fourth oxide layer (40) on a portion of the third gate and a portion of the drain region, “for reducing the channel resistance in the high voltage semiconductor device 101 and increasing the current of the high voltage semiconductor device,” ([0018]).
Therefore, it would have been obvious to the ordinary artisan at the effective time of filing to combine the device of Chee with the transistor details and protective layer of Hsu to reduce channel resistance and increase current of the high voltage semiconductor device.
With regard to claim 16, Hsu teaches, in Fig 1, that the fourth oxide layer is on the second spacer (relevant instance of 26).
With regard to claim 17, Hsu teaches, in Fig 1, a first silicide layer (relevant instance of 50) over another portion of the third gate; a second silicide layer (relevant instance of 50) a portion of the source region; and a third silicide layer (relevant instance of 50) over another portion of the drain region.
With regard to claim 18, Hsu teaches, in Fig 1, that the third portion of the substrate includes a p-type body region (W2) and an n-type drift region (W1), wherein the source region is in the p-type body region and the drain region is in the n-type drift region.
With regard to claim 20, Chee teaches, in Fig 19, that that the third device is a high voltage device ([0045]).
In reference to the claim language referring to "the first device is a core device, the second device is an input/output device" intended use and other types of functional language must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. In a claim drawn to a process of making, the intended use must result in a manipulative difference as compared to the prior art. In re Casey, 152 USPQ 235 (CCPA 1967); In re Otto, 136 USPQ 458, 459 (CCPA 1963); Ex parte Masham, 2USPQ2d 1647 (Bd. Pat. App. &Inter. 1987). In the instant case, Chee/Hsu teaches shows all structural limitations specifically recited in the claim and it appears that the recited functional limitation does not affect the structure of Chee/Hsu teaches device.
Claim(s) 10-13 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chee (US 2017/0179145) in view of Hsu et al. (US 2021/0083109) and Koutny, JR. et al. (US 2008/0293207).
With regard to claim 10, Chee/Hsu teach most of the limitations of this claim as set forth above with regard to claim 8.
Chee also teaches, in Fig 19, that the gate is a first gate, the set of spacers is a first set of spacers, and wherein the first device further comprises: a second gate on the first oxide layer (shown but not labeled in figure, see [0012]), a second set of spacers (shown but not labeled in figure, see [0058]) on opposite sides of the second gate.
Hsu teaches, in Fig 1, that the source region is a first source region, and the drain region is a first drain region.
Chee/Hsu do not explicitly teach a second source region in the first portion of the substrate on a first side of the second gate, and a second drain region in the first portion of the substrate on a second side of the second gate.
Koutny teaches, in Fig 4A, a second source region (480) in the first portion of the substrate on a first side of the second gate, and a second drain region (480) in the first portion of the substrate on a second side of the second gate to, “incorporate, for example, a memory device on the same substrate as a logic device to reduce the cost of fabrication as well as increase communication bandwidth between the memory and logic devices,” ([0004]).
Therefore, it would have been obvious to the ordinary artisan at the effective time of filing to combine the device of Chee/Hsu with the transistor details of Koutny to incorporate a memory device on the same substrate as a logic device to reduce the cost of fabrication as well as increase communication bandwidth between the memory and logic devices.
With regard to claim 11, Koutny teaches, in Fig 4G, a first silicide layer (relevant instance of 482) over the second gate; a second silicide layer (relevant instance of 482) a portion of the second source region; and a third silicide layer (relevant instance of 482) over a portion of the second drain region.
With regard to claim 12, Chee/Hsu teach most of the limitations of this claim as set forth above with regard to claim 8.
Chee also teaches, in Fig 19, that the gate is a first gate, the set of spacers is a first set of spacers, and wherein the second device further comprises: a second gate on the second oxide layer (shown but not labeled in figure, see [0012]), a second set of spacers (shown but not labeled in figure, see [0058]) on opposite sides of the second gate.
Hsu teaches, in Fig 1, that the source region is a first source region, and the drain region is a first drain region.
Chee/Hsu do not explicitly teach a second source region in the second portion of the substrate on a first side of the second gate, and a second drain region in the second portion of the substrate on a second side of the second gate.
Koutny teaches, in Fig 4A, a second source region (480) in the second portion of the substrate on a first side of the second gate, and a second drain region (480) in the second portion of the substrate on a second side of the second gate to, “incorporate, for example, a memory device on the same substrate as a logic device to reduce the cost of fabrication as well as increase communication bandwidth between the memory and logic devices,” ([0004]).
Therefore, it would have been obvious to the ordinary artisan at the effective time of filing to combine the device of Chee/Hsu with the transistor details of Koutny to incorporate a memory device on the same substrate as a logic device to reduce the cost of fabrication as well as increase communication bandwidth between the memory and logic devices.
With regard to claim 13, Koutny teaches, in Fig 4G, a first silicide layer (relevant instance of 482) over the second gate; a second silicide layer (relevant instance of 482) a portion of the second source region; and a third silicide layer (relevant instance of 482) over a portion of the second drain region.
With regard to claim 19, Chee/Hsu teach most of the limitations of this claim as set forth above with regard to claim 15.
Hsu also teaches, in Fig 1, a third silicide layer (50) over a portion of the third gate.
Chee/Hsu do not explicitly teach a first silicide layer over the first gate; a second silicide layer over the second gate.
Koutny teaches, in Fig 4A, a first silicide layer (482) over the first gate (378); a second silicide layer (482) over the second gate (378, here applying the silicide layer of Koutny to the first and second gates of Chee/Hsu) to, “incorporate, for example, a memory device on the same substrate as a logic device to reduce the cost of fabrication as well as increase communication bandwidth between the memory and logic devices,” ([0004]).
Therefore, it would have been obvious to the ordinary artisan at the effective time of filing to combine the device of Chee/Hsu with the transistor details of Koutny to incorporate a memory device on the same substrate as a logic device to reduce the cost of fabrication as well as increase communication bandwidth between the memory and logic devices.
Conclusion
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/RAJ R GUPTA/
Primary Examiner, Art Unit 2829
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