Prosecution Insights
Last updated: April 19, 2026
Application No. 18/362,649

System Formed Through Package-In-Package Formation

Non-Final OA §103§112§DP
Filed
Jul 31, 2023
Examiner
SHAMSUZZAMAN, MOHAMMED
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Taiwan Semiconductor Manufacturing Co., Ltd.
OA Round
3 (Non-Final)
81%
Grant Probability
Favorable
3-4
OA Rounds
2y 7m
To Grant
99%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allow Rate
720 granted / 892 resolved
+12.7% vs TC avg
Strong +57% interview lift
Without
With
+56.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
28 currently pending
Career history
920
Total Applications
across all art units

Statute-Specific Performance

§101
1.7%
-38.3% vs TC avg
§103
50.0%
+10.0% vs TC avg
§102
6.6%
-33.4% vs TC avg
§112
33.4%
-6.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 892 resolved cases

Office Action

§103 §112 §DP
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 09/09/2025 has been entered. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. 3. Claims 1-20 are rejected under 35 U.S.C. 112(b), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. Claim 1 define” a distinguishable interface”. but its not clear or marked or defined how/why it is distinguishable. For examination purpose an interface is considered. A clarification is required Claim 11 defines “wherein a first part of the first gap-filling material physically contacts a second part of the first gap-filling material to form a vertical interface, and wherein the first part and the second part are formed of different materials” is indefinite. It is not clear or marked or defined which is a first part of the first gap-filling material or a second part of the first gap-filling material. How the material of the first part and second part is different? Is a second part is from the second ga-filling material? Appropriate correction is required. Claims 2-6, 9, 12-17, 21-22 are also rejected being dependent on rejected claims 1, 11. Double Patenting The nonstatutory double patenting rejection is based on a judicially createddoctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the "right to exclude" granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Omum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321 (c) or 1.321(d)may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. Effective January 1, 1994, a registered attorney or agent of record may sign aterminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b). Claims 1-2, 11-13, 18 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over claims 1-2, 10-13, 16 of US Patent 11,189,599 in view of Yu et al (US 2015/0318246 A1). Although the conflicting claims are not identical, they are not patentably distinct from each other. Regarding claim 1: Claim 1 of ‘9599 teaches about a package comprising: a first device die; a second device die over and bonded the first device die through both of fusion bonds and metal-to-metal direct bonds; a first isolation region encapsulating the first device die therein, wherein first edges of the first isolation region are vertically aligned to respective second edges of the second device die; a third device die under and bonded to the first device die through both of fusion bonds and metal-to-metal direct bonds; and a second isolation region encapsulating the first device die and the first isolation region therein, wherein third edges of the second isolation region are vertically aligned to respective fourth edges of the third device die, and wherein the first isolation region and the second isolation region form a distinguishable interface. Claim 1 of ‘9599 does not teach wherein first edges of the first isolation region are vertically aligned to respective second edges of the second device die, wherein third edges of the second isolation region are vertically aligned to respective fourth edges of the third device die, and wherein the first isolation region and the second isolation region form a distinguishable interface.. However claim 18 of ‘9599 teaches edges of the first gap-filling material are flush with respective edges of the second device die, and wherein edges of the second gap-filling material are flush with respective edges of the third device die and Yu teaches in Fig. 46 as marked below wherein first edges of the first isolation region are vertically aligned to respective second edges of the second device die, wherein third edges of the second isolation region are vertically aligned to respective fourth edges of the third device die , and wherein the first isolation region and the second isolation region form a distinguishable interface.. Therefore it would have been obvious to one of ordinary skill in the art, at the time of applicant’s invention to combine Yu’s teachings to claim 1 of ‘9599 semiconductor device to stack dies in a vertical direction to provide a higher density with smaller form factors and allow for increased performance and lower power consumption (Yu, [0004]). Regarding claim 2: Claim 2 of ‘9599 teaches all the limitations. Regarding claim 11: Claims 10 and 12 of ‘9599 teaches all the limitations. Regarding claim 12: Claim 13 of ‘9599 teaches all the limitations. Regarding claim 13: Claim 11 of ‘9599 teaches all the limitations. Regarding claim 18: Claim 16 of ‘9599 teaches all the limitations. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 5. Claims 1-4, 9, 11-16, 18-23 are rejected under 35 U.S.C. 103 as being obvious over Yu et al (US 2015/0318246 A1) in view of Kim et al. (US PGPUB 2018/0006006 A1) Regarding claims 1, 21, 23: Yu teaches in Fig. 46 about a package comprising: PNG media_image1.png 681 1042 media_image1.png Greyscale PNG media_image2.png 643 1282 media_image2.png Greyscale a first device die; a second device die over and bonded to the first device die through both of fusion bonds [0015] and metal-to-metal direct bonds; a first isolation region encapsulating the first device die therein, wherein first edges (as marked) of the first isolation region are vertically aligned to respective second edges (as marked) of the second device die; a third device die under and bonded to the first device die through both of fusion bonds and metal-to-metal direct bonds; and a second isolation region (as marked above) encapsulating the first device die and the first isolation region therein (for clarification, claim limitation is “region” and does not say different type of isolation regions or different isolating materials in first and second isolation regions and therefore in BRI two isolations regions are interpreted as the first and second isolation region) , wherein third edges (as marked) of the second isolation region are vertically aligned to respective fourth edges (as marked) of the third device die and wherein the first isolation region and the second isolation region form a distinguishable interface (As marked, 4102 is molding compound and 3016 is isolation material which are two different materials type). Yu does not explicitly show metal-to-metal direct bonds. However Yu teaches in [0019] die and wafer can be bonded by metal-to-metal-bonding and Kim teaches in Fig. 6-7 how different dies are connected by metal-to-metal bonding using the connection pads. Therefore it would have been obvious to one of ordinary skill in the art, at the time of applicant’s invention to combine Kim’s teachings to Yu’s semiconductor device to stack dies in a vertical direction to have more miniaturized and multi-functioned. compact packages to save space (Kim, [0003]). The examiner had to assume what the product would be by the process claimed. For example the claim limitations that the bonding was done by metal-to-metal direct bonds” was not considered to have full patentable weight. A “product by process” claim is directed to the product per se, no matter how actually made, MPEP 2113 “Product-by-Process Claims,” In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wertheim, 191 USPQ 90; In re Marosi et al, 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product per se which must be determined in a “product by process” claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in “product by process” claims or not. Yu teaches the first device die, the second device die, the third device die are bonded and therefore what method is used for bonding has not given patentable weight. Applicant’s arguments on 09/09/2026 on pages 10-12 “the asserted first outer edge is shifted laterally toward right relative to the asserted second outer edge. Therefore, Examiner's interpretation of Yu does not support the rejection” are not found persuasive in view of marked up interpretation as shown below. PNG media_image3.png 643 1282 media_image3.png Greyscale Regarding claim 2: Yu teaches as marked above a first through-via penetrating through the first isolation region, wherein the first through-via electrically connects the second device die to the third device die. Regarding claims 3, 20: Yu teaches as marked above a second through-via penetrating through the second isolation region and electrically connected to the third device die, wherein a first top width of the first through-via is smaller than a first bottom width of the first through-via, and a second top width of the second through-via is greater than a second bottom width of the second through-via (TSV’s are tapered shape). Regarding claim 4: Yu teaches in Fig. 46 wherein each of the first isolation region and the second isolation region comprises: a dielectric liner (the spacers for example 3502 in Fig. 37) contacting the first device die and the second device die, respectively; and a dielectric region (3106/3016 etc.) on the dielectric liner. Regarding claim 9: Yu teaches in [0017] wherein each of the first device die, the second device die, the third device die comprises: a semiconductor substrate; and through-substrate vias penetrating through the semiconductor substrate. Regarding claim 11: As explained in claims 1-3 above, Yu in view of Kim teaches all the limitations. PNG media_image4.png 643 1282 media_image4.png Greyscale Regarding claim 12: Kim teaches in Fig. 13 a fourth device die bonded to the second package, wherein the fourth device die is on a backside of the second device die, and the fourth device die is electrically connected to the third device die through the second through-via. Regarding claim 13: As explained in claim 4, Yu teaches in Fig. 46 wherein a first dielectric layer in the first device die is physically joined to a second dielectric layer in the second device die, and a first bond pad in the first device die is physically joined to a second bond pad in the second device die. Regarding claim 14: As explained in claim 3, Yu teaches in Fig. 46 wherein the first through-via has a first top end and a first bottom end wider than the first top end, and the second through-via has a second top end and a second bottom end narrower than the second top end. Regarding claim 15: As explained in claims 3, 9, Yu teaches in Fig. 46 wherein the first device die comprises: a first semiconductor substrate; and a third through-via penetrating through the first semiconductor substrate, wherein the third through-via has a third top end and a third bottom end narrower than the third top end. Regarding claim 16: As explained in claims 3, 9, Yu teaches in Fig. 46 wherein the second device die comprises: a second semiconductor substrate; and a fourth through-via penetrating through the second semiconductor substrate, wherein the fourth through-via has a fourth top end and a fourth bottom end wider than the fourth top end. Regarding claims 18, 23: As explained in claims 1-3, 9, Yu in view of Kim teaches all the limitations. (For clarification, as marked below PNG media_image2.png 643 1282 media_image2.png Greyscale Regarding claim 19: As explained above in claims 1-3, 9 Yu in view of Kim teaches all the limitations. Allowable Subject Matter Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The limitation allowable is “a third isolation region encapsulating the first device die, the second device die, the third device die, the first isolation region, and the second isolation region therein, wherein fifth edges of the fourth device die are vertically aligned to sixth edges of the third isolation region” in combination with other limitations as a whole. 6 is also allowable being dependent on claim 5. Claim 17 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The limitation allowable is “wherein a first edge of the first gap filling material contacts a second edge of the second gap filling material to form a the vertical interface is perpendicular to a horizontal interface between the first device die and the second device die, and the vertical interface is flush with a respective edge of the second device die.” in combination with other limitations as a whole. Response to Arguments Applicant's arguments filed 04/14/2025 have been fully considered but they are not persuasive. PNG media_image3.png 643 1282 media_image3.png Greyscale Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED SHAMSUZZAMAN whose telephone number is (571)270-1839. The examiner can normally be reached Monday-Friday 7 am -4 pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached at 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Mohammed Shamsuzzaman/Primary Examiner, Art Unit 2897
Read full office action

Prosecution Timeline

Jul 31, 2023
Application Filed
Jan 07, 2025
Non-Final Rejection — §103, §112, §DP
Apr 14, 2025
Response Filed
Jul 07, 2025
Final Rejection — §103, §112, §DP
Sep 09, 2025
Response after Non-Final Action
Sep 18, 2025
Request for Continued Examination
Oct 01, 2025
Response after Non-Final Action
Feb 18, 2026
Non-Final Rejection — §103, §112, §DP (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
81%
Grant Probability
99%
With Interview (+56.6%)
2y 7m
Median Time to Grant
High
PTA Risk
Based on 892 resolved cases by this examiner. Grant probability derived from career allow rate.

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