DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant's response to the Office Non-Final Action filed on 9/10/2026 is acknowledged.
Applicant amended claims 1 and 17.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7, 8, and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Frougier et al. (US 10192867 B1) (hereafter Frougier), in view of Chanemougame et al. (US 10090193 B1) (hereafter Chanemougame).
Regarding claim 1, Frougier discloses a semiconductor device, comprising:
a first transistor 820 (Fig. 17, Bridging paragraph from Col. 8 to Col. 9) disposed over a substrate (element number is not shown in Fig. 17 but see 320 in Fig. 2), wherein the first transistor 820 (Fig. 17) comprises first conductive segments (horizontal portion of 1810 of 820 in Fig. 17) that correspond to drain (element number is not shown in Fig. 17 but see D1 of 820 in Fig. 7) and source terminals (element number is not shown in Fig. 17 but see S1 of 820 in Fig. 7) of the first transistor 820 (Fig. 17) and extend in a first direction (vertical direction in Fig. 17), on a first layer (element number is not shown in Fig. 17 but see 330 in Fig. 2);
a second transistor 1330 (Fig. 17, Bridging paragraph from Col. 8 to Col. 9) disposed over the first transistor 820 (Fig. 17), wherein the second transistor 1330 (Fig. 17) comprises second conductive segments (horizontal portion of 1810 of 1330 in Fig. 17) that correspond to drain (element number is not shown in Fig. 17 but see D2 of 1330 in Fig. 12) and source terminals (element number is not shown in Fig. 17 but see S2 of 1330 in Fig. 7) of the second transistor 1330 (Fig. 17) and extend above a second layer (element number is not shown in Fig. 17 but see 810 in Fig. 13) along the first direction (vertical direction in Fig. 17), wherein the second layer (element number is not shown in Fig. 17 but see 810 in Fig. 13) is above the first layer (element number is not shown in Fig. 17 but see 330 in Fig. 2); and
a conductive trace (1710 (Fig. 16) and vertical portion of 1810 (Fig. 17)) extending on a third layer (element number is not shown in Fig. 17 but see 312a in Fig. 6), wherein the first (element number is not shown in Fig. 17 but see 330 in Fig. 2) to third layers (element number is not shown in Fig. 17 but see 312a in Fig. 6) are separated from each other in the first direction (vertical direction in Fig. 17), and the third layer (element number is not shown in Fig. 17 but see 312a in Fig. 6) is interposed between the first (element number is not shown in Fig. 17 but see 330 in Fig. 2) and second layers (element number is not shown in Fig. 17 but see 810 in Fig. 13),
wherein the first conductive segments (horizontal portion of 1810 of 820 in Fig. 17), the second conductive segments (horizontal portion of 1810 of 1330 in Fig. 17), and the conductive trace (1710 (Fig. 16) and vertical portion of 1810 (Fig. 17)) overlap (see Fig. 17, wherein vertical portion of 1810 overlaps horizontal portion of 1810 of 820 and horizontal portion of 1810 of 1330) in a layout view,
wherein the conductive trace (1710 (Fig. 16) and vertical portion of 1810 (Fig. 17)), the first conductive segments (horizontal portion of 1810 of 820 in Fig. 17), and the second conductive segments (horizontal portion of 1810 of 1330 in Fig. 17) include substantially the same material (see 1810 in Fig. 17).
Frougier does not disclose the conductive trace is a rectangle trace between the first transistor and the second transistor.
Chanemougame discloses the conductive trace 53.1(1) (Fig. 2E, first paragraph in Col. 11) is a rectangle trace between the first transistor 110 (Fig. 2E, second paragraph in Col. 9) and the second transistor 120 (Fig. 2E, second paragraph in Col. 9).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Frougier to form the conductive trace is a rectangle trace between the first transistor and the second transistor, as taught by Chanemougame, since within a stacked pair (Chanemougame, second paragraph in Col. 2) of FETs, an irregular-shaped buried interconnect electrically connects source/drain regions that are on opposite sides of the shared gate and at different levels.
Regarding claim 2, Frougier further discloses the semiconductor device of claim 1, wherein the conductive trace (1710 (Fig. 16) and vertical portion of 1810 (Fig. 17)) is electrically connected (see Y of Fig. 17) to at least one of the first conductive segments (horizontal portion of 1810 of 820 in Fig. 17).
Regarding claim 3, Frougier further discloses the semiconductor device of claim 1, wherein the second conductive segments (horizontal portion of 1810 of 1330 in Fig. 17) extend along the first direction (vertical direction in Fig. 17) to pass through a first active area (element number is not shown in Fig. 17 but see S2 and D2 in Fig. 7), wherein the conductive trace (1710 (Fig. 16) and vertical portion of 1810 (Fig. 17)) connects the second conductive segments (horizontal portion of 1810 of 1330 in Fig. 17).
Regarding claim 4, Frougier (utilized different elements for conductive trace, first conductive segments, and second conductive segments as applied in claim 1 in the above) for discloses a semiconductor device, comprising:
a first transistor 820 (Fig. 17, Bridging paragraph from Col. 8 to Col. 9) disposed over a substrate (element number is not shown in Fig. 17 but see 320 in Fig. 2), wherein the first transistor 820 (Fig. 17) comprises first conductive segments (1610, 1710, and horizontal portion of 1810 of 820 in Fig. 17) that correspond to drain (element number is not shown in Fig. 17 but see D1 of 820 in Fig. 7) and source terminals (element number is not shown in Fig. 17 but see S1 of 820 in Fig. 7) of the first transistor 820 (Fig. 17) and extend in a first direction (vertical direction in Fig. 17), on a first layer (element number is not shown in Fig. 17 but see 330 in Fig. 2);
a second transistor 1330 (Fig. 17, Bridging paragraph from Col. 8 to Col. 9) disposed over the first transistor 820 (Fig. 17), wherein the second transistor 1330 (Fig. 17) comprises second conductive segments (1610, 1710, and horizontal portion of 1810 of 1330 in Fig. 17) that correspond to drain (element number is not shown in Fig. 17 but see D2 of 1330 in Fig. 12) and source terminals (element number is not shown in Fig. 17 but see S2 of 1330 in Fig. 7) of the second transistor 1330 (Fig. 17) and extend above a second layer (element number is not shown in Fig. 17 but see 810 in Fig. 13) along the first direction (vertical direction in Fig. 17), wherein the second layer (element number is not shown in Fig. 17 but see 810 in Fig. 13) is above the first layer (element number is not shown in Fig. 17 but see 330 in Fig. 2); and
a conductive trace (vertical portion of 1810 in Fig. 17, Col. 10, Line 2) extending on a third layer (element number is not shown in Fig. 17 but see 312a in Fig. 6), wherein the first (element number is not shown in Fig. 17 but see 330 in Fig. 2) to third layers (element number is not shown in Fig. 17 but see 312a in Fig. 6) are separated from each other in the first direction (vertical direction in Fig. 17), and the third layer (element number is not shown in Fig. 17 but see 312a in Fig. 6) is interposed between the first (element number is not shown in Fig. 17 but see 330 in Fig. 2) and second layers (element number is not shown in Fig. 17 but see 810 in Fig. 13),
wherein the first conductive segments (1610, 1710, and horizontal portion of 1810 of 820 in Fig. 17), the second conductive segments (1610, 1710, and horizontal portion of 1810 of 1330 in Fig. 17), and the conductive trace (vertical portion of 1810 in Fig. 17) overlap (see Fig. 17, wherein vertical portion of 1810 overlaps horizontal portion of 1810 of 820 and horizontal portion of 1810 of 1330) in a layout view,
wherein the conductive trace (vertical portion of 1810 in Fig. 17), the first conductive segments (1610, 1710, and horizontal portion of 1810 of 820 in Fig. 17), and the second conductive segments (1610, 1710, and horizontal portion of 1810 of 1330 in Fig. 17) include substantially the same material;
wherein first (element number is not shown in Fig. 17 but see S1 and D1 in Fig. 7) and second active areas (element number is not shown in Fig. 17 but see S2 and D2 in Fig. 7) extending in a second direction (horizontal direction in Fig. 17) different from the first direction (vertical direction in Fig. 17), the first active area (element number is not shown in Fig. 17 but see S1 and D1 in Fig. 7) contacting the first conductive segments (1610, 1710, and horizontal portion of 1810 of 820 in Fig. 17) and the second active area (element number is not shown in Fig. 17 but see S2 and D2 in Fig. 7) contacting the second conductive segments (1610, 1710, and horizontal portion of 1810 of 1330 in Fig. 17); and first (element number is not shown in Fig. 17 but see left 1310 in Fig. 12) and second gates (element number is not shown in Fig. 17 but see right 1310 in Fig. 12) extending in a third direction (stacking direction in Fig. 17) different from the first (vertical direction in Fig. 17) and second directions (horizontal direction in Fig. 17), wherein the first gate (element number is not shown in Fig. 17 but see left 1310 in Fig. 12) is interposed between the first conductive segments (1610, 1710, and horizontal portion of 1810 of 820 in Fig. 17) and the second gate (element number is not shown in Fig. 17 but see right 1310 in Fig. 12) is interposed between the second conductive segments (1610, 1710, and horizontal portion of 1810 of 1330 in Fig. 17),
wherein the conductive trace (vertical portion of 1810 in Fig. 17) passes between the first (element number is not shown in Fig. 17 but see left 1310 in Fig. 12) and second gates (element number is not shown in Fig. 17 but see right 1310 in Fig. 12).
Frougier does not disclose the conductive trace is a rectangle trace between the first transistor and the second transistor.
Chanemougame discloses the conductive trace 53.1(1) (Fig. 2E, first paragraph in Col. 11) is a rectangle trace between the first transistor 110 (Fig. 2E, second paragraph in Col. 9) and the second transistor 120 (Fig. 2E, second paragraph in Col. 9).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Frougier to form the conductive trace is a rectangle trace between the first transistor and the second transistor, as taught by Chanemougame, since within a stacked pair (Chanemougame, second paragraph in Col. 2) of FETs, an irregular-shaped buried interconnect electrically connects source/drain regions that are on opposite sides of the shared gate and at different levels.
Regarding claim 5, Frougier further discloses the semiconductor device of claim 4, wherein the conductive trace (vertical portion of 1810 in Fig. 17) contacts the second conductive segments (1610, 1710, and horizontal portion of 1810 of 1330 in Fig. 17).
Regarding claim 7, Frougier further discloses the semiconductor device of claim 1, wherein first (element number is not shown in Fig. 17 but see 1310 of left portion of 820 in Fig. 12) and second gates (element number is not shown in Fig. 17 but see 1310 of left portion of 1330 in Fig. 12) extending in a second direction (horizontal direction in Fig. 17) different from the first direction (vertical direction in Fig. 17), wherein the first gate (element number is not shown in Fig. 17 but see 1310 of left portion of 820 in Fig. 12) is interposed between the first conductive segments (horizontal portion of 1810 of 820 in Fig. 17) and the second gate (element number is not shown in Fig. 17 but see 1310 of left portion of 1330 in Fig. 12) is interposed between the second conductive segments (horizontal portion of 1810 of 1330 in Fig. 17), wherein the conductive trace (1710 (Fig. 16) and vertical portion of 1810 (Fig. 17)) is arranged interposed between the first (horizontal portion of 1810 of 820 in Fig. 17) and second conductive segments (horizontal portion of 1810 of 1330 in Fig. 17) and the first (element number is not shown in Fig. 17 but see 1310 of left portion of 820 in Fig. 12) and second gates (element number is not shown in Fig. 17 but see 1310 of left portion of 1330 in Fig. 12).
Regarding claim 8, Frougier further discloses the semiconductor device of claim 1, wherein a gate (element number is not shown in Fig. 17 but see 1310 in Fig. 12) extending in the first direction (vertical direction in Fig. 17) and arranged between the first (horizontal portion of 1810 of 820 in Fig. 17) and second conductive segments (horizontal portion of 1810 of 1330 in Fig. 17), wherein the conductive trace (1710 (Fig. 16) and vertical portion of 1810 (Fig. 17)) passes through the gate (element number is not shown in Fig. 17 but see 1310 in Fig. 12).
Regarding claim 17, Frougier discloses a method, comprising:
forming a stack of transistors (820 and 1330 in Fig. 17, Bridging paragraph from Col. 8 to Col. 9) along a vertical direction (vertical direction in Fig. 17), comprising:
forming a first set of contacts (horizontal portion of 1810 of 820 in Fig. 7) that are on a first active area (element number is not shown in Fig. 17 but see S1 and D1 in Fig. 7) and have a height smaller than a distance between first (element number is not shown in Fig. 17 but see 330 in Fig. 2) and second layers (element number is not shown in Fig. 17 but see 1110 in Fig. 13) of a semiconductor device; and
forming a second set of contacts (horizontal portion of 1810 of 1330 in Fig. 7) on a second active area (element number is not shown in Fig. 17 but see S2 and D2 in Fig. 12) different from the first active area (element number is not shown in Fig. 17 but see S1 and D1 in Fig. 7); and
forming a conductive trace (1710 (Fig. 16) and vertical portion of 1810 (Fig. 17)) extending in a horizontal direction (horizontal direction in Fig. 17) in the second layer (element number is not shown in Fig. 17 but see 1110 in Fig. 13) disposed between the first (horizontal portion of 1810 of 820 in Fig. 7) and second sets of contacts (horizontal portion of 1810 of 1330 in Fig. 7).,
wherein the conductive trace (1710 (Fig. 16) and vertical portion of 1810 (Fig. 17)), the first set of contacts (horizontal portion of 1810 of 820 in Fig. 7), and the second set of contacts (horizontal portion of 1810 of 1330 in Fig. 7) include substantially the same material (see 1810 in Fig. 17).
Frougier does not disclose the conductive trace is a rectangle trace between the stack of transistors.
Chanemougame discloses the conductive trace 53.1(1) (Fig. 2E, first paragraph in Col. 11) is a rectangle trace between the stack of transistors (110 and 120 in Fig. 2E, second paragraph in Col. 9).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Frougier to form the conductive trace is a rectangle trace between the stack of transistors, as taught by Chanemougame, since within a stacked pair (Chanemougame, second paragraph in Col. 2) of FETs, an irregular-shaped buried interconnect electrically connects source/drain regions that are on opposite sides of the shared gate and at different levels.
Regarding claim 18, Frougier further discloses the method of claim 17, wherein the second set of contacts (horizontal portion of 1810 of 1330 in Fig. 7) extend in the vertical direction (vertical direction in Fig. 17) to contact the conductive trace (1710 (Fig. 16) and vertical portion of 1810 (Fig. 17)).
Regarding claim 19, Frougier further discloses the method of claim 17, further comprising: forming a gate structure (element number is not shown in Fig. 17 but see 1310 in Fig. 12) of the stack of transistors (820 and 1330 in Fig. 17) disposed between the first (horizontal portion of 1810 of 820 in Fig. 7) and second set (horizontal portion of 1810 of 1330 in Fig. 7), wherein the conductive trace (1710 (Fig. 16) and vertical portion of 1810 (Fig. 17)) passes through the gate structure (element number is not shown in Fig. 17 but see 1310 in Fig. 12).
Regarding claim 20, Frougier further discloses the method of claim 17, further comprising: forming a first gate structure (element number is not shown in Fig. 17 but see 1310 of 820 in Fig. 12) disposed between the first set of contacts (horizontal portion of 1810 of 820 in Fig. 7); and forming a second gate structure (element number is not shown in Fig. 17 but see 1310 of 1330 in Fig. 12) disposed between the second set of contacts (horizontal portion of 1810 of 1330 in Fig. 7), wherein the first (element number is not shown in Fig. 17 but see 1310 of 820 in Fig. 12) and second gate structures (element number is not shown in Fig. 17 but see 1310 of 1330 in Fig. 12) overlap with each other in a layout view and are separated from each other in the vertical direction (vertical direction in Fig. 17).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Frougier in view of Chanemougame as applied to claim 4 above, and further in view of Xie et al. (US 9847390 B1) (hereafter Xie).
Regarding claim 6, Frougier in view of Chanemougame discloses the semiconductor device of claim 4, however Frougier and Chanemougame do not disclose a third gate passing through the first and second active areas, wherein the conductive trace terminates beside the third gate along the second direction.
Xie discloses a third gate 116 (Fig. 10B, second paragraph in Col. 5) passing through the first (left 102 in Fig. 10B, second paragraph in Col. 5) and second active areas (right 102 in Fig. 10B, second paragraph in Col. 5), wherein the conductive trace 602 (Fig. 10A) terminates beside the third gate 116 (Fig. 10B) along the second direction (horizontal direction in Fig. 10B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Frougier in view of Chanemougame to form a third gate passing through the first and second active areas, wherein the conductive trace terminates beside the third gate along the second direction, as taught by Xie, since Metal gate 116 (Xie, Fig. 10B, Bridging paragraph from Col. 8 to Col. 9) may be disposed on nanosheet stack 104 such that a wrap-around contact (WAC) (Xie, fourth paragraph in Col. 1) may be formed over the entire outer surface of source/drain regions in order to reduce resistance in the nanosheet FET.
Allowable Subject Matter
Claims 9-16 are allowed. The following is an examiner’s statement of reasons for allowance: a closest prior art, Frougier et al. (US 10192867 B1), discloses a conductive trace 1810 (Fig. 17, Col. 10, Line 2) above the first (element number is not shown in Fig. 17 but see 1610 (Fig. 15) contacting S1 (Fig. 7) of left portion of 820) and second conductive segments (element number is not shown in Fig. 17 but see 1610 (Fig. 15) contacting D1 (Fig. 7) of left portion of 820) and overlapping (see Fig. 17, wherein 1810 vertically overlaps S1 and D1 (Fig. 7), S2 (Fig. 12), and 1610 (Fig. 15) of left portion of 820; and see Figs. 1 and 17, wherein Fig. 17 is the cross-section view of the layout view of Fig. 1) the first (element number is not shown in Fig. 17 but see S1 of left portion of 820 in Fig. 7) and second portions (element number is not shown in Fig. 17 but see D1 of left portion of 820 in Fig. 7) of the first active area (element number is not shown in Fig. 17 but see S1 and D1 in Fig. 7), the first portion (element number is not shown in Fig. 17 but see S2 of left portion of 820 in Fig. 12) of the second active area (element number is not shown in Fig. 17 but see S2 and D2 in Fig. 12), and the first (element number is not shown in Fig. 17 but see 1610 (Fig. 15) contacting S1 (Fig. 7) of left portion of 820, Col. 9, Line 45) to third conductive segments (element number is not shown in Fig. 17 but see 1610 (Fig. 15) contacting S2 (Fig. 12) of left portion of 820) in a layout view but fails to disclose a conductive trace extending continuously in the first direction from the first conductive segment to the second conductive segment; and wherein the conductive trace, the first conductive segment, and the second conductive segment include substantially the same material. Additionally, the prior art does not teach or suggest a semiconductor device, comprising: a conductive trace extending continuously in the first direction from the first conductive segment to the second conductive segment; and wherein the conductive trace, the first conductive segment, and the second conductive segment include substantially the same material in combination with other elements of claim 9.
A closest prior art, Frougier et al. (US 10192867 B1), discloses a semiconductor device, comprising: a first portion (element number is not shown in Fig. 17 but see S1 of left portion of 820 in Fig. 7, Col. 7, Line 57) of a first active area (element number is not shown in Fig. 17 but see S1 and D1 in Fig. 7) in contact with a first conductive segment (element number is not shown in Fig. 17 but see 1610 (Fig. 15) contacting S1 of left portion of 820 in Fig. 7, Col. 9, Line 45) and a second portion (element number is not shown in Fig. 17 but see D1 of left portion of 820 in Fig. 7, Col. 7, Line 60) of the first active area (element number is not shown in Fig. 17 but see S1 and D1 in Fig. 7) in contact with a second conductive segment (element number is not shown in Fig. 17 but see 1610 (Fig. 15) contacting D1 (Fig. 7) of left portion of 820, Col. 9, Line 45), wherein the first (element number is not shown in Fig. 17 but see 1610 (Fig. 15) contacting S1 (Fig. 7) of left portion of 820) and second conductive segments (element number is not shown in Fig. 17 but see 1610 (Fig. 15) contacting D1 (Fig. 7) of left portion of 820) are separated by a first gate structure (element number is not shown in Fig. 17 but see 1310 of left portion of 820 in Fig. 12) along a first direction (horizontal direction in Fig. 17); a first portion (element number is not shown in Fig. 17 but see S2 of left portion of 820 in Fig. 12) of a second active area (element number is not shown in Fig. 17 but see S2 and D2 in Fig. 12) in contact with a third conductive segment (element number is not shown in Fig. 17 but see 1610 (Fig. 15) contacting S2 (Fig. 12) of left portion of 820, Col. 9, Line 45), wherein the first portion (element number is not shown in Fig. 17 but see S1 of left portion of 820 in Fig. 7) of the first active area (element number is not shown in Fig. 17 but see S1 and D1 in Fig. 7) is below and isolated from the first portion (element number is not shown in Fig. 17 but see S2 of left portion of 820 in Fig. 12) of the second active area (element number is not shown in Fig. 17 but see S2 and D2 in Fig. 12) along a second direction (vertical direction in Fig. 17); and a conductive trace 1810 (Fig. 17, Col. 10, Line 2) above the first (element number is not shown in Fig. 17 but see 1610 (Fig. 15) contacting S1 (Fig. 7) of left portion of 820) and second conductive segments (element number is not shown in Fig. 17 but see 1610 (Fig. 15) contacting D1 (Fig. 7) of left portion of 820) and overlapping (see Fig. 17, wherein 1810 vertically overlaps S1 and D1 (Fig. 7), S2 (Fig. 12), and 1610 (Fig. 15) of left portion of 820; and see Figs. 1 and 17, wherein Fig. 17 is the cross-section view of the layout view of Fig. 1) the first (element number is not shown in Fig. 17 but see S1 of left portion of 820 in Fig. 7) and second portions (element number is not shown in Fig. 17 but see D1 of left portion of 820 in Fig. 7) of the first active area (element number is not shown in Fig. 17 but see S1 and D1 in Fig. 7), the first portion (element number is not shown in Fig. 17 but see S2 of left portion of 820 in Fig. 12) of the second active area (element number is not shown in Fig. 17 but see S2 and D2 in Fig. 12), and the first (element number is not shown in Fig. 17 but see 1610 (Fig. 15) contacting S1 (Fig. 7) of left portion of 820, Col. 9, Line 45) to third conductive segments (element number is not shown in Fig. 17 but see 1610 (Fig. 15) contacting S2 (Fig. 12) of left portion of 820) in a layout view but fails to teach a conductive trace extending continuously in the first direction from the first conductive segment to the second conductive segment; and wherein the conductive trace, the first conductive segment, and the second conductive segment include substantially the same material as the context of claim 9. The other allowed claims each depend from one of these claims, and each is allowable for the same reasons as the claim from which it depends. Claims 10-16 depend on claim 1.
Response to Arguments
1. Applicant's arguments filed 6/2/2026 have been fully considered.
2. Applicant's arguments with respect to claims 1-8 and 17-20 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/L.B.K/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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