DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to because Fig. 2E: The third cell pin on Row2 has been identified as 260(2) instead of 260(3), and the second pin is not identified, as it should be the pin 260(2).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered, and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
(Text within parentheses is either a missing or a corrected information to character(s) in bold.)
[0010] Specific examples of components, materials, values, steps, operations, materials,() arrangements, or the like, are described below to simplify the present disclosure.
[0013] … Failure to satisfy a design rule sometimes results in a process-related problem such as shorting between me(t)al lines due to optical proximity, in some instances.
[0020] Referring to FIG. 1 and FIG 2A, method 100 includes operation 102 in which a plurality of first conductive lines 220-228 for a plurality of first cells 202 having a first cell height (CHI ) and a plurality of second conductive lines for 232-236 for a plurality of second cells 204 having a second cell height CHI(2) less than the first cell height CH2(1) are placed along corresponding horizontal routing tracks of a plurality of horizontal routing tracks HT1-HT21; first and second cells 202 and 204 are arranged into a plurality of rows. FIG. 2A is a layout diagram 200A of an IC after placing a plurality of first conductive lines 220-228 and a plurality of second conductive lines for 232(0)-236(4) along corresponding horizontal routing tracks of a plurality of horizontal routing tracks HT1-HT21, in accordance with some embodiments.
[0026] … In some embodiments, top boundary 212A of each first cell 202 is defined in the middle of a corresponding power rail 206a or 206c, and bottom boundary 212B of each first cell 202 is defined in the middle of a corresponding power rail 206b or 206b(d).
[0027] … Each of second cells 204 includes a plurality of second conductive lines 232(0), 234(2) and 236(4) within top and bottom boundaries 214A, 214B thereof. Second conductive lines 232(0), 234(2) and 236(4) in each of second cells 204 are arranged substantially parallel to one another along the X direction and aligned with corresponding horizontal routing tracks, e.g., HT8-HT10 and HT18-20.
[0028] In some embodiments, power rails 206a-206e and conductive lines 220-228 and 232(0)- 236(4) are formed within a first metal layer, i.e., M1 layer that is close to a substrate where active components of cells 202 and 204, e.g., transistors or the like, are formed. During a routing stage, power rails 206a-e and conductive lines 220-228 and 232(0)-236(4) are laid out with respect to the corresponding horizontal routing tracks HT1-HT21 by the APR tool.
[0035] … Via placement points 250 correspond to possible locations for placing vias 262 (FIG. 2E) that electrically connect second conductive lines 232(0)-236(4) in the M1 layer to second cell pins 260 (FIG. 2D) to be formed in the overlying M2 layer, thereby enabling device signal transmission. Via placement points 250 are located at intersections of second conductive lines 232(0)-236(4) and corresponding vertical routing tracks in vertical routing tracks VT1-VH2O. For example, for the leftmost second cell 204 in Row 2, two exemplary via placement points 250(1) and 250(2) are identified as possible locations for placing vias over a second(first) conductive line 232(0) laid on horizontal routing track HT8, two exemplary via placement points 250(3) and 250(4) are identified as possible locations for placing vias over a second conductive line 234(2) laid on horizontal routing track HT9, and two exemplary via placement points 250(5) and 250(6) are identified as possible locations for placing vias over a second(third) conductive line 236(4) laid on horizontal routing track HT9(10).
[0037] … In other embodiments, second cell pin 2602()(2) can be formed to have an end terminated within the leftmost second cell 204 in Row 2 and an opposite end extending across a corresponding boundary 214A or 214B and onto a portion of vertical routing track VT5 in Row 1 or onto a portion of vertical routing track VT5 in Row 3 because both portions of vertical routing track VT5 in Row 1 and Row 3 are unoccupied.
[0039] Referring to FIG. 1 and FIG. 2E, method 100 proceeds to operation 110 in which a plurality of second vias 262 is placed to couple the plurality of second cell pins 260 to the plurality of second conductive lines 232(0)-236(4). FIG. 2E is a layout diagram 200E of layout diagram 200D after placing a plurality of second vias 262 to couple the plurality of second cell pins 260 to the plurality of second conductive lines 232(0)-236(4), in accordance with some embodiments.
[0040] Second cell pins 260 are electrically coupled to corresponding underlying second conductive lines 232(0)-236(4) through second vias 262.
[0042] …Each of first and second cell pins 240 and 260 can be elongated to any length as long as the minimum end-to-end spacing requirement is satisfied between facing ends of adjacent first cell pin 240 and second cell pin 260 on the same vertical routing track VT1-VT3(2)0 after pin elongation.
[0043] … Method 300 is describe(d) below in conjunction with FIGS. 4A-4C where various stages of generating layout diagram 200F are illustrated. Unless specified otherwise, components in FIGS. 4A-4C that are essentially the same as their like components in FIGS. 2A-2F, are denoted by like reference numerals shown in FIGS. 2A-2F.
[0045] Referring to FIG. 3, method 300 includes operation 302 in which a plurality of first conductive lines 220-228 for a plurality of first cells 202 of a first cell height and a plurality of second conductive lines for 232(0)-236(4) for a plurality of second cell 204 of a second cell height CH1 less than the first cell height CH2 are placed along corresponding horizontal routing tracks HT1- HT21 of a routing grid;
[0046] … First via placement points 270 are located at intersections of first conductive lines 220-222()8 and corresponding vertical routing tracks in vertical routing tracks VT1-VT20.
[0048] Likewise, second via placement points 250 correspond to possible locations for placing second vias 262 (FIG. 4C) configured to electrically connect second conductive lines 232(0)-236(4) in the M1 layer to second cell pins 260 (FIG. 4B) to be formed in the overlying M2 layer, thereby enabling signal transmission for second cells 204. Second via placement points 250 are located at intersections of second conductive lines 232(0)-236(4) and corresponding vertical routing tracks in vertical routing tracks VT1-VT20.
[0053] Referring to FIG. 3 and FIG. 4C, method 300 proceeds to operation 308 in which a plurality of first vias 242 is placed to couple the plurality of first cell pins 240 to the plurality of first conductive lines 220-228 and a plurality of second vias 262 is placed to couple the plurality of second cell pins 260 to the plurality of second conductive lines 232(0)-236(4). FIG. 4C is a layout diagram 400C of layout diagram 400B after placing a plurality of first vias 242 to couple the plurality of first cell pins 240 to the plurality of first conductive lines and placing a plurality of second vias 262 to couple the plurality of second cell pins 260 to the plurality of second conductive lines 232(0)-236(4), in accordance with some embodiments.
[0054] … Likewise, second cell pins 260 are electrically coupled to corresponding underlying second conductive lines 232(0)-236(4) through second vias 262.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4-5, 7-8, and 18-20 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Deepak D. Sherlekar et. al. (US 20140229908 A1) hereinafter Sherlekar-908.
Regarding claim 1
Sherlekar discloses
A method of generating a layout diagram for an integrated circuit, the method comprising
(Sherlekar-908, p. 2, [0023] “FIG. 8 illustrates one embodiment of a method for generating a layout for an integrated circuit.”)
arranging a plurality of cells in the layout diagram, wherein each cell of the plurality of cells comprises a first power rail along a first boundary and a second power rail along a second boundary, and the first boundary is spaced from the second boundary in a first direction
(Sherlekar-908, p. 1, [0006] “During the process of designing an integrated circuit, a designer may select particular cells from a library of cells and use them in a design.”)
(Sherlekar-908, p. 1, [0011] “One embodiment of the non-transitory computer readable medium stores instructions for receiving a plurality of cells and generating a layout for an integrated circuit from cells. At least one of the cells includes a first metal wire extending along a first boundary of the cell for carrying a first power supply voltage. A second metal wire extends along an interior of the cell for carrying a second power supply voltage. A cell pin corresponding to one of an input signal or output signal of the cell is located between the second metal wire and a second boundary that is opposite from the first boundary.”)
(Sherlekar-908, p. 4, [0051] “… As used herein, a power rail is defined as a wire structure that is primarily used to carry a power supply voltage, such as VDD, VSS, ground, etc. to the cells of an integrated circuit.”)
and placing a plurality of cell pins over a plurality of selected via placement points in a first cell of the plurality of cells in accordance with a design rule, wherein a first cell pin of the plurality of cell pins has a first end spaced from both the first power rail and the second power rail in the first direction.
(Sherlekar-908, p. 1, [0010] “… At least one cell in integrated circuit architecture includes a first metal wire extending along a first boundary of the cell for carrying a first power supply voltage. A second metal wire extends along an interior of the cell for carrying a second power supply voltage. A cell pin corresponding to an input signal or output signal of the cell is located between the second metal wire and a second boundary that is opposite from the first boundary. By configuring the power supply voltages and cell pins in this manner, the layout for the integrated circuit is more compact while still complying with various design rules.”)
(Sherlekar-908, p. 1, [0008] “… Routing in an IC design is accomplished through routing elements, such as traces in one or more metal layers. Each metal layer is separated from other metal layers by insulating layers, and vias connect one metal layer to another. These routing elements perform at least two functions: they connect individual transistors that make up a cell, and they connect cells to each other globally (i.e., on a chip-level) to implement the desired functionality of the integrated circuit.”)
(Sherlekar-908, p. 1, [0027] “… A cell pin carrying an input or output signal of the predefined cell, or an internal connection between transistors of the predefined cell, is positioned outside of the region between the two power rails. By routing the power supply voltages and signals of the predefined cell in this manner, the predefined cells, as well as the integrated circuit created from the predefined cells, are more compact while still complying with design rules.”)
(Sherlekar-908, p. 4, [0047] “… For example, to access the cell pin 425 for the Al input signal, a single trace on the M2 layer can be routed across the cell 400 in a direction that is orthogonal to the gates and connected to the pin 425 with a single via.”)
Regarding claim 4
Sherlekar-908 teaches all aspects of claim 1 as disclosed above and further discloses
The method of claim 1, wherein placing the plurality of cell pins comprises
placing the plurality of cell pins on a metal layer farther from a substrate than the first power rail.
(Sherlekar-908, p. 3, [0039] “… Integrated circuits use several metal layers for routing wires. The metal layer closest to the substrate is referred to as the metal 1 ("M1") layer. The next closest layer is referred to as the metal 2 ("M2") layer, and the next closest layer after the M2 layer is referred to as the metal 3 ("M3") layer.”)
(Sherlekar-908, p. 4, [0051] “In one embodiment, standard cells within a library may be designed to have power pins of fixed width placed at fixed heights. By fixing the width and heights of the power pins, the pins of the cells form a common power rail that is shared amongst the cells when placed into a layout.”)
Regarding claim 5
Sherlekar-908 teaches all aspects of claim 1 as disclosed above and further discloses
The method of claim 1, further comprising
retrieving the plurality of cells from a cell library.
(Sherlekar-908, p. 2, [0027] “Embodiments of the present disclosure relate to a cell library of compact predefined cells for use in designing and manufacturing an integrated circuit. In one embodiment, the cell library includes a plurality of predefined cells with one power supply voltage routed along the boundary of the cells and another power supply voltage routed along the interior of the cells.”)
Regarding claim 7
Sherlekar-908 teaches all aspects of claim 1 as disclosed above and further discloses
The method of claim 1, wherein placing the plurality of cell pins comprises
placing the plurality of cell pins using an automatic placement routing (APR) tool.
(Sherlekar-908, p. 5, [0056] “… The compiler 715 represents various software tools that are part of an Electronic Design Automation (EDA) toolset, such as synthesis tools and place and route tools.”)
Regarding claim 8
Sherlekar-908 teaches all aspects of claim 1 as disclosed above and further discloses
The method of claim 1, further comprising
fabricating at least one mask based on the layout diagram for forming the integrated circuit.
(Sherlekar-908, p. 5, [0060] “The fabrication facility 725 receives the layout 720 from the compiler and forms the shapes (e.g., metal wires, gates, vias, etc.) defined by the layout. In one embodiment, the facility 625 generates a lithographic mask and uses the lithographic mask to fabricate the IC.”)
Regarding claim 18
Sherlekar-908 discloses
A system for generating an integrated circuit, the system comprising
(Sherlekar-908, p. 7, [0076] “Upon reading this disclosure, those of skill in the art will appreciate still additional alternative structural and functional designs for a system for creating an integrated circuit from a standard cell library of compact standard cells through the disclosed principles herein.”)
a non-transitory computer readable medium configured to store instructions thereon
(Sherlekar-908, p. 1, [0011] “One embodiment of the non-transitory computer readable medium stores instructions for receiving a plurality of cells and generating a layout for an integrated circuit from cells.”)
and a processor connected to the non-transitory computer readable medium, wherein the processor is configured to execute the instructions for
(Sherlekar-908, p. 2, [0014] “Figure (FIG.) 1 illustrates one embodiment of components of an example machine able to read instructions from a machine-readable medium and execute them in a processor (or controller).”)
arranging a plurality of cells in the layout diagram, wherein each cell of the plurality of cells comprises a first power rail along a first boundary and a second power rail along a second boundary, and the first boundary is spaced from the second boundary in a first direction
(Sherlekar-908, p. 1, [0006] “During the process of designing an integrated circuit, a designer may select particular cells from a library of cells and use them in a design.”)
(Sherlekar-908, p. 1, [0011] “One embodiment of the non-transitory computer readable medium stores instructions for receiving a plurality of cells and generating a layout for an integrated circuit from cells. At least one of the cells includes a first metal wire extending along a first boundary of the cell for carrying a first power supply voltage. A second metal wire extends along an interior of the cell for carrying a second power supply voltage. A cell pin corresponding to one of an input signal or output signal of the cell is located between the second metal wire and a second boundary that is opposite from the first boundary.”)
(Sherlekar-908, p. 4, [0051] “… As used herein, a power rail is defined as a wire structure that is primarily used to carry a power supply voltage, such as VDD, VSS, ground, etc. to the cells of an integrated circuit.”)
and placing a plurality of cell pins over a plurality of selected via placement points in a first cell of the plurality of cells in accordance with a design rule, wherein a first cell pin of the plurality of cell pins has a first end spaced from both the first power rail and the second power rail in the first direction.
(Sherlekar-908, p. 1, [0010] “… At least one cell in integrated circuit architecture includes a first metal wire extending along a first boundary of the cell for carrying a first power supply voltage. A second metal wire extends along an interior of the cell for carrying a second power supply voltage. A cell pin corresponding to an input signal or output signal of the cell is located between the second metal wire and a second boundary that is opposite from the first boundary. By configuring the power supply voltages and cell pins in this manner, the layout for the integrated circuit is more compact while still complying with various design rules.”)
(Sherlekar-908, p. 1, [0008] “… Routing in an IC design is accomplished through routing elements, such as traces in one or more metal layers. Each metal layer is separated from other metal layers by insulating layers, and vias connect one metal layer to another. These routing elements perform at least two functions: they connect individual transistors that make up a cell, and they connect cells to each other globally (i.e., on a chip-level) to implement the desired functionality of the integrated circuit.”)
(Sherlekar-908, p. 1, [0027] “… A cell pin carrying an input or output signal of the predefined cell, or an internal connection between transistors of the predefined cell, is positioned outside of the region between the two power rails. By routing the power supply voltages and signals of the predefined cell in this manner, the predefined cells, as well as the integrated circuit created from the predefined cells, are more compact while still complying with design rules.”)
(Sherlekar-908, p. 4, [0047] “… For example, to access the cell pin 425 for the Al input signal, a single trace on the M2 layer can be routed across the cell 400 in a direction that is orthogonal to the gates and connected to the pin 425 with a single via.”)
Regarding claim 19
Sherlekar-908 teaches all aspects of claim 18 as disclosed above and further discloses
The system of claim 18, wherein the processor is further configured to execute the instructions for arranging the plurality of cells by abutting the adjacent cells in the first direction.
(Sherlekar-908, p. 5, [0054] “… The Vx power rails 650 and 652 may be shared with cells in adjacent and abutting rows (not shown), similar to how the VSS power rail 630 is shared between two rows of cells.”)
Regarding claim 20
Sherlekar-908 teaches all aspects of claim 18 as disclosed above and further discloses
The system of claim 18, wherein the processor is further configured to execute the instructions for instructing at least one manufacturing tool to manufacture the integrated circuit including the first pin cell.
(Sherlekar-908, p.1, [0010] “Embodiments of the present disclosure relate to an integrated circuit, a computer-readable medium storing instructions for creating a layout for an integrated circuit, and a method for fabricating an integrated circuit. At least one cell in integrated circuit architecture includes a first metal wire extending along a first boundary of the cell for carrying a first power supply voltage. A second metal wire extends along an interior of the cell for carrying a second power supply voltage. A cell pin corresponding to an input signal or output signal of the cell is located between the second metal wire and a second boundary that is opposite from the first boundary. By configuring the power supply voltages and cell pins in this manner, the layout for the integrated circuit is more compact while still complying with various design rules.”)
(Sherlekar-908, p.2, [0027] “Embodiments of the present disclosure relate to a cell library of compact predefined cells for use in designing and manufacturing an integrated circuit.”)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Sherlekar-908 as applied to claim 1 above, and further in view of Jae-Boong Lee et. al. (US 20180294226 A1) hereinafter Lee.
Regarding claim 2
Sherlekar-908 teaches all aspects of claim 1 as disclosed above.
The method of claim 1, wherein placing the plurality of cell pins comprises
Sherlekar-908 does not explicitly teach
placing a second cell pin of the plurality of cell pins having a second end aligned with an edge of the first power rail outside the first cell.
However, Lee discloses
placing a second cell pin of the plurality of cell pins having a second end aligned with an edge of the first power rail outside the first cell.
(Lee, p. 5, [0046] “… As shown in FIG. 6A, the input pins P61 to P64 and the output pin P65 may extend in a Y-axis direction to a position close to a boundary of the standard cell C60. The close proximity of the pins P61 to P65 to the boundary of the standard cell C60 is due to omission of the conductive line of the M2 layer in the power rails PR61 and PR62.”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of Sherlekar-908 and of Lee to extend the pins to the edge of the power rail and meet the circuit layout design requirement and yield predictable result of highly optimized layout in terms of power consumption etc.
Regarding claim 3
Sherlekar-908 teaches all aspects of claim 1 as disclosed above.
Sherlekar-908 does not explicitly teach
The method of claim 1, wherein placing the plurality of cell pins comprises
placing the first cell pin extending beyond the first power rail in the first direction.
However, Lee discloses
placing the first cell pin extending beyond the first power rail in the first direction.
(Lee, p. 2, [0025] “… For example, as shown in FIG. 1, the input pin and/or the output pin of the first standard cell C11 may extend in the Y-axis direction such that conductive lines L23, L24, and L25 passing through the first power rail PR11 and/or the second power rail PR12 may be formed.”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of Sherlekar-908 and of Lee to extend the pins to meet the circuit layout design requirement and yield predictable result of highly optimized layout in terms of power consumption etc.
Regarding claim 6
Sherlekar-908 teaches all aspects of claim 1 as disclosed above.
Sherlekar-908 does not explicitly teach
The method of claim 1, wherein placing the plurality of cell pins comprises
placing the first cell pin extending only in the first direction.
However, Lee discloses
placing the first cell pin extending only in the first direction.
(Lee, p. 2, [0025] “… For example, as shown in FIG. 1, the input pin and/or the output pin of the first standard cell C11 may extend in the Y-axis direction such that conductive lines L23, L24, and L25 passing through the first power rail PR11 and/or the second power rail PR12 may be formed.”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of Sherlekar-908 and of Lee to extend the pins in one direction to the edge of the power rail and meet the circuit layout design requirement and yield predictable result of highly optimized layout in terms of power consumption etc.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sherlekar-908 and in view of Jae-Boong Lee et. al. (US 20180294226 A1) hereinafter Lee
Regarding claim 9
Sherlekar-908 discloses
A method of generating a layout diagram for an integrated circuit, the method comprising
(Sherlekar-908, p. 2, [0023] “FIG. 8 illustrates one embodiment of a method for generating a layout for an integrated circuit.”)
arranging a plurality of cells in the layout diagram, wherein each cell of the plurality of cells comprises a first power rail along a first boundary and a second power rail along a second boundary, and the first boundary is spaced from the second boundary in a first direction
(Sherlekar-908, p. 1, [0006] “During the process of designing an integrated circuit, a designer may select particular cells from a library of cells and use them in a design.”)
(Sherlekar-908, p. 1, [0011] “One embodiment of the non-transitory computer readable medium stores instructions for receiving a plurality of cells and generating a layout for an integrated circuit from cells. At least one of the cells includes a first metal wire extending along a first boundary of the cell for carrying a first power supply voltage. A second metal wire extends along an interior of the cell for carrying a second power supply voltage. A cell pin corresponding to one of an input signal or output signal of the cell is located between the second metal wire and a second boundary that is opposite from the first boundary.”)
(Sherlekar-908, p. 4, [0051] “… As used herein, a power rail is defined as a wire structure that is primarily used to carry a power supply voltage, such as VDD, VSS, ground, etc. to the cells of an integrated circuit.”)
and placing a plurality of cell pins over a plurality of selected via placement points in a first cell of the plurality of cells in accordance with a design rule
(Sherlekar-908, p. 1, [0010] “… At least one cell in integrated circuit architecture includes a first metal wire extending along a first boundary of the cell for carrying a first power supply voltage. A second metal wire extends along an interior of the cell for carrying a second power supply voltage. A cell pin corresponding to an input signal or output signal of the cell is located between the second metal wire and a second boundary that is opposite from the first boundary. By configuring the power supply voltages and cell pins in this manner, the layout for the integrated circuit is more compact while still complying with various design rules.”)
(Sherlekar-908, p. 1, [0008] “… Routing in an IC design is accomplished through routing elements, such as traces in one or more metal layers. Each metal layer is separated from other metal layers by insulating layers, and vias connect one metal layer to another. These routing elements perform at least two functions: they connect individual transistors that make up a cell, and they connect cells to each other globally (i.e., on a chip-level) to implement the desired functionality of the integrated circuit.”)
(Sherlekar-908, p. 1, [0027] “… A cell pin carrying an input or output signal of the predefined cell, or an internal connection between transistors of the predefined cell, is positioned outside of the region between the two power rails. By routing the power supply voltages and signals of the predefined cell in this manner, the predefined cells, as well as the integrated circuit created from the predefined cells, are more compact while still complying with design rules.”)
(Sherlekar-908, p. 4, [0047] “… For example, to access the cell pin 425 for the Al input signal, a single trace on the M2 layer can be routed across the cell 400 in a direction that is orthogonal to the gates and connected to the pin 425 with a single via.”)
Sherlekar-908 does not teach
wherein a first cell pin of the plurality of cell pins overlaps the first power rail between the adjacent cells of the plurality of cells.
However, Lee discloses
wherein a first cell pin of the plurality of cell pins overlaps the first power rail between the adjacent cells of the plurality of cells.
(Lee, p. 5, [0047] “… Additionally, in reference to FIGS. 1, 2A, 2B, 6A and 6B, the input pins P61 to P64 and the output pin P65 may extend in the Y-axis direction across the power rails PR61 and PR62, and thus, the input signals A0, A1, B0, B1 and the output signal Y may be routed to the outside of the standard cell C60. Accordingly, routing congestion for the input signals A0, A1, B0, B1 and the output signal Y of the standard cell C60 may not occur.”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of Sherlekar-908 and of Lee to extend the pins to meet the circuit layout design requirement and yield predictable result of highly optimized layout in terms of physical size, routing congestion, power consumption etc.
Claims 10-15 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Sherlekar-908 as applied to claim 9 above, and further in view of Jae-Boong Lee et. al. (US 20180294226 A1) hereinafter Lee.
Regarding claim 10
Sherlekar-908 and Lee teaches all aspects of claim 9 as disclosed above and Sherlekar-908 further discloses
The method of claim 9, further comprising placing a via at a first via placement point of the plurality of selected via placement points, wherein the via overlaps the first cell pin.
(Sherlekar-908, p. 4, [0047] “… For example, to access the cell pin 425 for the Al input signal, a single trace on the M2 layer can be routed across the cell 400 in a direction that is orthogonal to the gates and connected to the pin 425 with a single via.”)
Regarding claim 11
Sherlekar-908 and Lee teaches all aspects of claim 9 as disclosed above and Sherlekar-908 further discloses
The method of claim 9, wherein placing the plurality of cell pins comprises placing a second cell pin of the plurality of cell pins entirely within a first cell of the plurality of cells.
(Sherlekar-908, p. 6, [0064] “… In one embodiment of the method, a cell pin for carrying an input or output signal of a cell of the integrated circuit is formed 910 in a metal layer. A metal wire for carrying a power supply voltage (e.g., VDD) is formed 920 along a first boundary of a cell of the integrated circuit. A second metal wire for carrying a second power supply voltage (e.g., VSS) is formed 930 along an interior of the cell. The metal wires are formed such that the cell pin is located between the second metal wire and a boundary of the cell that is opposite the first boundary. In one embodiment, the fabricated integrated circuit appears similar to the illustrations in FIG. 6A and 6B.”)
Regarding claim 12
Sherlekar-908 and Lee teaches all aspects of claim 11 as disclosed above.
Sherlekar-908 does not explicitly teach
The method of claim 11, wherein placing the second cell pin comprises
placing the second cell pin overlapping with a first via placement point of the plurality of selected via placement points.
However, Lee discloses
placing the second cell pin overlapping with a first via placement point of the plurality of selected via placement points.
(Lee, p. 5, [0047] “… In other words, the via V2 may be placed in at least one of points marked with ‘⋆’ in FIG. 6B, and thus, the input pins P61 to P64 and the output pin P65 may be electrically connected to at least one of the conductive lines L61 to L65 of the M3 layer. Since the input pins P61 to P64 and the output pin P65 extend close to a boundary of the standard cell C60 due to the conductive line of the M2 layer being omitted from the power rails PR61 and PR62 as described above with reference to FIG. 6A, points at which the via V2 may be placed may be expanded. “)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of Sherlekar-908 and of Lee to extend the pins to meet the circuit layout design requirement and yield predictable result of highly optimized layout in terms of physical size, routing congestion, power consumption etc.
Regarding claim 13
Sherlekar-908 and Lee teaches all aspects of claim 9 as disclosed above and Sherlekar-908 further discloses
The method of claim 9, wherein arranging the plurality of cells comprises
abutting the adjacent cells in the first direction.
(Sherlekar-908, p. 5, [0054] “… The Vx power rails 650 and 652 may be shared with cells in adjacent and abutting rows (not shown), similar to how the VSS power rail 630 is shared between two rows of cells.”)
Regarding claim 14
Sherlekar-908 and Lee teaches all aspects of claim 9 as disclosed above.
Sherlekar-908 does not explicitly teach
The method of claim 9, wherein placing the plurality of cell pins comprises
placing the plurality of cell pins satisfying a minimum end-to-end spacing requirement.
However, Lee discloses
placing the plurality of cell pins satisfying a minimum end-to-end spacing requirement.
(Lee, p. 4, [0042] “… As shown in FIG. 5A, the input pin P51 and the output pin P52 may be spaced apart from the conductive line of the M2 layer included in the power rail PR51 by a predetermined distance Y51 and may be spaced apart from each other by a predetermined distance X51. The predetermined distances Y51 and X51 may due to a semiconductor process or a design rule.”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of Sherlekar-908 and of Lee to extend the pins to meet the circuit layout design requirement and yield predictable result of highly optimized layout in terms of physical size, routing congestion, power consumption etc.
Regarding claim 15
Sherlekar-908 and Lee teaches all aspects of claim 9 as disclosed above.
Sherlekar-908 does not explicitly teach
The method of claim 9, further comprising
identifying a location of each of a plurality of via placement points, comprising the plurality of selected via placement points, based on an intersection of conductive lines at different levels of the integrated circuit.
However, Lee discloses
identifying a location of each of a plurality of via placement points, comprising the plurality of selected via placement points, based on an intersection of conductive lines at different levels of the integrated circuit.
(Lee, p. 2, [0024] “… For example, as shown in FIG. 1, the first power rail PR11 includes conductive lines L11 and L31 extending in parallel to each other in the X-axis direction and vias for electrically connecting the conductive lines L11 and L31 to each other. The second power rail PR12 may also include conductive lines L12 and L32 extending in parallel to each other in the X-axis direction and vias for electrically connecting the conductive lines L12 and L32 to each other.”)
(Lee, p. 3, [0026] “Referring to FIG. 2A, in a region R22, the second power rail PR12 may include the conductive lines L12 and L32 extending in parallel to each other in the X-axis direction and formed in the M1 layer and the M3 layer, respectively, and the conductive line L22 formed in the M2 layer extending in the X-axis direction. The second power rail PR12 may also include a plurality of vias V11, V12, V13, V21, V22 and V23 for electrically interconnecting the conductive lines L12, L22 and L32 in the region R22.”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of Sherlekar-908 and of Lee to extend the pins to meet the circuit layout design requirement and yield predictable result of highly optimized layout in terms of physical size, routing congestion, power consumption etc.
Regarding claim 17
Sherlekar-908 and Lee teaches all aspects of claim 9 as disclosed above and Sherlekar-908 further discloses
The method of claim 9, further comprising
instructing at least one manufacturing tool to manufacture the integrated circuit including the first pin cell.
(Sherlekar-908, p.1, [0010] “Embodiments of the present disclosure relate to an integrated circuit, a computer-readable medium storing instructions for creating a layout for an integrated circuit, and a method for fabricating an integrated circuit. At least one cell in integrated circuit architecture includes a first metal wire extending along a first boundary of the cell for carrying a first power supply voltage. A second metal wire extends along an interior of the cell for carrying a second power supply voltage. A cell pin corresponding to an input signal or output signal of the cell is located between the second metal wire and a second boundary that is opposite from the first boundary. By configuring the power supply voltages and cell pins in this manner, the layout for the integrated circuit is more compact while still complying with various design rules.”)
(Sherlekar-908, p.2, [0027] “Embodiments of the present disclosure relate to a cell library of compact predefined cells for use in designing and manufacturing an integrated circuit.”)
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Sherlekar-908(US 20140229908 A1) and Lee (US 20180294226 A1) as applied to claim 15 above, and further in view of Deepak Sherlekar (US 20080111158 A1), hereinafter Sherlekar-158.
Regarding claim 16
Sherlekar-908 and Lee teach all aspects of claim 15 as disclosed above.
Sherlekar-908 and Lee do not teach
The method of claim 15, further comprising
selecting each of the plurality of selected via placement points from the plurality of via placement points based on a spacing requirement.
However, Sherlekar-158 discloses
selecting each of the plurality of selected via placement points from the plurality of via placement points based on a spacing requirement.
(Sherlekar-158, p. 2, [0020] “… For example, the power rail may be formed by wires run in the same direction on a lower metal layer and a higher metal layer that are connected by a plurality of vias at intervals of regulated spacing between each via in the plurality of vias..”)
(Sherlekar-158, p. 2, [0024] “Another rule that renders routing difficult in submicron designs is the Via Farm Spacing Rule. Referring now to FIG. 2, this rule calls for larger via spacings (the shortest distance between two adjacent vias) when there are "many" vias in the vicinity (in the example here, four vias).”)
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains combine the teachings of Sherlekar-908, of Lee, and of Sherlekar-158 to extend the pins to meet the circuit layout design requirement and yield predictable result of highly optimized layout in terms of physical size, routing congestion, power consumption etc.
Conclusion
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/R.S./Examiner, Art Unit 2851
/JACK CHIANG/Supervisory Patent Examiner, Art Unit 2851
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