DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on February 10, 2026 has been entered.
Response to Arguments
Applicant's arguments filed February 10, 2026 have been fully considered but they are not persuasive. On pages 7-8, with respect to independent claims 1 and 10, the Applicant contends that Higuchi does not disclose “a bottom surface of the dielectric material directly contacts a top surface of the solder bump region of the second electrical connector”. The Examiner respectfully disagrees. Higuchi (see Fig. 6 and corresponding description) distinctly demonstrates that a bottom surface of the dielectric material (item 130) is in direct contact with the top surface of the solder bump region (top surface of item 220d) of the second electrical connector (item 220d).
Figure 6 from Higuchi has been included twice for reference in consideration of potential issues viewing the colors (blue, red, yellow, and green) or if the figures are displayed in grayscale.
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As illustrated in the enlarged view above, the dielectric layer 130 (yellow, lighter shade of gray or black) is shown directly contacting the top surface of the solder bump region 220d (white) at the outer edge/top surface. As stated before in the previous Office letter, the top surface of solder bump region 220d is wider than items 220a, 220b, and 220c. Higuchi discloses, “Thereafter, an underfill material mainly composed of an epoxy resin is filled between the first bump 120 and the second bump 220 and cured to form an underfill resin 130 as shown in FIG. (Post-coating) The underfill resin 130 may be applied on the first semiconductor chip 100 in advance as shown in FIG. 7 before the bonding step of the first bump 120 and the second bump 220 (First application). In that case, it can also be hardened by heat treatment at the time of bump bonding. In the case of pre-coating, the underfill resin 130 remaining in the recesses of the first bump 120 is pushed out by the second bump 220 when the first bump 120 and the second bump 220 are pressed. The first bump 120 and the second bump 220 are joined.”
A person skilled in the art would recognize that during this process, the solder bump region (item 220d), composed of Sn (tin), would conform to the recessed portion of item 120b due to tin’s relatively soft properties. Item 220c, constructed of nickel (Ni), known for its superior hardness and durability compared to tin (Sn), would maintain its original shape as depicted in Figure 6 of Higuchi. After completion of this step, the uppermost surface of the solder bump region (item 220d) exceeds the width of items 220a, 220b, and 220c. Therefore, a bottom surface of the dielectric layer (item 130) is in direct contact with the side surfaces of items 220a, 220b, and 220c, as well as with the uppermost/top surface of the solder bump region (item 220d) along its outer edge/top surface. Even if the Applicant wants to call it a sidewall, the sidewall of the dielectric material (item 130) of Higuchi has still has a bottom surface of its own in direct contact with the uppermost/top surface of the solder bump region (item 220d) along its outer edge/top surface. Accordingly, the Examiner stands by the decision that the rejection is appropriate. The same rationale applies to independent claims 10 and 17.
Applicant's arguments filed February 10, 2026 have been fully considered but they are not persuasive. On pages 8-9, with respect to independent claims 1 and 10, the Applicant contends that Higuchi does not disclose “fails to disclose a top surface of the asserted first U-shaped pattern 13 is horizontally coplanar with a top surface of the asserted second U-shaped pattern 14 and a top surface of any solder bumps. Specifically, Wakiyama fails to teach or suggest that its element 15 is a solder bump. Instead, Wakiyama merely states that it's third metal layer 15 could be made of copper, cobalt, nickel, palladium, gold, platinum, or the like. See Wakiyama [0067]”. The examiner respectfully disagrees. While Wakiyama does not explicitly state that metal layer 15 is a solder bump, it is still a metal bump that is made of common materials (copper) known in the art that to be used in lead-free solder. The Examiner takes the position the rejection is proper.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chandolu et al. (Chandolu) (US 2016/0225731 A1 also known as US 9,768,134 B2) in view of Wakiyama et al. (Wakiyama) (US 2017/0053960 A1) in view of Higuchi (WO 2014033977 A1).
In regards to claim 1, Chandolu (Figs. 5G, 6, 7 and associated text) discloses a semiconductor structure (Figs. 5G, 6, 7), comprising: a semiconductor substrate (item 502) having a first surface and a second surface opposite to the first surface; a first electrical connector (items 542, 522, 524 or 522 plus 524 or 542 plus 522 plus 524) disposed over the first surface of the semiconductor substrate (item 502); comprising a first U-shaped pattern (items 542 or 522) and a second U-shaped pattern (items 522, 524 or 522 plus 524); a second electrical connector (item 532) electrically connected to the first electrical connector (items 542, 522, 524 or 522 plus 524 or 542 plus 522 plus 524), the first electrical connector (items 542, 522, 524 or 522 plus 524 or 542 plus 522 plus 524) surrounding the second electrical connector (item 532); and a dielectric material (items 526 or 526 plus 536 or 526 plus 536 plus 508) between the first electrical connector (items 542, 522, 524 or 522 plus 524 or 542 plus 522 plus 524) and the second electrical connector (item 533), wherein the first surface (bottom surface) of the second electrical connector (item 532) is physically connected to the second U-shaped pattern (items 522, 524 or 522 plus 524), a sidewall (outer sidewall) connecting to the first surface (bottom surface) of the second electrical connector (item 532) is physically separated from a sidewall (inner sidewall) of the second U-shaped pattern (items 522, 524 or 522 plus 524) and the dielectric material (items 526 or 526 plus 536 or 526 plus 536 plus 508) is disposed between the sidewall (outer sidewall) of the second electrical connector (item 532) and the sidewall (inner sidewall) of the second U-shaped pattern (items 522, 524 or 522 plus 524). Examiner notes the items 526, 508 and 536 can be made of some of the same materials and could therefore be made as an integral structure (paragraphs 29, 34 and 45).
Chandolu does not specifically disclose a projection of the second U-shaped pattern onto the first surface of the semiconductor substrate is smaller than a projection of the first U-shaped pattern on to the first surface of the semiconductor substrate and larger than the projection of the second electrical connector onto the first surface of the semiconductor substrate.
In regards to claim 1, Wakiyama (Fig. 6B and associated text) discloses a projection of the second U-shaped pattern (item 14, Wakiyama) onto the first substrate (item 10, Wakiyama) is smaller than a projection of the first U-shaped pattern (item 13, Wakiyama) onto the first substrate (item 10, Wakiyama) and larger than a projection of the second electrical connector (item 15, Wakiyama) onto the first substrate (item 10, Wakiyama).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Wakiyama for the purpose of an electrical connection (paragraph 65) and design choice, since such a modification would have involved a mere change in the size/shape of a component. A change in size/shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)).
Chandolu as modified by Wakiyama does not specifically disclose a bottom surface of the dielectric material directly contacts a top surface of the solder bump region of the second electrical connector.
Higuchi (Fig. 6 and associated text) discloses a bottom surface of the dielectric material (item 130) directly contacts a top surface of the solder bump region (top surface of item 220d) of the second electrical connector (item 220d).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Higuchi for the purpose of protection and mechanical bonding.
In regards to claim 2, Chandolu (Figs. 5G, 6, 7 and associated text) discloses wherein the first electrical connector (items 542, 522, 524 or 522 plus 524 or 542 plus 522 plus 524) surrounds the sidewall (outer sidewall) and the first surface (bottom surface) of the second electrical connector (item 533).
In regards to claim 3, Chandolu (Figs. 5G, 6, 7 and associated text) as modified by Wakiyama (Fig. 6B and associated text) discloses wherein a surface of the first electrical connector (items 542, 522, 524 or 522 plus 524 or 542 plus 522 plus 524, Chandolu, items 13 plus 14, Wakiyama) is horizontally coplanar with a second surface (top surface) opposite to the first surface (bottom surface) of the second electrical connector (item 532, Chandolu, item 15, Wakiyama).
In regards to claim 4, Chandolu (Figs. 5G, 6, 7 and associated text) discloses wherein the dielectric material (items 526 or 526 plus 536 or 526 plus 536 plus 508) is in direct contact with sidewall (inner sidewall) of the second U-shaped pattern (items 522, 524 or 522 plus 524) and the sidewall (outer sidewall) the second electrical connector (item 533). Examiner notes the items 526, 508 and 536 can be made of some of the same materials and could therefore be made as an integral structure (paragraphs 29, 34 and 45).
In regards to claim 5, Chandolu (Figs. 5G, 6, 7 and associated text) discloses wherein the dielectric material (items 526 or 526 plus 536 or 526 plus 536 plus 508) further surrounds the first electrical connector (items 522, 524 or 522 plus 524). Examiner notes the items 526, 508 and 536 can be made of some of the same materials and could therefore be made as an integral structure (paragraphs 29, 34 and 45).
In regards to claim 6, Chandolu (Figs. 5G, 6, 7 and associated text) discloses wherein the dielectric material (items 526 or 526 plus 536 or 526 plus 536 plus 508) covers the first electrical connector (items 522, 524 or 522 plus 524) and the second electrical connector (item 533). Examiner notes the items 526, 508 and 536 can be made of some of the same materials and could therefore be made as an integral structure (paragraphs 29, 34 and 45).
Claim(s) 1-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chandolu et al. (Chandolu) (US 2016/0225731 A1 also known as US 9,768,134 B2) in view of Tagami (JP 2001015549 A) in view of Higuchi (WO 2014033977 A1).
In regards to claim 1, Chandolu (Figs. 5G, 6, 7 and associated text) discloses a semiconductor structure (Figs. 5G, 6, 7), comprising: a semiconductor substrate (item 502) having a first surface and a second surface opposite to the first surface; a first electrical connector (items 542, 522, 524 or 522 plus 524 or 542 plus 522 plus 524) disposed over the first surface of the semiconductor substrate (item 502); comprising a first U-shaped pattern (items 542 or 522) and a second U-shaped pattern (items 522, 524 or 522 plus 524); a second electrical connector (item 532) electrically connected to the first electrical connector (items 542, 522, 524 or 522 plus 524 or 542 plus 522 plus 524), the first electrical connector (items 542, 522, 524 or 522 plus 524 or 542 plus 522 plus 524) surrounding the second electrical connector (item 532); and a dielectric material (items 526 or 526 plus 536 or 526 plus 536 plus 508) between the first electrical connector (items 542, 522, 524 or 522 plus 524 or 542 plus 522 plus 524) and the second electrical connector (item 533), wherein the first surface (bottom surface) of the second electrical connector (item 532) is physically connected to the second U-shaped pattern (items 522, 524 or 522 plus 524), a sidewall (outer sidewall) connecting to the first surface (bottom surface) of the second electrical connector (item 532) is physically separated from a sidewall (inner sidewall) of the second U-shaped pattern (items 522, 524 or 522 plus 524) and the dielectric material (items 526 or 526 plus 536 or 526 plus 536 plus 508) is disposed between the sidewall (outer sidewall) of the second electrical connector (item 532) and the sidewall (inner sidewall) of the second U-shaped pattern (items 522, 524 or 522 plus 524). Examiner notes the items 526, 508 and 536 can be made of some of the same materials and could therefore be made as an integral structure (paragraphs 29, 34 and 45).
Chandolu does not specifically disclose a projection of the second U-shaped pattern onto the first surface of the semiconductor substrate is smaller than a projection of the first U-shaped pattern on to the first surface of the semiconductor substrate and larger than the projection of the second electrical connector onto the first surface of the semiconductor substrate.
In regards to claim 1, Tagami (Fig. 1and associated text) discloses a projection of the second U-shaped pattern (item 17, Tagami) onto the first substrate (item 11, Tagami) is smaller than a projection of the first U-shaped pattern (item 16, Tagami) onto the first substrate (item 11, Tagami) and larger than a projection of the second electrical connector (item 18, Tagami) onto the first substrate (item 11, Tagami).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Tagami for the purpose of an electrical connection and design choice, since such a modification would have involved a mere change in the size/shape of a component. A change in size/shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)).
Chandolu as modified by Tagami does not specifically disclose a bottom surface of the dielectric material directly contacts a top surface of the solder bump region of the second electrical connector.
Higuchi (Fig. 6 and associated text) discloses a bottom surface of the dielectric material (item 130) directly contacts a top surface of the solder bump region (top surface of item 220d) of the second electrical connector (item 220d).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Higuchi for the purpose of protection and mechanical bonding.
In regards to claim 2, Chandolu (Figs. 5G, 6, 7 and associated text) discloses wherein the first electrical connector (items 542, 522, 524 or 522 plus 524 or 542 plus 522 plus 524) surrounds the sidewall (outer sidewall) and the first surface (bottom surface) of the second electrical connector (item 533).
In regards to claim 3, Chandolu (Figs. 5G, 6, 7 and associated text) as modified by Wakiyama (Fig. 6B and associated text) discloses wherein a surface of the first electrical connector (items 542, 522, 524 or 522 plus 524 or 542 plus 522 plus 524, Chandolu, items 16 plus 17, Tagami) is horizontally coplanar with a second surface (top surface) opposite to the first surface (bottom surface) of the second electrical connector (item 532, Chandolu, item 18, Tagami).
In regards to claim 4, Chandolu (Figs. 5G, 6, 7 and associated text) discloses wherein the dielectric material (items 526 or 526 plus 536 or 526 plus 536 plus 508) is in direct contact with sidewall (inner sidewall) of the second U-shaped pattern (items 522, 524 or 522 plus 524) and the sidewall (outer sidewall) the second electrical connector (item 533). Examiner notes the items 526, 508 and 536 can be made of some of the same materials and could therefore be made as an integral structure (paragraphs 29, 34 and 45).
In regards to claim 5, Chandolu (Figs. 5G, 6, 7 and associated text) discloses wherein the dielectric material (items 526 or 526 plus 536 or 526 plus 536 plus 508) further surrounds the first electrical connector (items 522, 524 or 522 plus 524). Examiner notes the items 526, 508 and 536 can be made of some of the same materials and could therefore be made as an integral structure (paragraphs 29, 34 and 45).
In regards to claim 6, Chandolu (Figs. 5G, 6, 7 and associated text) discloses wherein the dielectric material (items 526 or 526 plus 536 or 526 plus 536 plus 508) covers the first electrical connector (items 522, 524 or 522 plus 524) and the second electrical connector (item 533). Examiner notes the items 526, 508 and 536 can be made of some of the same materials and could therefore be made as an integral structure (paragraphs 29, 34 and 45).
Claim(s) 8 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chandolu et al. (Chandolu) (US 2016/0225731 A1 also known as US 9,768,134 B2) in view of Wakiyama et al. (Wakiyama) (US 2017/0053960 A1) in view of Higuchi (WO 2014033977 A1) as applied to claims 1-6 above, and further in view of in view of Li et al. (Li) (US 2015/0155242 A1).
In regards to claim 8, Chandolu as modified by Wakiyama and Higuchi does not specifically disclose a protection layer on sidewalls and the second surface of the semiconductor substrate.
Li (Figs. 2, 2’, 2F” and associated text) discloses a protection layer (items 202, 212 or 202 plus 212) on sidewalls and the second surface of the semiconductor substrate (item 201).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Li for the purpose of protection and inducing stress (paragraph 42).
In regards to claim 9, Chandolu as modified by Wakiyama and Higuchi does not specifically disclose wherein a surface of the protection layer is horizontally coplanar with the first surface of the semiconductor substrate.
Li (Figs. 2, 2’, 2F” and associated text) discloses wherein a surface of the protection layer (items 202, 212 or 202 plus 212) is horizontally coplanar with the first surface of the semiconductor substrate (item 201).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Li for the purpose of protection and inducing stress (paragraph 42).
Claim(s) 8 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chandolu et al. (Chandolu) (US 2016/0225731 A1 also known as US 9,768,134 B2) in view of Tagami (JP 2001015549 A) in view of Higuchi (WO 2014033977 A1) as applied to claims 1-6 above, and further in view of in view of Li et al. (Li) (US 2015/0155242 A1).
In regards to claim 8, Chandolu as modified by Tagami and Higuchi does not specifically disclose a protection layer on sidewalls and the second surface of the semiconductor substrate.
Li (Figs. 2, 2’, 2F” and associated text) discloses a protection layer (items 202, 212 or 202 plus 212) on sidewalls and the second surface of the semiconductor substrate (item 201).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Li for the purpose of protection and inducing stress (paragraph 42).
In regards to claim 9, Chandolu as modified by Tagami and Higuchi does not specifically disclose wherein a surface of the protection layer is horizontally coplanar with the first surface of the semiconductor substrate.
Li (Figs. 2, 2’, 2F” and associated text) discloses wherein a surface of the protection layer (items 202, 212 or 202 plus 212) is horizontally coplanar with the first surface of the semiconductor substrate (item 201).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Li for the purpose of protection and inducing stress (paragraph 42).
Claim(s) 10, 12, 13, 24, 25 and 28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Higuchi (WO 2014033977 A1) in view of Chandolu et al. (Chandolu) (US 2016/0225731 A1 also known as US 9,768,134 B2).
In regards to claim 10, Higuchi (Figs. 5-7 and associated text) discloses a semiconductor structure (Fig. 6), comprising: a first substrate (item 101), comprising a first bonding structure (item 120, 110 plus 120 or 102 plus 110 plus 120) thereon; a second substrate (item 201), comprising a second bonding structure (items 220 or 210 plus 220 or 220d) thereon, the second bonding structure (items 220 or 210 plus 220 or 220d) bonded to the first bonding structure (item 120, 110 plus 120 or 102 plus 110 plus 120), wherein the second bonding structure (items 220 or 210 plus 220 or 220d) comprises a solder bump (item 220d), wherein an inner sidewall of the first bonding structure (item 120, 110 plus 120 or 102 plus 110 plus 120) surrounds an outer sidewall of the solder bump (item 220d) of the second bonding structure (items 220 or 210 plus 220); and a dielectric material (item 130), wherein the dielectric material (item 130) is continuously inserted between the inner sidewall of the first bonding structure (item 120, 110 plus 120 or 102 plus 110 plus 120), the dielectric material (item 130) covers a top surface of the first bonding structure (item 120, 110 plus 120 or 102 plus 110 plus 120) and a top surface of the solder bump (item 220d) of the second bonding structure (items 220 or 210 plus 220 or 220d), and the top surface of the first bonding structure (item 120, 110 plus 120 or 102 plus 110 plus 120) and the top surface of the solder bump (item 220d) of the second bonding structure (items 220 or 210 plus 220 or 220d) both face the second substrate (item 201), and a bottom surface of the dielectric material (item 130) directly contacts the top surface of the solder bump (item 220d) of the second bonding structure (items 220 or 210 plus 220 or 220d), but does not specifically disclose wherein the dielectric material (item 130) is continuously inserted between the inner sidewall of the first bonding structure (item 120, 110 plus 120 or 102 plus 110 plus 120) and the outer sidewall of the solder bump (item 220d) of the second bonding structure (items 220 or 210 plus 220 or 220d).
In regards to claim 10, Chandolu (Fig. 7 and associated text) discloses a dielectric material (items 526 or 526 plus 536 or 526 plus 536 plus 508), wherein the dielectric (items 526 or 526 plus 536 or 526 plus 536 plus 508) is continuously inserted between the inner sidewall of the first bonding structure (items 522 plus 524) and the outer sidewall of the of the solder bump (item 532) of the second bonding structure (items 532 or 532 plus 534). Examiner notes that items 508, 526 and 536 could be made of the same material (paragraphs 29, 34, 45, polyimide).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings Chandolu for the purpose of protection.
In regards to claim 12, Higuchi (Figs. 5-7 and associated text) discloses wherein the first bonding structure (item 120, 110 plus 120 or 102 plus 110 plus 120) comprises a first U-shaped pattern (items 120a or 120b) and a second U-shaped pattern (items 120a or 120b).
In regards to claim 13, Higuchi (Figs. 5-7 and associated text) discloses wherein the second U-shaped pattern (items 120a or 120b) surrounds the solder bump (item 220d).
In regards to claim 24, Higuchi (Figs. 5-7 and associated text) discloses as wherein the dielectric material (item 130) is in direct contact with the top surface of the first bonding structure (item 120, 110 plus 120 or 102 plus 110 plus 120) and the second bonding structure (items 220 or 210 plus 220 or 220d).
In regards to claim 25, Higuchi (Figs. 5-7 and associated text) as modified by Chandolu (Fig. 7 and associated text) discloses wherein the dielectric material (item 130, Higuchi, items 526 or 526 plus 536 or 526 plus 536 plus 508, Chandolu) further continuously covers an outer sidewall of the first bonding structure (items 120a plus 120b, Higuchi, items 522 plus 524, Chandolu).
In regards to claim 28, Higuchi (Figs. 5-7 and associated text) as modified by Chandolu (Fig. 7 and associated text) discloses wherein the second bonding structure (items 220 or 210 plus 220 or 220d, Higuchi, items 532, 534, Chandolu) further comprises a conductive pad (items 220a, 220b or 220c, Higuchi, item 534, Chandolu), and wherein the dielectric material (item 130, Higuchi, items 526 or 526 plus 536 or 526 plus 536 plus 508, Chandolu) extends continuously from a bottom surface of the conductive pad (items 220a, 220b or 220c, Higuchi, item 534, Chandolu) to the top surface of the solder bump (item 220d, Higuchi).
Claim(s) 14, 15, 17, 18, 22 and 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Higuchi (WO 2014033977 A1) in view of Chandolu et al. (Chandolu) (US 2016/0225731 A1 also known as US 9,768,134 B2) as applied to claims 10, 12 and 13 above and further in view of Wakiyama et al. (Wakiyama) (US 2017/0053960 A1).
In regards to claim 14, Higuchi (Figs. 5-7 and associated text) as modified by Chandolu (Fig. 7 and associated text) does not specifically disclose wherein top surfaces of the first U-shaped pattern (items 120a or 120b, Higuchi, items 522 or 524, Chandolu,) and a second U-shaped pattern (items 120a or 120b, Higuchi, items 522 or 524, Chandolu,) and the bump (item 532, Chandolu) are horizontally coplanar.
Wakiyama (Fig. 6B and associated text) discloses wherein top surfaces of the first U-shaped pattern (item 13) and a second U-shaped pattern (item 14) and the solder bump (item 15,) are horizontally coplanar.
It would have been obvious to modify the invention to include top surfaces of a first and second U-shaped patterns and the solder bump to be horizontally coplanar, since such a modification would have involved a mere change in the size/shape of a component. A change in size/shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)).
In regards to claim 15, Higuchi (Figs. 5-7 and associated text) as modified by Chandolu (Fig. 7 and associated text) and Wakiyama (Fig. 6B and associated text) discloses wherein the dielectric material (item 130, Higuchi, items 526 or 526 plus 536 or 526 plus 536 plus 508, Chandolu, items 12 plus 16, Wakiyama) is in direct contact with the top surfaces of the first U-shaped pattern (items 120a or 120b, Higuchi, items 524 or 522, Chandolu, item 13, Wakiyama) and a second U-shaped pattern (items 120a or 120b, Higuchi, items 522, 524 or 522 plus 524, Chandolu, item 14, Wakiyama).
In regards to claim 17, Higuchi (Figs. 5-7 and associated text) discloses a semiconductor structure (Fig. 6), comprising: a first semiconductor element (item 100), comprising a first pad (items 120a plus 120b), wherein the first pad (items 120a plus 120b) comprises a first U-shaped pattern (item 120a) and a second U-shaped pattern (item 120b) in the first U-shaped pattern (items 120a); a second semiconductor element (item 200), comprising a solder bump (item 220d), wherein the solder bump (items 220 or 220d alone) is in direct contact with the second U-shaped pattern (item 120b) of the first pad (items 120a plus 120b); and a dielectric material (item 130) between the solder bump (items 220 or 220d alone) and the second U-shaped pattern (items 120b) of the first pad (items 120a plus 120b), the dielectric material (item 130) directly contacts the top surface of the top surface of the second U-shaped pattern (item 120b) and the top surface of the solder bump (item 220d), but does not specifically disclose wherein a dielectric material (item 130) between the solder bump (item 220d) and the second U-shaped pattern (items 120b) of the first pad (items 120a plus 120b).
Chandolu (Fig. 7 and associated text) discloses a dielectric material (items 526 or 526 plus 536 or 526 plus 536 plus 508) between the solder bump (item 532) and the second U-shaped pattern (item 524) of the first pad (items 524 plus 522, Chandolu). Examiner notes that items 508, 526 and 536 could be made of the same material (paragraphs 29, 34, 45, polyimide).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings Chandolu for the purpose of protection.
Higuchi as modified by Chandolu does not specifically disclose wherein a top surface of the first U-shaped pattern is horizontally coplanar with a top surface of the second U-shaped pattern and a top surface of the solder bump, and the dielectric material overlaps directly contacts the top surface of the first U-shaped pattern, the top surface of the second U-shaped pattern and the top surface of the solder bump.
Wakiyama (Fig. 6B and associated text) discloses wherein a top surface of the first U-shaped pattern (item 13) is horizontally coplanar with a top surface a second U-shaped pattern (item 14) and the solder bump (item 15).
It would have been obvious to modify the invention to include top surfaces of a first and second U-shaped patterns and the solder bump to be horizontally coplanar, since such a modification would have involved a mere change in the size/shape of a component. A change in size/shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)).
Therefore, Higuchi (Figs. 5-7 and associated text) as modified by Chandolu (Fig. 7 and associated text) and Wakiyama (Fig. 6B and associated text) discloses wherein a top surface of the first U-shaped pattern (item 120a, Higuchi, item 522, Chandolu, item 13, Wakiyama) is horizontally coplanar with a top surface of the second U-shaped pattern (item 120b, Higuchi, item 524, Chandolu, item 14, Wakiyama) and a top surface of the solder bump (item 220d, Higuchi, item 15, Wakiyama), and the dielectric material (item 130, Higuchi, items 526 or 526 plus 536 or 526 plus 536 plus 508, Chandolu, items 12 plus 16, Wakiyama) directly contacts the top surface of the first U-shaped pattern (items 120a or 120b, Higuchi, items 524 or 522, Chandolu, item 13, Wakiyama), the top surface of the second U-shaped pattern (items 120a or 120b, Higuchi, items 522, 524 or 522 plus 524, Chandolu, item 14, Wakiyama) and the top surface of the solder bump (item 220d, Higuchi).
In regard to claim 18, Higuchi (Figs. 5-7 and associated text) as modified by Chandolu (Fig. 7 and associated text) and Wakiyama (Fig. 6B and associated text) discloses wherein the dielectric material (item 130, Higuchi, items 526 or 526 plus 536 or 526 plus 536 plus 508, Chandolu, items 12 plus 16, Wakiyama) continuously surrounds the first pad (items 120a plus 120b, Higuchi, items 522 plus 524, Chandolu, item 13 plus 14, Wakiyama) and the solder bump (item 220d, Higuchi, item 532, Chandolu) and covers the first pad (items 120a plus 120b, Higuchi, items 522 plus 524, Chandolu, item 13 plus 14, Wakiyama) and the solder bump (item 220d, Higuchi).
In regards to claim 22, Higuchi (Figs. 5-7 and associated text) as modified by Chandolu (Fig. 7 and associated text) and Wakiyama (Fig. 6B and associated text) discloses wherein the first semiconductor element (item 100, Higuchi, items 500a or 500b, Chandolu, item 23, Wakiyama) further comprises a first substrate (item 101, Higuchi, item 502, Chandolu, item 10, Wakiyama), and a projection of the second U-shaped pattern ((item 120b, Higuchi, item 524, Chandolu, item 14, Wakiyama) onto the first substrate ((item 101, Higuchi, item 502, Chandolu, item 10, Wakiyama) is smaller than a projection of the first U-shaped pattern (item 120a, Higuchi, item 510 or 510 plus 522, Chandolu, item 13, Wakiyama) onto the first substrate (item 101, Higuchi, item 502, Chandolu, item 10, Wakiyama).
In regards to claim 27, Higuchi (Figs. 5-7 and associated text) as modified wherein the second semiconductor element (item 200) further comprises a conductive pad (item 220c) directly contacting a top surface of the solder bump (item 220d), wherein the dielectric material (item 130) directly contacts sidewalls of the conductive pad (item 220c), and wherein a width of the conductive pad (item 220c) is less than a width of the solder bump (item 220d).
Conclusion
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TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898
April 2, 2026