DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on January 26, 2026 has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-6, 9-14, and 16 are rejected under 35 U.S.C. 102(a)(1)(2) as being anticipated by U.S. Patent No. 4,803,526 to Terada et al. (“Terada”). As to claim 1, Terada discloses a semiconductor structure comprising: a well region (60, 70, 72, 74, 76) disposed within a semiconductor substrate (10); the well region (60, 70, 72, 74, 76) comprising a plurality of first regions (60, 70, 72) separated by a plurality of second regions (74, 76), wherein the plurality of first regions (60, 70, 72) are of a first doping type (P) and a first concentration (p) of the first doping type (P) and the plurality of second regions (74, 76) are of the first doping type (P) and a second concentration (p+) of the first doping type (P) that is different than the first concentration (p); and a source (16) and a drain (18), wherein bottommost surfaces of the source (16) and the drain (18) contact alternating portions of the plurality of first (60, 70, 72) and second (74, 76) regions, wherein the source (16) and the drain (18) are of a second doping type (N) that is different than the first doping type (P) (See Fig. 8, Column 2, lines 51-67, Column 8, lines 34-58) (Notes: the limitation “portion” is defined as an often limited part of a whole by and the limitation “region” is defined as any of the major subdivisions into which the body or one of its parts is divisible by Merriam-Webster.com. Further, GaAs is a well-known III-V semiconductor material. Lastly, the bottommost surfaces are the lower curved surfaces as shown in Fig. 3 of the Application). As to claim 2, Terada discloses wherein the source (16) and the drain (18) are disposed within the plurality of first regions (60, 70, 72) and the plurality of second regions (74, 76) (See Fig. 8). As to claim 3, Terada further discloses wherein top surfaces of the source (16) and the drain (18) are level with a first top surface of the plurality of first (60, 70, 72) and second (74, 76) regions and wherein bottom surfaces of the source (16) and the drain (18) are above a second top surface of the plurality of first (60, 70, 72) and second (74, 76) regions (See Fig. 8) (Notes: the top overlapped surfaces are level). As to claim 4, Terada further discloses wherein a top surface of the plurality of first regions (60, 70, 72) or a top surface of the plurality of second regions (74, 76) are curved (See Fig. 8). As to claim 5, Terada further discloses wherein a width of the plurality of first regions (60, 70, 72) is different than a width of the plurality of second regions (74, 76) (See Fig. 8). As to claim 6, Terada discloses further comprising: a gate electrode (14) overlying the well region (60, 70, 72, 74, 76), wherein the gate electrode (14) is disposed laterally overlapping a portion of the plurality of first regions (60, 70, 72) and a portion of the plurality of second regions (74, 76), and wherein the plurality of first regions (60, 70, 72) extend in a lateral direction perpendicular to a longest length of the gate electrode (14) (See Fig. 8). As to claim 9, Terada discloses a semiconductor structure comprising: a well region (60, 70, 72, 74, 76) disposed within a semiconductor substrate (10), wherein the well region (60, 70, 72, 74, 76) comprises a plurality of first regions (60, 70, 72) separated by a plurality of second regions (74, 76), wherein the plurality of first (60, 70, 72) and second (74, 76) regions have a first doping type (P) and different doping concentrations relative to one another; a gate stack (14) overlying the well region (60, 70, 72, 74, 76) wherein the plurality of first regions (60, 70, 72) extends vertically beneath the gate stack (14) from a bottom surface of the gate stack (14) to a bottom surface of the well region (60, 70, 72, 74, 76) and the plurality of second regions (74, 76) extends vertically beneath the gate stack (14) from the bottom surface of the gate stack (14) to the bottom surface of the well region (60, 70, 72, 74, 76); and a source (16) and a drain (18) having a second doping type (N) that is different than the first doping type (P), wherein from a top view, between outer edges of the well region (60, 70, 72, 74, 76) and across a length of the well region (60, 70, 72, 74, 76) that is in a direction where the gate stack (14) separates the source (16) from the drain (18) and at an interior of the well region (60, 70, 72, 74, 76), outer sidewalls of each of the plurality of first regions (60, 70, 72) at the interior of the well region (60, 70, 72, 74, 76) are entirely bordered by the plurality of second regions (74, 76), and outer sidewalls of each of the plurality of second regions (74, 76) at the interior of the well region (60, 70, 72, 74, 76) are entirely bordered by the plurality of first regions (60, 70, 72) (See Fig. 8, Column 2, lines 51-67, Column 8, lines 34-58) (Notes: GaAs is a well-known III-V semiconductor material). As to claim 10, Terada further discloses wherein the plurality of first regions (60, 70, 72) are of a first doping concentration (p) and the plurality of second regions (74, 76) are of a second doping concentration (p+) different than the first doping concentration (p) (See Fig. 8). As to claim 11, Terada further discloses wherein the plurality of second regions (74, 76) extends laterally past an outer edge of the gate stack (14) (See Fig. 8). As to claim 12, Terada further discloses wherein the source (16) or the drain (18) are laterally offset from the gate stack (14) wherein the plurality of first regions (60, 70, 72) or the plurality of second regions (74, 76) extend from a bottom surface of the source (16) or the drain (18) to the bottom surface of the well region (60, 70, 72, 74, 76); and the plurality of first regions (60, 70, 72) or the plurality of second regions (74, 76) extend laterally past an outer edge of the source (16) or the drain (18) (See Fig. 8). As to claim 13, Terada discloses further comprising a first top surface of the plurality of first regions (60, 70, 72) aligned beneath the gate stack (14) and a second top surface of the plurality of first regions (60, 70, 72) laterally offset from the gate stack (14) wherein the second top surface of the plurality of first regions (60, 70, 72) is below the first top surface of the plurality of first regions (60, 70, 72) (See Fig. 8). As to claim 14, Terada discloses further comprising a conductive contact (20, 22) aligned over the second top surface (See Fig. 8). As to claim 16, Terada further discloses wherein outermost edges of the plurality of first regions (60, 70, 72) laterally extends from outside of an outer edge of the gate stack (14) to a region within the outer edge of the gate stack (14) (See Fig. 8).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 8 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent No. 4,803,526 to Terada et al. (“Terada”) as applied to claim 1 above, and further in view of U.S. Patent Application Publication No. 2003/0230786 A1 to Kim et al. (“Kim”). The teaching of Terada has been discussed above. As to claim 8, although Terada does not further disclose a shallow trench isolation (STI) structure disposed within the semiconductor substrate, Terada in view of Kim discloses further comprising a shallow trench isolation (STI) structure (110) disposed within the semiconductor substrate (10/100), wherein one of the plurality of first regions (60, 70, 72) laterally separates the STI structure (110) from one of the plurality of second regions (74, 76) or one of the plurality of second regions (74, 76) laterally separates the STI structure (110) from one of the plurality of the plurality of second regions (74, 76) (See Terada Fig. 8 and Kim Fig. 1, ¶ 0039), where the STI structure is known to define the active region.
Allowable Subject Matter
Claims 17-18, 20, and 23 are allowed.
Claims 21-22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments with respect to claims 1 and 9 have been considered but are moot in view of the new ground(s) of rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID CHEN whose telephone number is (571)270-7438. The examiner can normally be reached M-F 12-6.
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/DAVID CHEN/Primary Examiner, Art Unit 2815