Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of group I, claims 1-14, 21-26 in the reply filed on 11/21/25 is acknowledged.
Information Disclosure Statement
The information disclosure statements filed 1/24/25; 8/1/23 have been considered.
Oath/Declaration
Oath/Declaration filed on 8/1/23 has been considered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-6 is/are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Chen et al. (U.S. Patent Publication No. 2024/0413028).
Referring to figures 1-20, Chen et al. teaches method of manufacturing a semiconductor device, the method comprising:
singulating a first wafer to separate a first die of the first wafer from a second die of the first wafer (see paragraph# 18);
bonding the first die (50a) and the second die (50b) to a first side of a second wafer, (110) wherein after bonding the first die and the second die to the first side of the second wafer, a gap is disposed between the first die and the second die, wherein a first dielectric layer (62/122) of each of the first die and the second die is directly bonded to a second dielectric layer (62/122) of the second wafer, and wherein a first portion of the gap has a first width that is larger than a second width of a second portion of the gap (see figures 3, 19, paragraph# 28, 62-63);
depositing a third dielectric layer (130) on top surfaces and sidewalls of the first die and the second die, as well as on a bottom surface within the gap;
forming a molding material (132, 134) over the third dielectric layer to fill the gap;
performing a planarization process to expose top surfaces of the first die and the second die (see figures 6, 19); and
coupling a package substrate to a second side of the second wafer using conductive connectors, the second side of the second wafer being an opposite side of the second wafer as the first side of the second wafer (see figures 9, 19).
Regarding to claim 2, the third dielectric layer comprises silicon oxide, silicon oxynitride, silicon carbon nitride or tetraethyl orthosilicate (see paragraph# 33).
Regarding to claim 3, wherein a thickness of the third dielectric layer is in a range from 0.1 µm to 2 µm (see paragraph# 33).
Regarding to claim 4, wherein a material of the third dielectric layer (SiO2, see paragraph# 33) is different from a material of the first dielectric layer and the second dielectric layer (PSG, see paragraph# 21).
Regarding to claim 5, wherein performing the planarization process further comprises removing a portion of the third dielectric layer and a portion of the molding material, wherein after performing the planarization process, the top surfaces of the first die and the second die are level with top surfaces of the third dielectric layer and the molding material (see figures 6-19, paragraphs# 38).
Regarding to claim 6, after performing the planarization process, attaching a carrier substrate to the top surfaces of the first die and the second die, and the planarized surfaces of the third dielectric layer and the molding material; and thinning a back side of a substrate of the second wafer to expose through substrate vias (TSVs) within the second wafer (see figure 8, paragraph# 42).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 8-11, 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (U.S. Patent Publication No. 2024/0413028) in view of Chen et al. (U.S. Patent Publication No. 2021/0375826).
Referring to figures 1-20, Chen et al. teaches a method of manufacturing a semiconductor device, the method comprising:
bonding the first die (50a) and the second die (50b) to a first side of a second wafer, (110) wherein after bonding the first die and the second die to the first side of the second wafer, a gap is disposed between the first die and the second die, , and wherein a first portion of the gap has a first width that is larger than a second width of a second portion of the gap (see figures 3, 19, paragraph# 28, 62-63);
depositing a first dielectric layer (130) on top surfaces and sidewalls of the first die and the second die, as well as on a bottom surface within the gap;
forming a molding material (132, 134) over the third dielectric layer to fill the gap;
planarizing the molding material such that the top surface of the molding material is level with top surfaces of the adjacent dies of the plurality of dies (see figures 6, 19).
However, the reference does not clearly teach a gap is disposed between adjacent dies of the plurality of dies, wherein a top portion of the gap has a larger width than a width of a bottom portion of the gap (in claim 8).
Chen et al. teaches a gap is disposed between adjacent dies of the plurality of dies, wherein a top portion of the gap has a larger width than a width of a bottom portion of the gap (see figure 2d).
Therefore, it would have been obvious to a person of ordinary skill in the requisite art at the time of the invention was file would form a gap is disposed between adjacent dies of the plurality of dies, wherein a top portion of the gap has a larger width than a width of a bottom portion of the gap in Chen et al. as taught by Chen et al. because the process is known in the art provide isolation between the dies.
Regarding to claim 9, wherein the first dielectric layer (130) isolates the molding material from the sidewalls of the adjacent dies, and from a top surface of the wafer within the gap.
(see figure 6).
Regarding to claim 10, wherein a thickness of the first dielectric layer is in a range from 0.1 µm to 2 µm (see paragraph# 33).
Regarding to claim 11, planarizing the first dielectric layer such that a top surface of the first dielectric layer is level with the top surface of the molding material and the top surfaces of the adjacent dies of the plurality of dies (see figures 6, 19).
Regarding to claim 14, the first dielectric layer comprises an oxide (see paragraph# 33).
Claim 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (U.S. Patent Publication No. 2024/0413028) in view of Chen et al. (U.S. Patent Publication No. 2021/0375826) as applied to claims 8-11, 14 above, further in view of Chiu et al. (U.S. Patent Publication No. 2017/0323840).
Referring to figures 1-20, Chen et al. teaches a method of manufacturing a semiconductor device, the method comprising:
bonding the first die (50a) and the second die (50b) to a first side of a second wafer, (110) wherein after bonding the first die and the second die to the first side of the second wafer, a gap is disposed between the first die and the second die, and wherein a first portion of the gap has a first width that is larger than a second width of a second portion of the gap (see figures 3, 19, paragraph# 28, 62-63);
depositing a first dielectric layer (130) on top surfaces and sidewalls of the first die and the second die, as well as on a bottom surface within the gap;
forming a molding material (132, 134) over the third dielectric layer to fill the gap;
planarizing the molding material such that the top surface of the molding material is level with top surfaces of the adjacent dies of the plurality of dies (see figures 6, 19).
However, the reference does not clearly teach each of the plurality of dies comprises: a top portion having a first width; and a bottom portion having a second width, the second width being larger than the first width (in claim 12).
Chiu et al. teaches each of the plurality of dies comprises: a top portion having a first width; and a bottom portion having a second width, the second width being larger than the first width (see figure 3a).
Therefore, it would have been obvious to a person of ordinary skill in the requisite art at the time of the invention was file would each of the plurality of dies comprises: a top portion having a first width; and a bottom portion having a second width, the second width being larger than the first width in Chen et al. as taught by Chiu et al. because the process is known in the art reduce the stress suffered by the molded device dies (see paragraph# 46).
Chen et al. teaches Regarding to claim 13, after planarizing the molding material, the first dielectric layer (130) is in physical contact with top surfaces of the bottom portion of each of the plurality of dies (50a, 50b, see figure 19).
Claims 7, 21, 23-26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (U.S. Patent Publication No. 2024/0413028) in view of Wu et al. (U.S. Patent Publication No. 2024/0096848).
Referring to figures 4-20, Chen et al. teaches a method of manufacturing a semiconductor device, the method comprising:
singulating a first wafer to separate a first die of the first wafer from a second die of the first wafer (see paragraph# 18);
bonding the first die (50a) and the second die (50b) to a first side of a second wafer, (110) wherein after bonding the first die and the second die to the first side of the second wafer, a gap is disposed between the first die and the second die, , and wherein a first portion of the gap has a first width that is larger than a second width of a second portion of the gap (see figures 3, 19, paragraph# 28, 62-63);
depositing a first dielectric layer (130) on top surfaces of the first die and the second die, and on sidewalls of the first dies and the second die within the gap, wherein the first dielectric layer fill a bottom portion of the gap; and
forming a molding material (132, 134) over the first dielectric layer to fill top portion of the gap (see figures 6, 19).
However, the reference does not clearly teach wherein singulating the first wafer comprises: performing a plasma dicing process on a first side of the first wafer to form a first groove and a second groove that are disposed between adjacent sidewalls of the first die and the second die; and performing a blade dicing process on a second side of the first wafer to form a trench, wherein the trench overlaps and connects to the first groove and the second groove.
Wu et al. teaches singulating the first wafer comprises: performing a plasma dicing process on a first side of the first wafer to form a first groove and a second groove that are disposed between adjacent sidewalls of the first die and the second die; and performing a blade dicing process on a second side of the first wafer to form a trench, wherein the trench overlaps and connects to the first groove and the second groove (see paragraphs# 11, figures 1-7, meeting claims 7, 21).
Therefore, it would have been obvious to a person of ordinary skill in the art at the time of the invention was filed would performing a plasma dicing process on a first side of the first wafer to form a first groove and a second groove that are disposed between adjacent sidewalls of the first die and the second die; and performing a blade dicing process on a second side of the first wafer to form a trench, wherein the trench overlaps and connects to the first groove and the second groove in Chen et al. as taught by Wu et al. because it would reduce damage and less physical impact to the bonding layer (see paragraph# 11).
Regarding to claim 23, the first dielectric layer (130) isolates the molding material from the sidewalls of the adjacent dies, and from a top surface of the wafer within the gap.
(see figure 6).
Regarding to claim 24, the first dielectric layer comprises an oxide (see paragraph# 33).
Regarding to claim 25, wherein a thickness of the first dielectric layer is in a range from 0.1 µm to 2 µm (see paragraph# 33).
Regarding to claim 26, planarizing the first dielectric layer such that a top surface of the first dielectric layer is level with a top surface of the molding material and top surfaces of the first die and the second die (see figures 6, 19).
Claim 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (U.S. Patent Publication No. 2024/0413028) in view of Wu et al. (U.S. Patent Publication No. 2024/0096848) as applied to claims 21, 23-26, and further in view of Chen et al. (U.S. Patent Publication No. 2021/0375826).
Referring to figures 1-20, Chen et al. teaches a method of manufacturing a semiconductor device, the method comprising:
bonding the first die (50a) and the second die (50b) to a first side of a second wafer, (110) wherein after bonding the first die and the second die to the first side of the second wafer, a gap is disposed between the first die and the second die, , and wherein a first portion of the gap has a first width that is larger than a second width of a second portion of the gap (see figures 3, 19, paragraph# 28, 62-63);
depositing a first dielectric layer (130) on top surfaces and sidewalls of the first die and the second die, as well as on a bottom surface within the gap;
forming a molding material (132, 134) over the third dielectric layer to fill the gap;
performing a planarization process to expose top surfaces of the first die and the second die (see figures 6, 19); and
coupling a package substrate to a second side of the second wafer using conductive connectors, the second side of the second wafer being an opposite side of the second wafer as the first side of the second wafer (see figures 9, 19).
However, the reference does not clearly teach a gap is disposed between adjacent dies of the plurality of dies, wherein a top portion of the gap has a larger width than a width of a bottom portion of the gap (in claim 8).
Chen et al. teaches a gap is disposed between adjacent dies of the plurality of dies, wherein a top portion of the gap has a larger width than a width of a bottom portion of the gap (see figure 2d).
Therefore, it would have been obvious to a person of ordinary skill in the requisite art at the time of the invention was file would form a gap is disposed between adjacent dies of the plurality of dies, wherein a top portion of the gap has a larger width than a width of a bottom portion of the gap in Chen et al. as taught by Chen et al. because the process is known in the art provide isolation between the dies.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thanh Nguyen whose telephone number is (571) 272-1695, or by Email via address Thanh.Nguyen@uspto.gov. The examiner can normally be reached on Monday-Thursday from 6:00AM to 3:30PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Yara Green, can be reached on (571) 270-3035. The fax phone number for this Group is (571) 273-8300.
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/THANH T NGUYEN/Primary Examiner, Art Unit 2893
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